JP2884100B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2884100B2 JP2884100B2 JP3967490A JP3967490A JP2884100B2 JP 2884100 B2 JP2884100 B2 JP 2884100B2 JP 3967490 A JP3967490 A JP 3967490A JP 3967490 A JP3967490 A JP 3967490A JP 2884100 B2 JP2884100 B2 JP 2884100B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer wiring
- thickness
- psg
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、チップが二層配線構造を備えた半導体装置
に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device in which a chip has a two-layer wiring structure.
従来、半導体装置のチップの二層配線構造の第１層配
線と第２層配線の絶縁のための層間絶縁膜として、減圧
CVDによるPSG膜とプラズマCVDによるSiN膜を二層で使用
するものがある。Conventionally, as an interlayer insulating film for insulating a first-layer wiring and a second-layer wiring of a two-layer wiring structure of a chip of a semiconductor device, pressure reduction is performed.
Some use a PSG film formed by CVD and a SiN film formed by plasma CVD in two layers.
第１図は層間絶縁膜に減圧CVDによるPSG膜とプラズマ
CVDによるSiN膜を二層で使用した二層配線構造の一例を
示す。Fig. 1 PSG film and plasma by low pressure CVD for interlayer insulating film
An example of a two-layer wiring structure using two layers of SiN films by CVD is shown.
図において１はSi基板、２はフィードSiO2膜、３は第
１層配線（Al）、４は減圧CVDによるPSG膜、５はプラズ
マCVDによるSiN膜、６は第２層配線（Al）、７はパッシ
ベーション膜である。In the figure, 1 is a Si substrate, 2 is a feed SiO 2 film, 3 is a first layer wiring (Al), 4 is a PSG film formed by low pressure CVD, 5 is a SiN film formed by plasma CVD, 6 is a second layer wiring (Al), 7 is a passivation film.
従来、上記構造の二層配線構造において、減圧CVDに
よるPSG膜４とプラズマCVDによるSiN膜５の膜厚比が適
当でなく、絶縁膜にストレスが生じ、このストレスによ
り第２層配線６の金属膜が変形し、断線、短絡といった
不良を引き起こすことがあった。Conventionally, in the two-layer wiring structure having the above structure, the thickness ratio between the PSG film 4 formed by the low pressure CVD and the SiN film 5 formed by the plasma CVD is not appropriate, and a stress is generated in the insulating film. In some cases, the film was deformed, causing defects such as disconnection and short circuit.
本発明は上記の問題を解消するためになされたもの
で、第２層配線６の金属膜が変形し、断線、短絡といっ
た不良が生ずることのないものを提供することを目的と
する。The present invention has been made in order to solve the above-mentioned problem, and has as its object to provide a structure in which a metal film of the second-layer wiring 6 is not deformed and a defect such as disconnection or short circuit does not occur.
上記目的を達成するために、本発明は、層間絶縁膜に
生ずるストレスが極小になるように、層間絶縁膜のプラ
ズマCVDによるSiN膜５の膜厚を減圧CVDによるPSG膜４の
膜厚の7.8〜13.0倍にしたものである。In order to achieve the above object, the present invention is to reduce the thickness of the SiN film 5 by plasma CVD of the interlayer insulating film to 7.8 of the thickness of the PSG film 4 by low-pressure CVD so that the stress generated in the interlayer insulating film is minimized. It is up to 13.0 times.
以下、第１図により本発明の二層配線構造の実施例に
ついて説明する。Hereinafter, an embodiment of the two-layer wiring structure of the present invention will be described with reference to FIG.
第１層配線３上に減圧CVDにより厚さ1000ÅのPSG膜４
をデポし、さらにPSG膜４上にプラズマCVDにより厚さ10
000ÅのSiN膜５をデポし、このPSG膜４とSiN膜５を層間
絶縁膜とし、この層間絶縁膜上に第２層配線６を施した
ものでは、第２層配線６の金属膜に殆んど変形が認めら
れず、断線、短絡などが発生しないことが確認された。PSG film 4 having a thickness of 1000 に よ り by low pressure CVD on first layer wiring 3
And a thickness of 10 μm on the PSG film 4 by plasma CVD.
In the case where the SiN film 5 of 000 ° is deposited, the PSG film 4 and the SiN film 5 are used as an interlayer insulating film, and the second layer wiring 6 is formed on the interlayer insulating film, the metal film of the second layer wiring 6 is almost completely removed. No deformation was observed, and it was confirmed that no disconnection or short circuit occurred.
上記の例は、SiN膜５とPSG膜４の膜厚比（SiN膜厚/PS
G膜厚）を10としたものであるが、この膜厚比を7.8〜1
3.0の範囲にまで広げても、第２層配線６の金属膜に断
線、短絡などの不良が発生しないことが実験的に実証さ
れた。In the above example, the thickness ratio of the SiN film 5 to the PSG film 4 (SiN film thickness / PS
G film thickness) was 10, but this film thickness ratio was 7.8 to 1
It has been experimentally demonstrated that even when the thickness is increased to the range of 3.0, defects such as disconnection and short circuit do not occur in the metal film of the second layer wiring 6.
以上説明したとおり、本発明によれば、第２層配線の
金属膜に変性が生ずることがなくなり、断線、短絡など
の不良が発生しなくなり、歩留りが上り、信頼性が向上
するという効果がある。As described above, according to the present invention, the metal film of the second-layer wiring is prevented from being denatured, defects such as disconnection and short-circuit are not generated, the yield is increased, and the reliability is improved. .
第１図は層間絶縁膜に減圧CVDによるPSG膜とプラズマCV
DによるSiN膜を二層で使用した二層配線構造の一例を示
す説明図である。 １……Si基板、２……フィールドSiO2膜、３……第１層
配線、４……PSG膜、５……SiN膜、６……第２層配線、
７……パッシベーション膜Fig. 1 shows PSG film by low pressure CVD and plasma CV for interlayer insulating film.
FIG. 4 is an explanatory diagram showing an example of a two-layer wiring structure using a two-layered SiN film by D. 1 ... Si substrate, 2 ... Field SiO 2 film, 3 ... First layer wiring, 4 ... PSG film, 5 ... SiN film, 6 ... Second layer wiring,
7 ... Passivation film
Claims (1)
るPSG膜とプラズマCVDによるSiN膜を二層で使用する半
導体装置において、 SiN膜の膜厚をPSG膜の膜厚の7.8〜13.0倍にしたことを
特徴とする半導体装置。A semiconductor device in which a PSG film formed by low-pressure CVD and a SiN film formed by plasma CVD are used as two layers as an interlayer insulating film having a two-layer wiring structure, wherein the thickness of the SiN film is 7.8 to 13.0 times the thickness of the PSG film. A semiconductor device characterized in that it is doubled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3967490A JP2884100B2 (en) | 1990-02-22 | 1990-02-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3967490A JP2884100B2 (en) | 1990-02-22 | 1990-02-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03244144A JPH03244144A (en) | 1991-10-30 |
| JP2884100B2 true JP2884100B2 (en) | 1999-04-19 |
Family
ID=12559647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3967490A Expired - Fee Related JP2884100B2 (en) | 1990-02-22 | 1990-02-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2884100B2 (en) |
-
1990
- 1990-02-22 JP JP3967490A patent/JP2884100B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03244144A (en) | 1991-10-30 |
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