JPS61284928A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61284928A JPS61284928A JP12563785A JP12563785A JPS61284928A JP S61284928 A JPS61284928 A JP S61284928A JP 12563785 A JP12563785 A JP 12563785A JP 12563785 A JP12563785 A JP 12563785A JP S61284928 A JPS61284928 A JP S61284928A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- compressive stress
- plasma cvd
- dyne
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、最終保護膜あるいは多層配線の層間絶縁膜
として、プラズマCVD法で形成された窒化シリコン膜
を用いた半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device using a silicon nitride film formed by plasma CVD as a final protective film or an interlayer insulating film of multilayer wiring.
従来この種の装置として第4図に示すものがあった。図
において、1はPSG膜、2はアルミ合金配線、3は最
終保護膜で、プラズマCVD法で形成された窒化シリコ
ン膜である。A conventional device of this type is shown in FIG. In the figure, 1 is a PSG film, 2 is an aluminum alloy wiring, and 3 is a final protective film, which is a silicon nitride film formed by plasma CVD.
また従来の他の例を第5図に示す。図において、4は1
層目アルミ合金配線、5は層間絶縁膜、6は2層目アル
ミ合金配線、7は最終保護膜である。Another conventional example is shown in FIG. In the figure, 4 is 1
5 is an interlayer insulating film, 6 is a second layer aluminum alloy wiring, and 7 is a final protective film.
層間絶縁膜5及び最終保護膜7は、プラズマCVD法で
形成された窒化シリコン膜である。The interlayer insulating film 5 and the final protective film 7 are silicon nitride films formed by plasma CVD.
次に製造フローを第5図のアルミ2層配線構造について
説明する。1層目アルミ合金配線4の形成後、層間絶縁
膜5としてプラズマCVD法で窒化シリコン膜を堆積す
る。次に層間絶縁膜5に、1層目と2層目のアルミ合金
配線4,6を接続するためのスル−ホールをあけ、2層
目アルミ合金配線6を形成する。最後に、最終保護膜7
として、プラズマCVD法で窒化シリコン膜を堆積する
。Next, the manufacturing flow will be explained for the aluminum two-layer wiring structure shown in FIG. After forming the first layer aluminum alloy wiring 4, a silicon nitride film is deposited as an interlayer insulating film 5 by plasma CVD. Next, a through hole is made in the interlayer insulating film 5 to connect the first and second layer aluminum alloy wires 4 and 6, and a second layer aluminum alloy wire 6 is formed. Finally, the final protective film 7
Then, a silicon nitride film is deposited by plasma CVD.
このような半導体装置において、プラズマCVD法で形
成された窒化シリコン膜は、6〜12×109 dyn
e/ ca!という大きな圧縮性応力をもつので、最終
保護膜31.7あるいは多層配線の層間絶縁膜5として
用いると、窒化シリコン膜堆積時及びその後の熱処理工
程において、下層のアルミ合金配線2,4.6に対し、
機械的損傷を与え、例えば第6図及び第7図に示すよう
に、アルミ合金配線2に欠損部分8を生じさせる。In such a semiconductor device, a silicon nitride film formed by plasma CVD has a thickness of 6 to 12×109 dyn.
e/ca! Therefore, when used as the final protective film 31.7 or the interlayer insulating film 5 of multilayer wiring, the underlying aluminum alloy wiring 2, 4.6 will be damaged during the silicon nitride film deposition and subsequent heat treatment process. On the other hand,
Mechanical damage is caused, for example, as shown in FIGS. 6 and 7, a defective portion 8 is created in the aluminum alloy wiring 2.
また、この大きな圧縮性応力は、アルミ合金配線2.4
.6のマイグレーション耐性を著しく劣化させることが
わかっている。In addition, this large compressive stress is caused by aluminum alloy wiring 2.4
.. It is known that the migration resistance of 6 is significantly deteriorated.
従来の半導体装置は以上のように構成されており、プラ
ズマCVD法で形成された窒化シリコン膜は6〜12X
l 09dyne/cIl!という大きな圧縮性応力を
持つため、これを最終保護膜あるいは多層配線の層間絶
縁膜として用いると、下層のアルミ合金配線に対し機械
的FJM傷を及ぼしてアルミ合金配線の欠損現象を引き
起こしたり、配線のマイグレーション耐性の著しい劣化
を引き起こすという欠点があった。The conventional semiconductor device is constructed as described above, and the silicon nitride film formed by plasma CVD method has a thickness of 6 to 12X.
l 09dyne/cll! Because it has a large compressive stress, if it is used as a final protective film or an interlayer insulating film for multilayer wiring, it may cause mechanical FJM damage to the underlying aluminum alloy wiring, causing damage to the aluminum alloy wiring, or causing damage to the wiring. The drawback was that it caused a significant deterioration in migration resistance.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、アルミ合金配線の欠損現象が発生
せず、又マイグレーション耐性が高く、信頼性の高い半
導体装置を提供することを目的としている。This invention was made in order to eliminate the above-mentioned drawbacks of the conventional devices, and its purpose is to provide a highly reliable semiconductor device that does not cause defects in aluminum alloy wiring, has high migration resistance, and is highly reliable. It is said that
この発明は、最終保護膜あるいは層間絶縁膜として、プ
ラズマCVD法で形成された窒化シリコン膜を用いるよ
うにした半導体装置において、窒化シリコン膜を、その
圧縮応力が膜厚1μm換算で5 X 109 dyne
/crA以下のものとしたものである。This invention provides a semiconductor device in which a silicon nitride film formed by plasma CVD is used as a final protective film or an interlayer insulating film.
/crA or less.
この発明においては、窒化シリコン膜として圧縮性応力
の小さいものを用いたことから、窒化シリコン膜堆積時
あるいはその後の熱処理工程において下層のアルミ合金
配線が機械的損傷を受けることはほとんどなく、又アル
ミ合金配線のマイグレーション耐性もほとんど劣化する
ことはない。In this invention, since a silicon nitride film with low compressive stress is used, there is almost no mechanical damage to the underlying aluminum alloy wiring during deposition of the silicon nitride film or during the subsequent heat treatment process, and the aluminum The migration resistance of the alloy wiring also hardly deteriorates.
(実施例) 以下、本発明の実施例を図について説明する。(Example) Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例による半導体装置を示す。図
において、1はPSGHfA、2はアルミ合金配線、1
3は最終保護膜で、これは、プラズマCVD法で形成さ
れ、圧縮性応力を膜厚1μm換算で5 X 109 d
yne/ ad以下とした窒化シリコン膜である。FIG. 1 shows a semiconductor device according to an embodiment of the present invention. In the figure, 1 is PSGHfA, 2 is aluminum alloy wiring, 1
3 is the final protective film, which is formed by the plasma CVD method and has a compressive stress of 5 x 109 d when converted to a film thickness of 1 μm.
This is a silicon nitride film with a thickness of yne/ad or less.
次に作用効果について説明する。Next, the effects will be explained.
前述のアルミ合金配線の欠損現象は、プラズマCVD窒
化シリコン膜の圧縮性応力が大きいほど、また膜厚が大
きいほど発生しやすいわけであるが、膜厚が1μmのと
き、5 X 109 dyne/cIa以下の圧縮性応
力であれば欠損現象は発生しない。即ち、膜厚2μmの
ときは2.5 X 109 dyne/c1a以下、膜
厚0.5μmのときは10 X 109 dyne/c
ot以下であればよい。The above-mentioned defective phenomenon of aluminum alloy wiring occurs more easily as the compressive stress of the plasma CVD silicon nitride film increases and as the film thickness increases. If the compressive stress is below, the chipping phenomenon will not occur. That is, when the film thickness is 2 μm, it is 2.5 × 109 dyne/c1a or less, and when the film thickness is 0.5 μm, it is 10 × 109 dyne/c.
It is sufficient if it is less than or equal to ot.
通常の拡散炉型プラズマCVD装置において、膜形成温
度が300〜400℃の場合、1.0〜2゜OTorr
程度の圧力下で膜形成したプラズマCVD窒化膜は6〜
12 X 109 dyne/cJの圧縮性応力をもつ
。In a normal diffusion furnace type plasma CVD apparatus, when the film formation temperature is 300 to 400°C, the temperature is 1.0 to 2°OTorr.
The plasma CVD nitride film formed under a pressure of 6~
It has a compressive stress of 12 x 109 dyne/cJ.
このようなプラズマCVD窒化膜の圧縮性応力を小さく
する方法の1つとして、膜形成時の圧力を高くすること
が挙げられる。上記の例では、膜形成圧力を2.OTo
rr以上にすることにより、圧縮性応力を5 X 10
9 dyne/c4以下にすることができる。One way to reduce the compressive stress of such a plasma CVD nitride film is to increase the pressure during film formation. In the above example, the film forming pressure is set to 2. OTo
By increasing the compressive stress to 5 x 10
It can be reduced to 9 dyne/c4 or less.
以上のような本実施例の装置では、低応力のプラズマC
VD窒化膜を用いるようにしたので、アルミ合金配線の
欠損現象が発生せず、かつ配線のマイグレーション耐性
の劣化を防止できる。In the apparatus of this embodiment as described above, the low stress plasma C
Since the VD nitride film is used, the defect phenomenon of the aluminum alloy wiring does not occur, and deterioration of the migration resistance of the wiring can be prevented.
なお、上記実施例ではアルミ一層配線の最終保護膜に低
応力のプラズマCVD窒化シリコン膜を通用したものを
示したが、第2図に示すように、アルミニ層配線の層間
絶縁膜15.及び最終保護膜17に適用しても同じ効果
がある。In the above embodiment, a low-stress plasma CVD silicon nitride film was used as the final protective film for the single-layer aluminum wiring, but as shown in FIG. 2, the interlayer insulating film 15. The same effect can be obtained even when applied to the final protective film 17.
また、第3図に示すように、アルミニ層配線の層間絶縁
膜10として酸化シリコン膜、最終保護膜17として窒
化シリコン膜を用いる場合でも、2層目アルミ合金配線
6に与える機械的損傷を防ぐために、低応力の窒化シリ
コン膜を通用すれば、あるいは層間絶縁膜として用いら
れているプラズマCVD窒化シリコン膜の圧縮性応力を
膜厚1μm換算で5 X 109 dyne/cTA以
下としたので、アルミ合金配線の欠損現象を起こさず、
配線のマイグレーション耐性の高い半導体装置が得られ
る効果がある。Furthermore, as shown in FIG. 3, even when a silicon oxide film is used as the interlayer insulating film 10 of the aluminum layer wiring and a silicon nitride film is used as the final protective film 17, mechanical damage to the second layer aluminum alloy wiring 6 can be prevented. For this reason, it is possible to use a low-stress silicon nitride film, or because the compressive stress of the plasma CVD silicon nitride film used as an interlayer insulating film is 5 x 109 dyne/cTA or less when converted to a film thickness of 1 μm, an aluminum alloy can be used. Does not cause wiring defects,
This has the effect of providing a semiconductor device with high wiring migration resistance.
第1図は本発明の一実施例による半導体装置の断面図、
第2図は本発明の他の実施例の断面図、第3図は本発明
のさらに他の実施例の断面図、第4図及び第5図は各々
従来の半導体装置の断面図、第6図は従来の問題点を説
明するための平面図、第7図は第6図のA−A線断面図
である。
図において、13.17は最終保護膜、15は層間絶縁
膜である。
なお図中同一符号は同−又は相当部分を示す。
代理人 弁理士 早 瀬 憲 −第1図
13:、4さび躍層
第2図
15:麿67.11層1
17:pPay7H
第3図
第4図
第5図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
2 is a cross-sectional view of another embodiment of the present invention, FIG. 3 is a cross-sectional view of still another embodiment of the present invention, FIGS. 4 and 5 are cross-sectional views of a conventional semiconductor device, and FIG. The figure is a plan view for explaining the conventional problems, and FIG. 7 is a sectional view taken along the line A--A in FIG. 6. In the figure, 13 and 17 are final protective films, and 15 is an interlayer insulating film. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Patent Attorney Ken Hayase - Fig. 1 13:, 4 rustic layer Fig. 2 15: Maro 67.11 layer 1 17: pPay7H Fig. 3 Fig. 4 Fig. 5
Claims (1)
、プラズマCVD法で形成された窒化シリコン膜を用い
た半導体装置において、上記窒化シリコン膜はその圧縮
性応力が膜厚1μm換算で5×10^9dyne/cm
^2以下のものであることを特徴とする半導体装置。(1) In a semiconductor device using a silicon nitride film formed by plasma CVD as a final protective film or an interlayer insulating film of multilayer wiring, the silicon nitride film has a compressive stress of 5×10 when converted to a film thickness of 1 μm. ^9dyne/cm
A semiconductor device characterized in that it is ^2 or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12563785A JPS61284928A (en) | 1985-06-10 | 1985-06-10 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12563785A JPS61284928A (en) | 1985-06-10 | 1985-06-10 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61284928A true JPS61284928A (en) | 1986-12-15 |
Family
ID=14914955
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12563785A Pending JPS61284928A (en) | 1985-06-10 | 1985-06-10 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61284928A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0488632A (en) * | 1990-07-31 | 1992-03-23 | Murata Mfg Co Ltd | Formation of protective film for heat treatment |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52115785A (en) * | 1976-01-22 | 1977-09-28 | Western Electric Co | Process for coating substrate |
JPS59114829A (en) * | 1982-12-21 | 1984-07-03 | Agency Of Ind Science & Technol | Formation of silicon nitride film |
-
1985
- 1985-06-10 JP JP12563785A patent/JPS61284928A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52115785A (en) * | 1976-01-22 | 1977-09-28 | Western Electric Co | Process for coating substrate |
JPS59114829A (en) * | 1982-12-21 | 1984-07-03 | Agency Of Ind Science & Technol | Formation of silicon nitride film |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0488632A (en) * | 1990-07-31 | 1992-03-23 | Murata Mfg Co Ltd | Formation of protective film for heat treatment |
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