JPS62242331A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62242331A JPS62242331A JP8552886A JP8552886A JPS62242331A JP S62242331 A JPS62242331 A JP S62242331A JP 8552886 A JP8552886 A JP 8552886A JP 8552886 A JP8552886 A JP 8552886A JP S62242331 A JPS62242331 A JP S62242331A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- nitride film
- wiring
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000005360 phosphosilicate glass Substances 0.000 claims description 14
- 239000010410 layer Substances 0.000 abstract description 17
- 230000001681 protective effect Effects 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 12
- 239000011229 interlayer Substances 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 238000005245 sintering Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract 3
- 239000011574 phosphorus Substances 0.000 abstract 3
- 150000004767 nitrides Chemical class 0.000 abstract 2
- 239000005368 silicate glass Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置特にその半導体素子の表面保護膜
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a surface protective film of a semiconductor element thereof.
本発明は、半導体素子の表面を保護する表向保Ｎ膜とし
て、シリコン窒化膜とリンシリケートガラスとシリコン
窒化膜の３層構造の膜を用いることによって、耐湿性を
向上し、また＾ｌ配線の欠損を防止するようにしたもの
である。The present invention improves moisture resistance by using a film with a three-layer structure of a silicon nitride film, phosphosilicate glass, and a silicon nitride film as a surface N retaining film that protects the surface of a semiconductor element. It is designed to prevent loss of.
第３図は従来の半導体集積回路の製造プロセスの一例を
示す。この例では、半導体基体（１）に所要の半導体素
子を形成した後、絶縁層を介して第１の＾Ｅ配線（２）
が形成される（第３図Ａ）。次に第１の＾ｌ配線（２）
を含んでリンシリケートガラス（３）とプラズマ・シリ
コン窒化膜（４）とからなる晴間絶縁１’＄ ＋５１を
形成しく第３図Ｂ）、この層間絶縁膜（５）上に第２の
＾ｌ配線（６）が形成される（第３図Ｃ）。FIG. 3 shows an example of a conventional semiconductor integrated circuit manufacturing process. In this example, after the required semiconductor elements are formed on the semiconductor substrate (1), the first ^E wiring (2) is formed through the insulating layer.
is formed (Fig. 3A). Next, the first ^l wiring (2)
A clear insulation layer 1'$+51 consisting of phosphosilicate glass (3) and plasma silicon nitride film (4) is formed (Fig. 3B), and a second interlayer insulation film (5) is formed on this interlayer insulation film (5). A wiring (6) is formed (FIG. 3C).
次にリンシリケートガラス（７）とプラズマ・シリコン
窒化膜（８）からなる表面保護膜（９）が被着形成され
（第３図Ｄ）、その後シンタリング処理される。Next, a surface protection film (9) consisting of phosphosilicate glass (7) and plasma silicon nitride film (8) is deposited (FIG. 3D), and then sintered.
又、Ａ１配線が一層の場合の表向保！！膜も、リンシリ
ケートガラス（７）とプラズマ・シリコン窒化膜（８）
の２層構造膜（９）が用いられていた。Also, when the A1 wiring is one layer, the surface is protected! ! The films are phosphosilicate glass (7) and plasma silicon nitride film (8).
A two-layer structure film (9) was used.
上述した従来の半導体集積回路においては、表面保護膜
（９）の熱処理工程や、最終のシンタリング工程におい
て、Ａｌ配線の１部に欠損が生じ、特に２［＾ｌ配線構
造では第２の＾ｌ配線（６）の１部が消失し、また表面
保護膜（９）にクランクが入る等、信頼性が低下するも
のであった。In the conventional semiconductor integrated circuit described above, defects occur in a portion of the Al wiring during the heat treatment process of the surface protection film (9) and the final sintering process, and especially in the 2[^l wiring structure, the second^ A portion of the l wiring (6) was lost, and the surface protective film (9) was cracked, resulting in a decrease in reliability.
本発明は、上述の点に鑑み、表面保護膜を改善し°ζ信
頼性の高い半導体装置を提供するものである。In view of the above-mentioned points, the present invention provides a semiconductor device with improved surface protection film and high reliability.
本発明による半導体装置は、半導体素子のＡＩ！配線Ｃ
２）（又は（６））が形成された表面の表面保ｉＩ膜と
してシリコン窒化膜（１１）とリンシリケートガラス（
１２）とシリコン窒化膜（１３）の３層構造の膜（１４
）を用いて成るものである。多層配線を構成する場合に
は、層間絶縁膜（５）を形成した後、又は上層へ！配線
（６）を形成した後に熱処理を施し、その後最終的に上
記３層構造による表面保護膜（１４）を形成して構成す
る。The semiconductor device according to the present invention is an AI! Wiring C
Silicon nitride film (11) and phosphosilicate glass (
12) and a silicon nitride film (13).
). When configuring multilayer wiring, after forming the interlayer insulating film (5) or to the upper layer! After the wiring (6) is formed, heat treatment is performed, and then finally the surface protection film (14) having the three-layer structure is formed.
表面保護膜をシリコン窒化膜（１１）とリンシリケート
ガラス（１２）とシリコン窒化１％（１３）の３層構造
のｌ？（１４）で構成することにより、表面像Ｗｔ膜形
成後の熱処理においてへｌ配線の欠損が生ぜず、また表
面保護膜のクラック発生が回避され耐湿性が向上する。The surface protective film has a three-layer structure of silicon nitride film (11), phosphosilicate glass (12), and 1% silicon nitride (13). By configuring (14), no loss of the F1 wiring occurs in the heat treatment after the formation of the surface image Wt film, and cracks in the surface protective film are avoided, resulting in improved moisture resistance.
これはシリコン窒化１！ｉｉ！（１１）とリンシリケー
トガラス（１２）とシリコン窒化膜（１３）の３層構造
により、＾ｌ膜と表面保噌膜とのストレスが減少したこ
とによると考えられる。This is silicon nitride 1! ii! This is thought to be due to the three-layer structure of (11), phosphosilicate glass (12), and silicon nitride film (13), which reduced the stress on the ^l film and the surface protective film.
多層配線の場合、層間絶縁膜（５）を形成した後に熱処
理を行うと、より効果を高めることができる。In the case of multilayer wiring, the effect can be further enhanced by performing heat treatment after forming the interlayer insulating film (5).
以Ｆ、図面を参照して本発明による半導体装置の実施例
を説明する。Hereinafter, embodiments of a semiconductor device according to the present invention will be described with reference to the drawings.
第１図は２層ＡＪ配線構造の半導体集積回路の例を工程
順に示したものである。FIG. 1 shows an example of a semiconductor integrated circuit having a two-layer AJ wiring structure in the order of steps.
先ず、第１図Ａに丞すように半導体基体（１１に所要の
半導体素子を形成した後、絶縁層を介して第１のへｌ配
線（２）を形成する０次に第１図Ｂに示すように第１の
ＡＮ配線（２）を含む表面に例えば０．６μｍ厚のリン
シリケートガラス（３）と ０．１μ−厚のプラズマ・
シリコン窒化膜（４）からなる層間絶縁膜（５）をＣＶ
Ｄ （化学気相成長）法で被着形成し°ｒ１ｉｉ、例え
ば４００℃程度の熱処理を施す（第１１ｇＩＣ）。次に
、第１図りに示すように層間絶縁膜（５）上に第２のＡ
！配線（６）を形成する。次に第１図Ｅにポずように例
えば０．１μ端厚のプラズマ・シリコン窒化ＩＩ（１１
）と例えば０．６μ■厚のリンシリケートガラス（１２
）と例えば０．３μ端厚のプラズマ・シリコン窒化ＩＩ
！！（１３）からなる３Ｍ構造の表面保護膜（１４）を
ＣＶＤ法にて被着形成する。この後シンタリング処理が
施される。First, as shown in FIG. 1A, the required semiconductor elements are formed on the semiconductor substrate (11), and then the first wiring (2) is formed through the insulating layer. As shown, the surface containing the first AN wiring (2) is coated with, for example, 0.6 μm thick phosphosilicate glass (3) and 0.1 μm thick plasma glass.
The interlayer insulating film (5) made of silicon nitride film (4) is CV
D (Chemical Vapor Deposition) method is used to deposit and heat treatment is performed at, for example, about 400° C. (11th IC). Next, as shown in the first diagram, a second A is applied on the interlayer insulating film (5).
! A wiring (6) is formed. Next, as shown in FIG. 1E, for example, plasma silicon nitride II (11
) and, for example, 0.6 μ■ thick phosphosilicate glass (12
) and plasma silicon nitride II with an edge thickness of 0.3μ, for example.
! ! A surface protective film (14) having a 3M structure consisting of (13) is deposited by CVD. After this, a sintering process is performed.
斯る構成によれば、層間絶縁膜（５）の形成後に熱処理
を加え、さらに表面保護膜（１４）をプラズマ・シリコ
ン窒化膜（１１）−リンシリケートガラス（１２）−プ
ラズマ・シリコン窒化ＩＱ（１３）の膜構造としたこと
により、コンタクト窓あけ後のシンタリング処理でも、
第２のへ！配線（６）の欠損がなく、また表面保護Ｎｕ
（１４）のクラックも生じないことが認められた。According to this configuration, heat treatment is applied after the formation of the interlayer insulating film (5), and the surface protective film (14) is formed by forming the plasma silicon nitride film (11) - phosphosilicate glass (12) - plasma silicon nitride IQ ( 13) By adopting the film structure, even in the sintering process after opening the contact window,
To the second one! There is no damage to the wiring (6), and the surface is protected by Nu.
It was also observed that no cracks (14) were generated.
第２図は１層の＾ｌ配線に適用した場合である。FIG. 2 shows a case where the method is applied to one layer of ^l wiring.
本例においても、＾ｐ配線（２）を形成した後、０．１
．ｕｓ厚のプラズマ・シリコン窒化膜（１１）と０．６
μｍ厚のリンシリケートガラス（１２）と０．３μ端厚
のプラズマ・シリコン窒化膜（１３）からなる表向保護
１ｌｌｉ（１４）を被着形成する。この場合も、表面保
護膜（１４）によって、Ａ７！配線（２）の欠損が防止
され、また表面保護膜のクランク発生が回避される。Also in this example, after forming the ^p wiring (2), 0.1
．． Plasma silicon nitride film (11) with a thickness of 0.6
A surface protection layer (14) consisting of phosphosilicate glass (12) with a thickness of .mu.m and a plasma silicon nitride film (13) with an end thickness of 0.3 .mu.m is deposited. In this case as well, the surface protective film (14) protects A7! Breakage of the wiring (2) is prevented, and cranking of the surface protective film is also avoided.
上述せる本発明によれば、ＡＮ配線が形成された半導体
素子の表面保護膜として、シリコン窒化膜とリンシリケ
ートガラスとシリコン窒化膜の３層構造の膜を用いるこ
とにより、熱処理工程でのＡＪ配線の欠損が防止され、
また表面保護膜の耐湿性が向上する。従って、信頼性の
高い半導体装置が得られる。According to the present invention described above, by using a film with a three-layer structure of a silicon nitride film, phosphosilicate glass, and a silicon nitride film as a surface protection film of a semiconductor element on which an AN wiring is formed, the AJ wiring in a heat treatment process can be protected. loss of is prevented,
Moreover, the moisture resistance of the surface protective film is improved. Therefore, a highly reliable semiconductor device can be obtained.
第１図Ａ−Ｅば本発明の半導体装置の一例を示す製造工
程順の断面図、第２図は本発明の半導体装置の他の例を
示す断面図、第３図Ａ−Ｄは従来の半導体装置の例を示
す製造工程順の断面図である。
（］）は半導体基体、（２１＋６１はＡｌｌ配線、（５
）は層間絶縁膜、（１１）はシリコン窒化膜、（１２）
はリンシリケートガラス、（１３）はシリコン窒化膜、
（１４）は表曲保ｗｌ膜である。1A-E are cross-sectional views showing one example of the semiconductor device of the present invention in the order of manufacturing steps, FIG. 2 is a cross-sectional view showing another example of the semiconductor device of the present invention, and FIGS. 3A-D are cross-sectional views of conventional semiconductor devices. FIG. 3 is a cross-sectional view showing an example of a semiconductor device in the order of manufacturing steps. (]) is the semiconductor substrate, (21+61 is All wiring, (5
) is an interlayer insulating film, (11) is a silicon nitride film, (12)
is phosphosilicate glass, (13) is silicon nitride film,
(14) is a surface curved membrane.
Claims (1)
リケートガラスとシリコン窒化膜の３層構造の膜を用い
て成る半導体装置。A semiconductor device that uses a three-layered film of a silicon nitride film, phosphosilicate glass, and a silicon nitride film as a surface protection film for a semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8552886A JPS62242331A (en) | 1986-04-14 | 1986-04-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8552886A JPS62242331A (en) | 1986-04-14 | 1986-04-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62242331A true JPS62242331A (en) | 1987-10-22 |
Family
ID=13861387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8552886A Pending JPS62242331A (en) | 1986-04-14 | 1986-04-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62242331A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523616A (en) * | 1993-10-29 | 1996-06-04 | Nec Corporation | Semiconductor device having laminated tight and coarse insulating layers |
| US5592024A (en) * | 1993-10-29 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
| US5627403A (en) * | 1993-05-31 | 1997-05-06 | Sgs-Thomson Microelectronics S.R.L. | Adhesion between dielectric layers in an integrated circuit |
| US5688724A (en) * | 1992-07-02 | 1997-11-18 | National Semiconductor Corporation | Method of providing a dielectric structure for semiconductor devices |
| USRE39932E1 (en) | 1996-09-10 | 2007-12-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor interconnect formed over an insulation and having moisture resistant material |
| US8367541B2 (en) | 2005-03-30 | 2013-02-05 | Fujitsu Semiconductor Limited | Semiconductor device suitable for a ferroelectric memory and manufacturing method of the same |
| WO2021162752A1 (en) * | 2020-02-12 | 2021-08-19 | Raytheon Company | Process to yield ultra-large integrated circuits and associated integrated circuits |
-
1986
- 1986-04-14 JP JP8552886A patent/JPS62242331A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5688724A (en) * | 1992-07-02 | 1997-11-18 | National Semiconductor Corporation | Method of providing a dielectric structure for semiconductor devices |
| US5627403A (en) * | 1993-05-31 | 1997-05-06 | Sgs-Thomson Microelectronics S.R.L. | Adhesion between dielectric layers in an integrated circuit |
| US5523616A (en) * | 1993-10-29 | 1996-06-04 | Nec Corporation | Semiconductor device having laminated tight and coarse insulating layers |
| US5592024A (en) * | 1993-10-29 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
| US6794286B2 (en) | 1993-10-29 | 2004-09-21 | Kabushiki Kaisha Toshiba | Process for fabricating a metal wiring and metal contact in a semicondutor device |
| USRE39932E1 (en) | 1996-09-10 | 2007-12-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor interconnect formed over an insulation and having moisture resistant material |
| USRE41980E1 (en) | 1996-09-10 | 2010-12-07 | Panasonic Corporation | Semiconductor interconnect formed over an insulation and having moisture resistant material |
| US8367541B2 (en) | 2005-03-30 | 2013-02-05 | Fujitsu Semiconductor Limited | Semiconductor device suitable for a ferroelectric memory and manufacturing method of the same |
| WO2021162752A1 (en) * | 2020-02-12 | 2021-08-19 | Raytheon Company | Process to yield ultra-large integrated circuits and associated integrated circuits |
| US11189558B2 (en) | 2020-02-12 | 2021-11-30 | Raytheon Company | Process to yield ultra-large integrated circuits and associated integrated circuits |
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