JPS63198357A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an electrode wiring part at a contact part from being disconnected, by a method wherein an opening for contact use is filled with a polycrystalline silicon layer and, in addition, a metal wiring part is formed, via a barrier layer, on the surface of a refractory metal silicide layer which has been formed on the surface of the polycrystalline silicon layer. CONSTITUTION:An insulating film 2, an N-type diffusion region 3 and an interlayer insulating layer 4 are formed on a P-type silicon substrate 1; an opening for contact use is made at the interlayer insulating layer 4 on the diffusion region 3; a polycrystalline silicon layer 5 containing phosphorus is formed on the layer 4. Then, the layer 5 is removed by an anisotropic etching method in such a way that the polycrystalline silicon layer 5 is left only at the inside of the opening; a titanium layer 6 is formed on the whole surface by a sputtering method. Then, this assembly is heat-treated; the titanium layer 6 which comes into contact with the layer 5 is made to react; a titanium silicide layer 7 is formed; the unreacted titanium layer 6 is removed by etching. Then, this assembly is heat-treated in an atmosphere of ammonia; a barrier layer composed of a titanium nitride layer 8 is formed on the surface of the layer 7; a wiring part 9, which comes into contact with the layer 8 and is extended on the interlayer insulating film 4, is formed selectively. By this setup, the disconnection at the stepped part at the opening can be prevented.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

As semiconductor devices become more highly integrated, there is a need for electrode wiring techniques that have low contact resistance and do not cause disconnections due to steps.

In a conventional semiconductor device, a glabellar insulating layer is provided on a semiconductor substrate having an element region, a contact opening is provided in the interlayer insulating layer on the element region, and a contact opening is provided on the interlayer insulating layer including the opening. Then, an aluminum film containing 1 to 2% silicon for preventing contact failure is formed by sputtering, and the aluminum film is selectively etched to form an electrode wiring in contact with the element region.

[Opening point that the invention seeks to solve]

The above-described conventional semiconductor devices have a problem in that as the degree of integration increases and the contact openings become finer, step coverage deteriorates and wire breaks are more likely to occur due to the step differences in the openings. Another problem is that when the silicon contained in the aluminum wiring returns to room temperature after heat treatment, excess silicon precipitates in the form of particles at the contact portion, increasing contact resistance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having wiring that has low contact resistance and prevents disconnection at the step of an opening.

[Means for solving problems]

The semiconductor device of the present invention includes a glabella insulating layer formed on a semiconductor substrate on which a semiconductor element region is formed, and a multilayer insulating layer formed in an opening provided in the interlayer insulating layer that contacts the element region and is provided only in the opening. a crystalline silicon layer, a high melting point metal silicide layer provided on the polycrystalline silicon layer, a barrier layer provided on the surface of the high melting point metal silicide layer, and a layer in contact with the barrier layer and on the interlayer insulating layer. The structure includes a metal wiring formed so as to extend from the top to the bottom.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in Figure 1(a), P with a specific resistance of 1Ω
An insulating film 2 is selectively provided on one main surface of the silicon substrate 1, and an N-type diffusion region 3 with a depth of about 0.3 μm is formed on the surface of the P-type silicon substrate 1 using the insulation M2 as a mask. A glabellar insulating layer 4 having a thickness of 1 μm is formed. Next, a 1 μm x 1 μm contact opening is provided in the interlayer insulating layer 4 above the N-type diffusion region 3, and a C
A polycrystalline silicon layer 5 containing phosphorus having a film thickness of 0.61 Lm is formed by the VD method.

Next, as shown in FIG. 1(b), the polycrystalline silicon layer 5 on the interlayer insulating layer 4 is removed by an anisotropic etching method, leaving the polycrystalline silicon layer 5 only in the opening. A titanium layer 6 having a thickness of 0.05 μm is formed by sputtering.

Next, as shown in FIG. 1(c), heat treatment is performed at 600° C. to react the titanium layer 6 in contact with the polycrystalline silicon layer 5 in the opening to form a titanium silicide layer 7, Unreacted titanium layer 6 is removed by etching.

Next, as shown in FIG. 1(d), heat treatment is performed in an ammonia atmosphere at 900° C. to form a barrier layer of titanium nitride layer 8 on the surface of titanium silicide layer 7. Next, aluminum wiring 9 containing approximately 1% silicon is selectively provided, contacting titanium nitride layer 8 and extending above glabellar insulating layer 4 .

〔Effect of the invention〕

As explained above, the present invention fills the contact opening of a semiconductor device with a polycrystalline silicon layer deposited by the CVD method, and also provides a high melting point metal silicide layer on the surface of the polycrystalline silicon layer. By forming metal wiring on the surface of the silicide layer via a barrier layer, it is possible to prevent the electrode wiring from breaking at the contact portion and to obtain a semiconductor device equipped with the electrode wiring with low contact resistance. .

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention. 1... P-type silicon substrate, 2... Insulating film, 3...
N-type diffusion region, 4... Interlayer insulating layer, 5... Polycrystalline silicon layer, 6... Titanium layer, 7... Titanium silicide layer, 8... Titanium nitride layer, 9... Aluminum wiring.

Claims (1)

[Claims] an interlayer insulating layer formed on a semiconductor substrate in which a semiconductor element region is formed; a polycrystalline silicon layer in contact with the element region in an opening provided in the interlayer insulating layer and provided only in the opening; a high melting point metal silicide layer provided on the crystal silicon layer; a barrier layer provided on the surface of the high melting point metal silicide layer; and a barrier layer formed in contact with the barrier layer and extending over the interlayer insulating layer. What is claimed is: 1. A semiconductor device comprising: