JPS62287645A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62287645A JPS62287645A JP13253286A JP13253286A JPS62287645A JP S62287645 A JPS62287645 A JP S62287645A JP 13253286 A JP13253286 A JP 13253286A JP 13253286 A JP13253286 A JP 13253286A JP S62287645 A JPS62287645 A JP S62287645A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- film
- interlayer insulating
- insulating film
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000010410 layer Substances 0.000 abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 abstract description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000011347 resin Substances 0.000 abstract description 9
- 229920005989 resin Polymers 0.000 abstract description 9
- 150000004767 nitrides Chemical class 0.000 abstract description 8
- 238000007789 sealing Methods 0.000 abstract description 5
- 239000004411 aluminium Substances 0.000 abstract 3
- 230000008020 evaporation Effects 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000035882 stress Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体集積回路のチップ構造に関し、特にチッ
プの表面構造に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a chip structure of a semiconductor integrated circuit, and particularly to a surface structure of a chip.
従来の二層配線構造の半導体集積回路はシリコンへの不
純物拡散を行なった後、表面絶縁膜形成。In conventional semiconductor integrated circuits with a two-layer wiring structure, impurities are diffused into silicon, and then an insulating film is formed on the surface.
コンタクト穴形成，第ＩＡｌ形成，層間絶縁膜形成，第
２ＡＩ形成，表面保護膜形成により形成される。この場
合、チップの端については端または端の近傍まで層間絶
縁膜や表面保護膜等の絶縁膜で覆われていた。It is formed by forming a contact hole, forming a first IAl, forming an interlayer insulating film, forming a second AI, and forming a surface protection film. In this case, the end of the chip is covered with an insulating film such as an interlayer insulating film or a surface protection film up to or near the end.
ところが上述の構造のチップは、その後の組立工程の一
部である樹脂封止工程後、層間絶縁膜及び表面保護膜が
割れるという欠点がある。これは層間絶縁膜及び表面保
護膜がシリコン窒化膜で形成されており、シリコン窒化
膜は硬くて脆く樹脂と比べ熱膨張係数も小さいため樹脂
封止後の樹脂の圧縮応力に耐えられないためである。However, the chip having the above-mentioned structure has a drawback that the interlayer insulating film and the surface protection film crack after the resin sealing process that is part of the subsequent assembly process. This is because the interlayer insulating film and surface protection film are made of silicon nitride film, and silicon nitride film is hard and brittle and has a smaller coefficient of thermal expansion than resin, so it cannot withstand the compressive stress of the resin after resin sealing. be.
発明者は層間絶縁膜及び表面保護膜の割れ状態を調べた
結果、いずれもチップの端から割れていることを発見し
た。またチップ面積が大きい程割れやすいことも解った
。The inventor investigated the state of cracks in the interlayer insulating film and the surface protection film, and discovered that both cracks started from the edge of the chip. It was also found that the larger the chip area, the more likely it is to break.
従って、割れの原因はチップの横方向の応力がシリコン
窒化膜に作用して生ずるものと考えられる。Therefore, it is thought that the cause of the cracks is that stress in the lateral direction of the chip acts on the silicon nitride film.
上述した従来のプラズマ窒化膜等の硬くて脆い物質をシ
リコン上に形成する半導体集積回路では、樹脂による成
長膜の割れは避けて通れない問題である。また集積回路
の集積度は向上するものの回路自体の規模が大きくなり
チップサイズも大きくなる傾向にあシ、チップサイズが
大きいと割れも発生しやすくなる。In semiconductor integrated circuits in which a hard and brittle material such as the above-mentioned conventional plasma nitride film is formed on silicon, cracking of the grown film due to resin is an unavoidable problem. Furthermore, although the degree of integration of integrated circuits has improved, the scale of the circuit itself has increased and the chip size has also tended to increase, and the larger the chip size, the more likely it is that cracks will occur.
本発明は成長膜の割れの発生機構に注目し、チップ周辺
のみ緩衝材を用いれば割れが防げることが第１の独創的
内容であり、その結果として緩衝材として新たに新しい
物質を用いず従来の工程を増すことな〈従来もある電極
金属を用いることができることが第２の独創的内容であ
る。The present invention focuses on the mechanism by which cracks occur in a grown film, and its first original content is that cracks can be prevented by using a buffer material only around the chip. The second original content is that conventional electrode metals can be used without increasing the number of steps.
本発明は以上述べた多層配線構造等での層間絶縁膜及び
表面保護膜の割れを抑えること金目的としており、これ
によりコストが安く、信頼度の高い半導体集積回路を提
供できる。The object of the present invention is to suppress cracking of the interlayer insulating film and surface protective film in the above-mentioned multilayer wiring structure, etc., thereby making it possible to provide a semiconductor integrated circuit with low cost and high reliability.
本発明による半導体集積回路は層間絶縁膜及び表面保護
膜の割れがチップの端から生じていることに注目し、チ
ップの端において表面保護膜あるいは層間絶縁膜の端と
チップ端の間に配線金属を備えたことを特徴とする。In the semiconductor integrated circuit according to the present invention, attention is paid to the fact that cracks in the interlayer insulating film and the surface protection film occur from the edge of the chip, and at the edge of the chip, there is a wiring metal between the edge of the surface protection film or the interlayer insulating film and the chip edge. It is characterized by having the following.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.
１はシリコン基板である。シリコン基板内への不純物拡
散領域は図では省略している。１の表面に゛厚さ０．７
μｍのシリコン酸化膜２と厚さＯ，１μｍのシリコン窒
化膜３で表面絶縁膜を形成し、コンタクトの穴を形成後
第１アルミ蒸着層４を１．０μｍ蒸着し、その後プラズ
マ窒化膜層５を１．０μｍ成長し層間絶縁膜とし、第２
アルミ蒸着層６を２．０μｍ蒸着し、最後にプラズマ窒
化膜層７を１．０μｍ成長し表面保護膜としている。各
層はもちろん成長後パターン形成を行なっている。チッ
プの端８はシリコンｔ−ｍ出させておシ、表面保護膜と
しての７及び層間絶縁膜としての５の端とチップの端８
の間に第１アルミ蒸着層９と第２アルミ蒸着層１０を１
０μｍ備えている。1 is a silicon substrate. The impurity diffusion region into the silicon substrate is omitted in the figure. Thickness 0.7 on the surface of 1
A surface insulating film is formed with a silicon oxide film 2 of 1 μm thickness and a silicon nitride film 3 of 1 μm thickness, and after forming a contact hole, a first aluminum vapor deposition layer 4 of 1.0 μm thickness is deposited, and then a plasma nitride film layer 5 is formed. was grown to 1.0 μm to form an interlayer insulating film, and the second
An aluminum vapor deposition layer 6 is deposited to a thickness of 2.0 μm, and finally a plasma nitride film layer 7 is grown to a thickness of 1.0 μm to serve as a surface protection film. Of course, each layer is patterned after growth. The edge 8 of the chip is made of silicon t-m exposed, and the edge 7 of the surface protection film and the edge 5 of the interlayer insulating film are connected to the edge 8 of the chip.
Between the first aluminum vapor deposition layer 9 and the second aluminum vapor deposition layer 10,
Equipped with 0μm.
樹脂封止によるチップへの応力は圧縮応力でありチップ
端の層間絶縁膜や表面保護膜への加圧が周囲をアルミで
覆うことによシ緩和され割れがなくなる。The stress on the chip due to resin sealing is compressive stress, and the pressure applied to the interlayer insulating film and surface protection film at the edge of the chip is alleviated by covering the periphery with aluminum, eliminating cracks.
第２図は本発明の他の実施例の縦断面図である。FIG. 2 is a longitudinal sectional view of another embodiment of the invention.
本実施例は前例と異なり表面電極が一層の場合を挙げる
。This example differs from the previous example in that the surface electrode is one layer.
１１はシリコン基板であシ、シリコン基板内への不純物
拡散領域は図では省略している。厚さ０．７μｍのシリ
コン窒化膜１２と厚さ０．１μｍのシリコン窒化膜１３
で表面絶縁膜を形成しコンタクトの穴を形成後、アルミ
蒸着１４を１．７μｍ蒸着しその後プラズマ窒化膜層１
７を１．０μｍ成長し表面保護膜としている。各層はパ
ターン形成を行なっている。11 is a silicon substrate, and the impurity diffusion region into the silicon substrate is omitted in the figure. Silicon nitride film 12 with a thickness of 0.7 μm and silicon nitride film 13 with a thickness of 0.1 μm
After forming a surface insulating film and forming contact holes, aluminum 14 is deposited to a thickness of 1.7 μm, and then plasma nitride film layer 1 is deposited.
7 was grown to a thickness of 1.0 μm to serve as a surface protective film. Each layer is patterned.
チップの端１８はシリコンを露出させており、表面保護
膜としての１７の端とチップ端１８の間にアルミ蒸着層
１９を１０μｍ備えている。The end 18 of the chip has exposed silicon, and an aluminum vapor deposition layer 19 of 10 μm is provided between the end 17 and the end 18 of the chip as a surface protection film.
本実施例も第１図に示す例と同じくチップ周囲を柔かい
アルミで覆っているため割れない。Like the example shown in FIG. 1, this embodiment also does not break because the chip is covered with soft aluminum.
以上説明したように、本発明はチップ周囲を電極金属で
覆うことによシ、硬くて脆いプラズマ窒化膜等の樹脂封
止応力を周囲の金属の柔らかさで緩和し割れを効果的に
なくすことができる。As explained above, the present invention effectively eliminates cracks by covering the chip periphery with an electrode metal, thereby alleviating the resin sealing stress of the hard and brittle plasma nitride film with the softness of the surrounding metal. Can be done.
プラズマ窒化膜の割れはチップサイズが大きい程、また
樹脂の面積が大きい程割れやすいことが邂っているため
、本発明は必要に応じてチップの全周に実施してもよい
し一部に実施してもよい。It has been found that the larger the chip size and the larger the area of the resin, the more easily the plasma nitride film cracks. Therefore, the present invention may be applied to the entire circumference of the chip or to a part of the chip as necessary. May be implemented.
また金属はアルミニ限らず柔かい性質の金属であれば伺
でもよい。Also, the metal is not limited to aluminum; any metal with soft properties may be used.
本発明によシ製造上の不具合もなくせるはかシか、市場
へ出てからの熱ストレスによる応力に対しても高い信頼
性を得ることができる。The present invention not only eliminates manufacturing defects, but also provides high reliability against stress caused by thermal stress after being placed on the market.
第１図は本発明の一実施例を示す縦断面図であり、第２
図は本発明の他の実施例を示す縦断面図である。
１・・・・・・シリコン基板、２・・・・・・シリコン
酸化膜。
什押人 妻押キ 内 百 普
箭ｆ図
躬′２′図FIG. 1 is a vertical sectional view showing one embodiment of the present invention, and FIG.
The figure is a longitudinal sectional view showing another embodiment of the present invention. 1...Silicon substrate, 2...Silicon oxide film. 100 people who push their wives, 100 pictures of F'2'
Claims (2)
間に配線金属を備えたことを特徴とする半導体集積回路
。(1) A semiconductor integrated circuit characterized by having a wiring metal between the edge of a surface protective film or an interlayer insulating film and the edge of a chip.
化膜で構成されたことを特徴とする前記特許請求の範囲
（１）項記載の半導体集積回路。(2) The semiconductor integrated circuit according to claim (1), wherein the surface protection film or the interlayer insulating film is made of a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13253286A JPS62287645A (en) | 1986-06-06 | 1986-06-06 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13253286A JPS62287645A (en) | 1986-06-06 | 1986-06-06 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62287645A true JPS62287645A (en) | 1987-12-14 |
Family
ID=15083480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13253286A Pending JPS62287645A (en) | 1986-06-06 | 1986-06-06 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62287645A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02125638A (en) * | 1988-11-04 | 1990-05-14 | Nec Corp | Semiconductor integrated circuit device |
| JPH0488632A (en) * | 1990-07-31 | 1992-03-23 | Murata Mfg Co Ltd | Formation of protective film for heat treatment |
| WO2002097868A2 (en) * | 2001-06-01 | 2002-12-05 | Koninklijke Philips Electronics N.V. | Integrated circuit having an energy-absorbing structure |
| US6650010B2 (en) | 2002-02-15 | 2003-11-18 | International Business Machines Corporation | Unique feature design enabling structural integrity for advanced low K semiconductor chips |
-
1986
- 1986-06-06 JP JP13253286A patent/JPS62287645A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02125638A (en) * | 1988-11-04 | 1990-05-14 | Nec Corp | Semiconductor integrated circuit device |
| JPH0488632A (en) * | 1990-07-31 | 1992-03-23 | Murata Mfg Co Ltd | Formation of protective film for heat treatment |
| WO2002097868A2 (en) * | 2001-06-01 | 2002-12-05 | Koninklijke Philips Electronics N.V. | Integrated circuit having an energy-absorbing structure |
| WO2002097868A3 (en) * | 2001-06-01 | 2004-04-08 | Koninkl Philips Electronics Nv | Integrated circuit having an energy-absorbing structure |
| US6650010B2 (en) | 2002-02-15 | 2003-11-18 | International Business Machines Corporation | Unique feature design enabling structural integrity for advanced low K semiconductor chips |
| US6815346B2 (en) | 2002-02-15 | 2004-11-09 | International Business Machines Corporation | Unique feature design enabling structural integrity for advanced low k semiconductor chips |
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