JPS61107749A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61107749A JPS61107749A JP22860684A JP22860684A JPS61107749A JP S61107749 A JPS61107749 A JP S61107749A JP 22860684 A JP22860684 A JP 22860684A JP 22860684 A JP22860684 A JP 22860684A JP S61107749 A JPS61107749 A JP S61107749A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- onto
- film
- films
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(1)発明の属する技術分野
本発明は半導体装置にかか)、とくにパッシベーション
膜の欠陥を著るしく減らし高い信頼性をもった半導体装
置を実現する為のパッシベーション膜の構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to semiconductor devices, particularly to passivation films that significantly reduce defects in passivation films and realize semiconductor devices with high reliability. It is related to the structure of
(2)従来技術
半導体集積回路の微細化、高集積化によ)半導体表面は
複雑さを増して居りバッシペーション膜の微小な欠陥が
素子の信頼性に与える影響は太き表ものに彦9つつある
。第1図に従来から広く使われている表面保護膜を有す
る半導体装置の断面図の例を示す。図中1は半導体基板
、2は拡散層、3は絶縁膜、4は金属配線層、5゜6は
表面保護膜、7は保護膜に発生した欠陥である。半導体
装置では表面保護膜と下地との熱膨張係数の差による内
部応力や外から加えられる機械的応力、保護膜成長時の
ゴミの存在等によシ保護膜に欠陥が発生しこれら欠陥に
よる信頼性上の問題が誘発される事があった。その為従
来では保護膜の欠陥密度を減らす為、各種保護膜の検討
や2層構造をもった保護膜が使われたシしているが保護
膜形成時に表面の凹凸が激しい場合は段部での欠陥を減
らす事は非常に困難であシ、保護膜形成後も表面段部へ
の外部応力の集中や段部での保護膜厚の低下によシ欠陥
が段部で集中的に発生する事はさけられなかった。(2) Conventional technology Due to the miniaturization and high integration of semiconductor integrated circuits) semiconductor surfaces are becoming more complex, and the influence of minute defects in the bacsipation film on device reliability is becoming more pronounced9. It's coming. FIG. 1 shows an example of a cross-sectional view of a semiconductor device having a surface protection film that has been widely used in the past. In the figure, 1 is a semiconductor substrate, 2 is a diffusion layer, 3 is an insulating film, 4 is a metal wiring layer, 5.6 is a surface protection film, and 7 is a defect occurring in the protection film. In semiconductor devices, defects occur in the protective film due to internal stress due to the difference in thermal expansion coefficient between the surface protective film and the underlying layer, mechanical stress applied from the outside, the presence of dust during the growth of the protective film, etc. Sexual problems were sometimes induced. Therefore, conventionally, in order to reduce the defect density of the protective film, various types of protective films have been investigated and a protective film with a two-layer structure has been used. It is very difficult to reduce the number of defects, and even after the protective film is formed, defects occur intensively at the step due to the concentration of external stress on the surface step and the decrease in the thickness of the protective film at the step. The matter could not be avoided.
(3)発明の目的
本発明の目的は上述の保護膜への欠陥の発生を防止しよ
シ信頼性の高い半導体装置を提供することにある。(3) Purpose of the Invention The purpose of the present invention is to provide a highly reliable semiconductor device that prevents the above-mentioned defects from occurring in the protective film.
(4)発明の構成
本発明の特徴は、最終金属配線形成後3層以上から成る
絶縁膜を保護膜として有し、下層の絶縁膜を塗布法で形
成した事を特徴とする半導体装置にある。(4) Structure of the Invention The present invention is characterized by a semiconductor device having an insulating film consisting of three or more layers as a protective film after final metal wiring is formed, and the lower insulating film is formed by a coating method. .
(5)実施例の説明
第2図に本発明の一実施例による半導体装置の断面構造
を示す。図中1は半導体基板、2は一拡散層、3は絶縁
膜、4は金属配線層、8は塗布によって形成された無機
質文は有機質の絶縁膜9.10は金属又は半導体の酸化
膜又は窒化膜等の絶縁膜でスパッタ法、蒸着法、気相成
長法等の塗布法以外で形成した膜、7は保護膜に発生し
た欠陥である。図中8は金属配線4を形成した後の表面
平担化を目的として形成される絶縁膜であ)、絶l#膜
8を形成後さらによシ緻密な保護膜9,10を形成する
事によシ従来の構造による段部での欠陥発生を防止し欠
陥が極めて少ない保護膜が得られる。(5) Description of Embodiment FIG. 2 shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a diffusion layer, 3 is an insulating film, 4 is a metal wiring layer, 8 is an inorganic film formed by coating, and 9 is an organic insulating film. 10 is a metal or semiconductor oxide film or nitride film. Insulating films such as films formed by methods other than coating methods such as sputtering, vapor deposition, and vapor deposition, and 7 are defects that occur in the protective film. 8 in the figure is an insulating film formed for the purpose of flattening the surface after forming the metal wiring 4), and after forming the absolute # film 8, more dense protective films 9 and 10 are formed. As a result, it is possible to prevent the occurrence of defects at the stepped portions caused by the conventional structure, and to obtain a protective film with extremely few defects.
(6)発明の効果
平面を平担化した後その上にさらに2層以上の緻密な保
護膜を付ける事によシ欠陥が極めて少ない保護膜を形成
出来、高、い信頼性を有する半導体装置を実現出来る。(6) Effects of the invention By flattening the plane and then adding two or more dense protective films on top of it, a protective film with extremely few defects can be formed, resulting in a highly reliable semiconductor device. can be realized.
第1図は従来から一般に使われている表面保護膜を有す
る半導体装置の断面図である。図中1は半導体基板、2
は拡散層、3は絶縁膜、4は金属配線層、5.6は表面
保護膜、7は保護膜に発生した欠陥を示す。FIG. 1 is a cross-sectional view of a semiconductor device having a surface protection film that has been commonly used in the past. In the figure, 1 is a semiconductor substrate, 2
3 is a diffusion layer, 3 is an insulating film, 4 is a metal wiring layer, 5.6 is a surface protective film, and 7 is a defect occurring in the protective film.
Claims (1)
に塗布法以外の方法により形成された2層以上の絶縁膜
を設けた事を特徴とする半導体装置。A semiconductor device characterized in that an insulating film is provided on a metal wiring by a coating method, and two or more layers of insulating films formed by a method other than the coating method are provided on the insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22860684A JPS61107749A (en) | 1984-10-30 | 1984-10-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22860684A JPS61107749A (en) | 1984-10-30 | 1984-10-30 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61107749A true JPS61107749A (en) | 1986-05-26 |
Family
ID=16878980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22860684A Pending JPS61107749A (en) | 1984-10-30 | 1984-10-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61107749A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019087768A (en) * | 2019-03-13 | 2019-06-06 | ラピスセミコンダクタ株式会社 | Semiconductor device |
-
1984
- 1984-10-30 JP JP22860684A patent/JPS61107749A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019087768A (en) * | 2019-03-13 | 2019-06-06 | ラピスセミコンダクタ株式会社 | Semiconductor device |
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