JPH0642481B2 - Manufacturing method of semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for flattening a surface on an insulating layer between wirings in a semiconductor device having a multilayer wiring structure.

Background Art and Problems Thereof In a semiconductor device having a multilayer wiring structure, an upper layer wiring and a lower layer wiring are electrically separated from each other by forming an insulating thin film (interlayer insulating layer) between the both wirings. It is desirable that the surface shape of the interlayer insulating layer is flat when finely processing the upper wiring, regardless of the step of the underlying layer (lower wiring, field oxide film, etc.) for the following reason. That is,
This is because if the surface of the interlayer insulating layer is flat, disconnection due to deterioration (for example, step breakage) of the insulator covered by the step portion of the upper layer wiring is eliminated and reliability is improved. Further, since patterning is facilitated by photolithography for processing the upper layer wiring, processing accuracy and yield are improved.

When flattening the surface of this interlayer insulating layer, if the wiring material is a refractory material that does not deform or deteriorate even at high temperatures (for example, polysilicon, silicide, refractory metal, etc.), metal-impurity-doped glass (PSG, AsSG) , Pb-containing oxide film, etc.) as an interlayer insulating layer material, and can be softened by a high temperature treatment at 800 to 1100 ° C. to obtain a flat surface (so-called glass flow or reflow technique). However, Al with low electrical resistance
Alternatively, when using an alloy of Al, Si, Cu, etc., the above reflow technology cannot be used because these wiring materials are low melting point substances, and only the surface protrusion of the conventional interlayer insulating layer is RIEed. , Ion milling (ion beam etching)
Etching and removal were selectively carried out by means such as to flatten the surface. However, when attempting to form a thick interlayer insulating layer by the conventional method, the covering property of the insulating material deteriorates at the step portion of the wiring,
In particular, as shown in FIG. 1, the insulating material (2) overhangs (so-called overhang) between the wirings (1) arranged in parallel, and a groove portion or a cavity portion (3) occurs. As a result, there is a problem that a flat surface cannot be obtained even by etching. (5) is a Si substrate, and (4) is a SiO ₂ film. Further, in order to avoid such an overhang, the formation of a thin insulating layer and the planarization process by etching must be repeated several times, which complicates the manufacturing. And
When the interlayer insulating layer is formed by CVD, it is necessary to select and use the device and method because the step coverage varies depending on the CVD device and method (normal pressure, reduced pressure, plasma combined use, etc.). There was a flaw.

It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can flatten the surface of an insulating layer between wirings at a low temperature (normal temperature).

SUMMARY OF THE INVENTION According to the present invention, a step of forming a first insulating layer on a step portion formed in a semiconductor device and anisotropic etching of the first insulating layer to form a taper on a side surface of the step portion. A step, a step of forming a second insulating layer on the first insulating layer, and a step of forming a third insulating layer on the second insulating layer so that the surface is flattened; Is a method for manufacturing a semiconductor device including a step of flattening the second insulating layer by means of etching.

By the above manufacturing method, the surface of the insulating layer between the wirings can be flattened at a low temperature.

Example In this example, a method for manufacturing a semiconductor device having a two-layer wiring structure will be described.

First, as shown in FIG. 2A, SiO ₂ is formed on the surface of the Si substrate (11).
After forming the film (12), first-layer Al wirings (13) are formed in parallel at predetermined intervals. This Al wiring (13) contains 1% Si.
It is made of Al (pure Al, Al-Si-Cu alloy, etc.) contained and its thickness is 4000Å.

Next, as shown in FIG. 2B, SixNy of 1000 Å is sequentially deposited on the Al wiring (13) by plasma CVD and 1000 of pure SiO ₂ is deposited by CVD.
Å, 4000 Å of PSG is deposited to form the first insulating layer (14).

Next, as shown in FIG. 2C, for example, RIE (CF ₄ + H ₂ or
CHF ₃ , 6 × ▲ 10 ^-2 _torr ▼, 400W) is used for anisotropic etching to taper the insulating layer (14) on both sides of the Al wiring (13).
Form (15) (so-called side wall spacer). The insulating layer (14) on the Al wiring (13) may be completely removed or may be left partially. However, in order to prevent abnormal growth of Al (so-called formation of pits), it is preferable to leave the insulating layer (14) on the Al wiring (13).

Next, as shown in FIG. 2D, pure SiO ₂ is sequentially deposited to 1 by CVD.
000Å, 1.4 μ of PSG is deposited to form the second insulating layer (16). As the second insulating layer (16), in addition to the above configuration,
SiO ₂ , impurity-implanted SiO ₂ , Si ₃ N ₄ , polyimide (PIQ)
It may be composed of an inorganic or organic insulator such as, or a multilayer including a combination thereof. Note that this insulation layer (16)
As for the thickness, the height from the Si substrate (11) is T, Al wiring (1
When the thickness of 3) is t, it is formed so that T> t. On the contrary, when T <t, after flattening, the Al wiring (13)
It is unsuitable because the top is not covered with the insulating layer (16).

Next, as shown in FIG. 2E, the third insulating layer (17) is thick on the second insulating layer (16) between the two Al wirings (13), and on the Al wiring (13). For example, a spinner is applied so as to be thin, and the surface is formed to be substantially flat. As the insulating material used here, an organic substance or an inorganic substance dissolved in a solvent can be used. As a method of flattening the surface, a softening phenomenon may be utilized by applying an insulating material and then performing heat treatment at 100 to 300 ° C. A photoresist is applied to a thickness of about 1.0 μ by a spinner, and the surface is softened and flattened by heat treatment at 160 ° C. for 30 minutes. If the material of the third insulating layer (17) satisfies all of the following conditions, the desired planarization is achieved in this step. That is, first, the adhesiveness with the underlying insulating layer is good, but no chemical reaction occurs.
Thirdly, it does not adversely affect the electrically active region formed on the Si substrate, and thirdly, the adhesion to the wiring formed on the upper side is good,
No chemical reaction, and fourth, no deterioration or deformation by heat treatment at least at 400 to 500 ° C. However, at present, there is no substance that meets all of these requirements, and there is no formation method that provides sufficient planarization, so avoiding the occurrence of slight irregularities on the surface of the third insulating layer (7). I can't.
Therefore, this third insulating layer (17) is used only as an etching mask material in the next step.

Next, as shown in FIG. 2F, the dry etching method capable of anisotropic etching such as RIE is used to etch the second insulating layer (16) and the third insulating layer (17). Etching is performed under the same speed condition (the etching speed of the second insulating layer (16) may be slightly faster than the etching speed of the third insulating layer (17)), and the third insulating layer (17) is Chain line X
The position indicated by is obtained). This is because the lower step (18) of the second insulating layer (16) has a thicker third insulating layer (1).
It is not etched by the masking effect of 7) and Al wiring (1
This is because only the insulating layer (16) above 3) is selectively removed by etching. Therefore, after planarization, the third insulating layer (17)
Will be completely removed, but if it remains partially, only the third insulating layer (17) is removed by chemical selective etching or plasma etching using O ₂ gas. Specific conditions for etching with RIE are, for example, CHF ₃ (40 sccm) + O ₂ (3 sccm), 0.06 Torr, 450 Wa
tt (0.23W / cm ² ) The thickness of the planarized interlayer insulating layer finally formed in this step is sT-t, where s is the thickness of the upper portion of the Al wiring (13).

Next, as shown in FIG. 2H, Al (for example, containing 1% of Si) is formed by sputtering or vapor deposition to have a thickness of 1.0 μ, and then patterning is performed to form a second layer of Al wiring (1
9) is formed. Although not shown, usually, after this, an insulating layer serving as a protective film is formed on the second-layer Al wiring (19), and then a pad window is opened for connection with an external circuit.

When the Al wiring (13) is thick, the insulating layer (16) between the Al wirings (13) is formed even after the final flattening step shown in FIG. 2G.
A concave part may occur in the. In such a case, the flattening step may be repeated by the same method as the conventional method,
Since the concave part is very local, after baking the silica glass solvent with a spinner, baking (90 ~ 250 ℃)
Sufficient flattening can be achieved by just doing.

The present invention can be applied to, for example, a three-layer wiring structure including one layer of poly-Si wiring and two layers of Al wiring.
After the interlayer insulating film is formed flat on the wiring by heat treatment (reflow method), the same processing as in the above embodiment may be performed.
As another application example, an electrically active region (bipolar transistor or MOS) may be formed on the planarization layer described above.
It is also applicable to a so-called three-dimensional device provided with a transistor or the like).

According to the above-mentioned manufacturing method, the interlayer insulating layer can be formed thick without forming a groove portion or a cavity portion in the interlayer insulating layer as in the conventional case. Therefore, sufficient flatness can be obtained by the single continuous flattening step, so that the production is easy and the reproducibility and stability are excellent. In addition, since the insulating material has good coverage on the Al wiring step, it is not necessary to select the CVD apparatus, conditions, etc. as in the conventional case.

EFFECTS OF THE INVENTION According to the method for manufacturing a semiconductor device of the present invention, flattening of the interlayer insulating layer can be realized at a low temperature (normal temperature) without the need for high-temperature heat treatment. It can be used for wiring of a semiconductor device having a multilayer wiring structure. As a result, the operating speed of semiconductor devices such as VLSI and LSI can be improved. Further, since the manufacturing method is easy, it can be used for this manufacturing method without making a great change to the conventional wiring technique.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a conventional method for manufacturing a semiconductor device, and FIGS. 2A to 2H are sectional views showing a method for manufacturing a semiconductor device according to the present invention. (11) is a Si substrate, (12) is a SiO ₂ film, (13) is the first layer of Al wiring,
(14) is the first insulating layer, (15) is the taper, (16) is the second insulating layer, (17) is the third insulating layer, and (19) is the second-layer Al wiring.

Claims (1)

[Claims] 1. A step of forming a first insulating layer on a step portion formed in a semiconductor device, and a step of anisotropically etching the first insulating layer to form a taper on a side surface of the step portion. And a step of forming a second insulating layer on the first insulating layer, and a step of forming a third insulating layer on the second insulating layer so that the surface is planarized, The above second due to sex etching
Of a semiconductor device having a step of flattening the insulating layer of.