JPS58216443A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To smoothen a stepwise structure by coating resist thickly on an oxidized film which has the stepwise structure and etching by reactive ion etching it. CONSTITUTION:A CVD SiO2 film 13 is formed on the second polysilicon layer 15. The layer 13 on the layer 15 is formed to be thicker than the conventional one. When a resist 18 is coated on the layer 13, the resist 18 on the projecting part of the layer 12 becomes thin, while the resist on the recessed part of the layer 13 becomes thick. In Figure A, reactive ion etching (RIE) is performed under the conditions that the etching speed of the resist 18 is not so different from that of the layer 13. The etching is stopped before the layer 13 on the layer 15 is vanished. Then, a BPSG layer 17 is formed on the layer 13, and molten by heat treating. Then, an aluminum layer 16 is formed on the layer 17.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a method for smoothing a one-step structure in a semiconductor integrated circuit by performing reactive ion etching with a CVD5 iO layer coated with a thick resist over the entire surface. The present invention relates to a method of manufacturing a semiconductor device.

[Technical background of the invention]

In integrated circuits, as the degree of integration increases, the number of layers increases,
As the process progresses to later stages, resist patterning with larger steps is required. Further, the appropriate time for exposing the resist depends on the type of resist, the reflectance of the substrate to be etched, etc.

-7. Disadvantages of the conventional semiconductor device manufacturing method will be explained using drawings. In this embodiment, since aluminum is used as a wiring metal material, aluminum is used as an example of the F base plate etching material.

Figure 1 shows a typical two-layer polysilicon structure.
11 is Si substrate, 12 is 51 (J2 layer, 13h CVI
JSiU, layer: 14 c1 cy) polysilicon layer; 15 is second polysilicon layer; 16 is A/layer.

For example, the thickness of the first polysilicon layer 14 is 0.6 μm.
If the thickness of the second polysilicon layer 15 is 0.4 μm, a step difference of approximately 1 μm occurs.

Then, when a positive resist is applied on ktj@1e in the condition shown in Figure 1 at ℃, the viscosity of the resist is small and the surface becomes flat, so the thickness of the resist will differ in each part.
It is difficult to precisely control the resist dimensions of the thick and thin portions of the resist after patterning at the same time.

[Background technology Zhao point]

The conventional method taken to deal with this problem is shown in FIG. According to this method, CVI)8IO
, m 13 upper K BPSG layer 17 (Mataha PaG
If heat treatment is performed after forming the 8280 layer 17
When melting, the surface becomes flat 0 From this K, the A1 layer 16
The difference in height is reduced.

However, in the conventional method, the BP8G layer 17 (or P2O
A heat treatment time at high temperature is unavoidable in order to dissolve the layers). An increase in the heat treatment time at such high temperatures has five drawbacks: it increases the diffusion depth, decreases the breakdown voltage between diffusions due to K, shortens the effective channel length, and increases the short channel effect. Therefore, the dissolution time of the 8280 layer 17 (or P2O layer) must be suppressed as much as possible. Also, 8280 layer 17 (or P
Even after the heat treatment of the 2O layer), there was a drawback that the level difference disappeared because it was opaque. In this situation A/
When reactive ion etching is used for etching, there is not much difference in etching speed between the resist and M, so in the thin part of the resist in the convex part, the resist dimension is A/layer 16.
was etched, and A/ wire breakage was likely to occur.

[Purpose of the invention]

This invention was made in view of the above points.

The object is to provide a method for manufacturing a semiconductor device in which a step structure is smoothed in a semiconductor circuit.

[Summary of the invention]

A thick resist is coated on an oxide film having a step structure, and the step structure is smoothed by etching with reactive ion etching. An example will be explained.

3rd-(5) is the polysilicon layer of Hire 2) 15
UVI on this second polysilicon layer 15
J8i0. Layer 13 is thicker than the conventional one. Then, when the resist 18 is applied on the CVD5iO layer 13, the resist 18 on the convex portion of the CVD5iO layer 13 is thin (CVIJ8t01 layer 1317).
Above the concave part') J 8 becomes thicker. , in the state shown in FIG. 3(5)K, the resist 18 and CVI) 8i
0. Reactive ion etching (ITIG) is performed under conditions where the etching rate of layer 13 does not differ significantly. and,
Etching is stopped when the cvusto layer 13 on the second polysilicon layer 15 is removed. Finally, the state in which the resist 18 has been peeled off is shown in FIG. 3(B).

Next, upper f CVI)8i0. Layer top K 8280 layer 17
is formed and dissolved by heat treatment. And the above BP
An Aj layer 16 is formed on the 8GIWIJy. The state at this time is shown in Figure 3 (0). In other words, Figure 3 (B)
Since the level difference is reduced in the step , the heat treatment time for melting the 8280 layer 17 (or the P2O layer) can be shortened.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to reduce the step difference without increasing the heat treatment time, and therefore it is possible to prevent an increase in the low toya short channel effect of the inter-diffusion breakdown voltage.

[Brief explanation of drawings]

Figures 1v and 2 respectively show a method of manufacturing a semiconductor device. 1, @31! N(A) to C) indicate a method of manufacturing a semiconductor device according to an embodiment of the present invention. 11...SN board, 12...8i0mMb J s
...CVI) 8 iU, layer, 16-k1 layer, 17-
BPSG layer, 18...Resist 0 Applicant's agent Patent attorney Takehiko Suzue JIll Figure 2 Figure 1113 Figure JII31i3

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: a resist coating step of thickly coating a resist on an oxide film having a stepped structure; and a step of etching the resist formed in the resist coating step by reactive ion etching.