JPH09213793A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce process failure in a multilayer wiring without degrading reliability of a semiconductor device in a semiconductor integrated circuit device having a multilayer wiring. SOLUTION: A stopper silicon nitride film 11 is provided between a first-layer wiring 14 and a BPSG film 10. The silicon nitride film 11 stops etching of an interlayer dielectric film 15 upon formation of a through hole 16, which prevents etching of the BPSG film 10 and a silicon oxide film 9 positioned below the first-layer wiring 14. Further, since the stopper silicon nitride film 11 is provided only in a region where the through hole 16 is formed, hydrogen, which is introduced by hydrogen annealing treatment performed on a semiconductor substrate 1 after formation of a second-layer wiring 17, easily reaches the interface of a gate insulating film 4 and the semiconductor substrate 1. This reduces the interface levels.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a multilayer wiring.

[0002]

2. Description of the Related Art Wiring layer microfabrication technology is becoming more and more complicated due to the multi-layered wiring structure, which greatly affects the product yield of semiconductor integrated circuit devices.

Particularly, in a semiconductor integrated circuit device having a minimum processing dimension of 0.3 μm or less, a margin of alignment accuracy in the photolithography technique becomes very small, and a photoresist mask and a photoresist mask are used for processing. The misalignment with the pattern located under the thin film tends to occur. Therefore, in the etching process of the thin film, there arises a problem that the thin film located under the pattern and forming the semiconductor integrated circuit device is unnecessarily processed.

For example, as shown in FIG. 10, a through hole 16 for connecting an upper layer wiring 17 and a lower layer wiring 14 which sandwich an interlayer insulating film 15 made of a silicon oxide film is formed in the interlayer insulating film 15. When forming, interlayer insulating film 1
When the position of the photoresist mask provided on the wiring 5 is displaced from the wiring 14 provided under the interlayer insulating film 15, the interlayer insulating film 15 for forming the through hole 16 is formed.
The etching of the silicon oxide film forming the structure proceeds off the wiring 14. Therefore, a BPSG (Boron-doped Phospho Silicate Glass) film 1 formed under the wiring 14 is formed.
The underlying insulating film made of 0 and the silicon oxide film 9 is etched.

Therefore, the inventor of the present invention is concerned with a manufacturing method in which even if the above-mentioned misalignment occurs, through holes for connecting upper and lower wirings can be reliably formed only in the interlayer insulating film provided between these wirings. investigated.

The following is a technique which has not been publicly known but has been studied by the present inventor, and the outline thereof is as follows.

That is, as shown in FIG. 11, on a semiconductor substrate 1 made of silicon single crystal (Si), for example, M
ISFET (Metal Insulator Semiconductor Field Ef
After forming the effect transistor, a silicon oxide film 9, a BPSG film 10 and a stopper silicon nitride film 11 are sequentially deposited on the semiconductor substrate 1 to form a first interlayer insulating film.

Next, using a photoresist mask, the stopper silicon nitride film 11, the BPSG film 10, the silicon oxide film 9 or the silicon nitride film which covers the gate electrode 6 of the MISFET, which constitutes the first interlayer insulating film. 5 are sequentially etched to form a contact hole 13 for connecting the gate electrode 6 of the MISFET and the semiconductor region 7 to the wiring 14 of the first layer to be formed later.

Next, after depositing on the semiconductor substrate 1 and processing the metal film to form the wiring 14 of the first layer, the semiconductor substrate 1
An interlayer insulating film 15 is deposited on the upper surface to form a second interlayer insulating film. Then, using the photoresist mask, the interlayer insulating film 15 forming the second interlayer insulating film is etched to connect the wiring 14 of the first layer and the wiring 17 of the second layer to be formed later. After forming the through-holes 16 of the metal film, the metal film deposited on the semiconductor substrate 1 is processed to form a second film.
The wiring 17 of the layer is formed.

According to the above manufacturing method, the through hole 16
When forming the film, a misalignment occurs between the photoresist mask provided on the second interlayer insulating film and the wiring 14 on the first layer provided below the second interlayer insulating film. Also, after the interlayer insulating film 15 forming the second interlayer insulating film is etched, this etching is stopped by the stopper silicon nitride film 11 forming the upper layer of the first interlayer insulating film, and the first interlayer insulating film is formed. BPS constituting the lower layer of the membrane
It is possible to prevent the G film 10 and the silicon oxide film 9 from being etched.

[0011]

In the method of manufacturing the semiconductor integrated circuit device examined by the present inventor,
The following problems were found.

That is, in the semiconductor integrated circuit device having the MISFET, the gate insulating film made of the silicon oxide film (SiO ₂ ) of the MISFET and the semiconductor substrate (Si).
At the interface, an unbonded bond of Si crystal based on the irregularity of the crystal lattice exists, and an interface state that causes the threshold voltage of the MISFET to change is formed.

Therefore, usually, after forming the wiring layer, 40
A low-temperature hydrogen annealing treatment at 0 to 500 ° C. is performed on the semiconductor substrate to bond hydrogen to unbonded bonds of Si or SiO ₂ to reduce the interface state and stabilize the interface between the gate insulating film and the semiconductor substrate.

However, if the stopper silicon nitride film is formed on the entire surface of the semiconductor substrate other than the region where the contact hole is formed, hydrogen does not pass through the stopper silicon nitride film, so that the hydrogen is misfied.
It becomes difficult to reach the interface between the gate insulating film of ET and the semiconductor substrate,
Therefore, the interface level does not decrease and the threshold voltage of the MISFET fluctuates.

In order for hydrogen to pass through the silicon nitride film, it is necessary to make the thickness of the silicon nitride film as thin as 6 nm or less, but if the thickness of the silicon nitride film is 6 nm or less, the second interlayer insulation film is formed. When the silicon oxide film forming the film is etched, this silicon nitride film is easily etched.

It is an object of the present invention to provide a technique capable of reducing processing defects in a multi-layer wiring in a semiconductor integrated circuit device having multi-layer wiring without lowering the reliability of the semiconductor element.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device of the present invention, the first wiring is located on the first interlayer insulating film, and the second wiring is sandwiched on the first wiring with the second interlayer insulating film interposed therebetween. Is provided, a through hole for connecting the second wiring and the first wiring is provided in the second interlayer insulating film, and the first hole is formed in the region where the through hole is formed. An etching stopper layer is provided between the first wiring and the first interlayer insulating film, the etching stopper layer aligns the first wiring with the through hole, and a processing dimension of the first wiring. The pattern size is designed with a margin that allows the accuracy and the processing size accuracy of the through hole.

According to the above means, the second wiring and the first wiring
Even if the position of the through hole provided for connecting the wiring is shifted from the position above the first wiring, the etching for forming the through hole stops at the etching stopper layer, and the first hole is formed under the first wiring. Is not etched. Further, since the etching stopper layer arranged between the first wiring and the first interlayer insulating film is provided only in the region where the through hole is formed, it is introduced by the hydrogen annealing treatment applied to the semiconductor substrate. Hydrogen
It is easy to reach the interface between the gate insulating film of the MISFET and the semiconductor substrate, and the interface level can be reduced.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 shows a semiconductor integrated circuit device having an electrode wiring of a two-layer structure consisting of a first layer wiring and a second layer wiring, which is an embodiment of the present invention. It is a principal part sectional drawing of the semiconductor substrate shown.

A gate insulating film 4 made of a silicon oxide film forming a MISFET is formed on the surface of the semiconductor substrate 1, and a gate electrode 6 made of a polycrystalline silicon film is patterned through the gate insulating film 4. . Also,
Side wall spacers 8 made of a silicon nitride film are provided on both left and right side walls of the gate electrode 6, and the semiconductor regions 7 forming the source and drain regions of the MISFET extend from the surface of the semiconductor substrate 1 to a predetermined depth. The gate electrode 6 is formed from the vicinity directly below the left and right side walls to the outside.

A silicon oxide film 9 and a BPSG film 10 forming a first interlayer insulating film are formed on the MISFET, and the first wiring 14 and the gate are formed in the first interlayer insulating film. A contact hole 13 for connecting the electrode 6 or the wiring 14 of the first layer and the semiconductor region 7 is formed.

Further, a second wiring is formed on the wiring 14 of the first layer.
Is formed, and a through hole 16 for connecting the wiring 17 of the second layer and the wiring 14 of the first layer is formed in the second interlayer insulating film.
Are formed.

Incidentally, between the first-layer wiring 14 and the BPSG film 10 which constitutes the upper layer of the first interlayer insulating film, a stopper silicon nitride is used as a stopper layer for etching when forming the through hole 16. A membrane 11 is provided.

FIG. 2 is a plan view of the principal part of the semiconductor substrate 1 when the misalignment occurs between the through hole 16 and the wiring 14 of the first layer. In the figure, only the BPSG film 10, the stopper silicon nitride film 11, the first-layer wiring 14 and the through hole 16 which constitute the upper layer of the first interlayer insulating film are shown. The pattern size of the stopper silicon nitride film 11 is the same as that of the first-layer wiring 14 and the through hole 1.
6 is designed with an allowance for the alignment accuracy of 6, the processing dimensional accuracy of the wiring 14 of the first layer, and the processing dimensional accuracy of the through holes 16.

According to the present embodiment, the second layer wiring 1
Even if the position of the through hole 16 provided for connecting the wiring 7 of the first layer and the wiring 14 of the first layer is deviated from the position of the wiring 14 of the first layer, the etching for forming the through hole 16 is performed by the stopper silicon nitride. Since the BPSG film 10 and the silicon oxide film 9 forming the first interlayer insulating film are stopped by the film 11, the defective processing in the multilayer wiring can be prevented.

Further, the stopper silicon nitride film 11 is
Since it is provided only in the region where the through hole 16 is formed, the hydrogen introduced by the hydrogen annealing treatment applied to the semiconductor substrate 1 is the same as the gate insulating film 4 of the MISFET.
It is easy to reach the interface of the semiconductor substrate 1 and the interface level can be reduced.

Next, 2 shown in FIG. 1 which is the present embodiment.
A method for manufacturing a semiconductor integrated circuit device having layer wiring will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 3, the p-type well 2 and the field insulating film 3 are formed on the main surface of the semiconductor substrate 1 by a known method.
And the gate insulating film 4 are sequentially formed, and then the semiconductor substrate 1
A polycrystalline silicon film (not shown) and a silicon nitride film 5 are sequentially deposited on top by a CVD (Chemical Vapor Deposition) method.

Next, the silicon nitride film 5 and the polycrystalline silicon film are sequentially etched to form the gate electrode 6 of the MISFET, and then the silicon nitride film 5 and the gate electrode 6 are used as a mask to form the p-type well 2. n-type impurities are ion-implanted to form an n-channel MISFET semiconductor region 7.
To form

After that, a silicon nitride film (not shown) deposited by the CVD method on the semiconductor substrate 1 is subjected to RIE (Reactive I).
The side wall spacer 8 is formed on the side wall of the gate electrode 6 by etching by the on etching method. Next, the silicon oxide film 9 and the BPSG film 10 are formed on the semiconductor substrate 1 by C
After sequentially depositing by the VD method, 850 to 850 in a nitrogen gas atmosphere
A heat treatment is performed at 950 ° C. to flatten the surface of the BPSG film 10.

Next, as shown in FIG. 4, the flattened B
A silicon nitride film (not shown) having a thickness of 0.3 to 1.0 μm is deposited on the PSG film 10 by a plasma CVD method, and then a second layer wiring 17 and a first layer wiring 14 are formed later. A photoresist mask 12 is formed on the silicon nitride film in a region where a through hole 16 provided for connection is formed.

Next, using the photoresist mask 12, the silicon nitride film is subjected to μ (micro) wave ECR (El
ectron Cyclotron Resonance) Etching is performed by a dry etching device to form a stopper silicon nitride film 11. The conditions of dry etching are, for example, etching gas CHF ₃ / CH ₂ F ₂ and gas flow rate ratio CHF ₃ / CH ₂
F ₂ = 15/10 sccm, μ wave current 180 mA, rf
Power 120W, pressure 5mTorr and electrode temperature -3
0 ° C.

Next, as shown in FIG. 5, after removing the photoresist mask 12, the BPSG film 10, the silicon oxide film 9 and the silicon nitride film 5 are sequentially etched using a photoresist mask (not shown). , The contact hole 13 is formed.

Next, the photoresist mask is removed, and subsequently, the metal film deposited on the semiconductor substrate 1, for example, tungsten or aluminum alloy film is etched by using a photoresist mask (not shown), The wiring 14 of the first layer is formed.

Next, as shown in FIG. 6, a flattened thickness of about 1.0 forming a second interlayer insulating film on the semiconductor substrate 1 is obtained.
After depositing the interlayer insulating film 15 of μm by the plasma CVD method, using a photoresist mask (not shown),
The interlayer insulating film 15 is etched by a parallel plate type RIE apparatus to form a through hole 16 for connecting a second layer wiring 17 and a first layer wiring 14 which will be formed later.

The conditions of dry etching are, for example, etching gas C ₄ F ₈ / CF ₄ / CO / Ar and gas flow rate ratio C ₄ F ₈ / CF ₄ / CO / Ar = 2/5/170/60.
0 sccm, rf power 1000 W, pressure 100 mTo
rr and electrode temperature -10 ° C.

Under the above etching conditions, the etching ratio of the silicon nitride film to the silicon oxide film is about 5, and the etching ratio of the tungsten film to the silicon oxide film is about 20. Therefore, when the through hole 16 is processed, the positions of the photoresist 14 and the first layer wiring 14 provided on the interlayer insulating film 15 having a thickness of about 1.0 μm forming the second interlayer insulating film are displaced. However, the thickness is 0.3 to 1.0
The μm stopper silicon nitride film 11 can prevent etching of the BPSG film 10 and the silicon oxide film 9 that form the first interlayer insulating film.

If the silicon nitride film is too thick, the stress of the silicon nitride film causes the semiconductor wafer to warp and the semiconductor wafer will not be adsorbed on the sample stage of the etching apparatus. Therefore, the stopper silicon nitride film 11 is formed.
Is set to 1.0 μm or less.

Next, a metal film deposited on the semiconductor substrate 1,
For example, tungsten, an aluminum alloy film or the like is etched using a photoresist mask (not shown) to form the wiring 17 of the second layer. Finally, the surface of the semiconductor substrate 1 is covered with the passivation film 18, and then 40
By performing hydrogen annealing treatment on the semiconductor substrate 1 at 0 to 500 ° C., the semiconductor integrated circuit device having the two-layer wiring of the first embodiment shown in FIG. 1 is completed.

(Embodiment 2) FIG. 7 shows a semiconductor integrated circuit device having an electrode wiring of a two-layer structure consisting of a first layer wiring and a second layer wiring, which is another embodiment of the present invention. 2 is a plan view of a main part of the semiconductor substrate showing FIG.

In the first embodiment, the BPSG forming the upper layer of the wiring 14 of the first layer and the first interlayer insulating film.
Silicon nitride film 1 for stopper disposed between the film 10 and
1 was provided only in the region where the through hole 16 was formed. However, as shown in FIG. 7, not only the region where the through hole 16 is formed, but the stopper silicon nitride film 11 may be formed entirely under the first-layer wiring 14.

At this time, the pattern size of the stopper silicon nitride film 11 located in the region where the through hole 16 is formed is determined by the alignment accuracy between the wiring 14 of the first layer and the through hole 16 and the first layer. The wiring 14 and the through hole 16 are designed with a margin that allows the processing dimensional accuracy and the through hole 16 processing dimensional accuracy.

According to the present embodiment, the first layer wiring 1
4 and the photoresist mask used in forming the stopper silicon nitride film 11 have different pattern dimensions, but the shapes are the same. Therefore, by using the same exposure mask and changing the exposure conditions, a photoresist mask for processing the first layer wiring 14 and a photoresist mask for processing the stopper silicon nitride film 11 are formed. Therefore, it is not necessary to manufacture a new exposure mask for processing the stopper silicon nitride film 11.

Next, a method of manufacturing the semiconductor integrated circuit device having the two-layer wiring according to the present embodiment will be described with reference to FIGS. 8 and 9.

First, as shown in FIG. 3, the first interlayer insulating film composed of the silicon oxide film 9 and the BPSG film 10 was formed on the MISFET by the manufacturing method similar to that of the first embodiment. After that, the thickness on the BPSG film 10 is 0.3
Plasma C with a silicon nitride film (not shown) of about 1.0 μm
It is deposited by the VD method.

Next, as shown in FIG. 8, a photoresist mask 19 is formed on the silicon nitride film in a region where the wiring 14 of the first layer will be formed later, and then the photoresist mask 19 is used. The above silicon nitride film is used as a μ wave EC
By processing with an R dry etching device, a stopper silicon nitride film 11 is formed.

Next, as shown in FIG. 9, after removing the photoresist mask 19, the stopper silicon nitride film 1 is formed.
1, the BPSG film 10, the silicon oxide film 9 and the silicon nitride film 5 are sequentially etched to form a contact hole 13, and then a first-layer wiring 14 is formed.

After that, the second interlayer insulating film made of the interlayer insulating film 15, the through hole 16 and the wiring 17 of the second layer are sequentially formed by the same manufacturing method as in the first embodiment.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above embodiment, the silicon nitride film is used as the stopper layer for etching when the second interlayer insulating film is processed to form the through hole, but the present invention is not limited to this. Any insulating film or conductive film having an etching ratio of 5 or more with respect to the insulating film forming the second interlayer insulating film may be used.

In the above-described embodiment, the stopper silicon nitride film used as the stopper layer for etching when the second interlayer insulating film is processed to form the through holes is processed by dry etching. It may be processed by etching.

Further, in the above-described embodiment, the case where the present invention is applied to the semiconductor integrated circuit device having the multilayer wiring of the two-layer structure including the wiring of the first layer and the wiring of the second layer has been described. It is also applicable to the semiconductor integrated circuit device having the multi-layer wiring.

Further, in the above-mentioned embodiment, the MISFET having the multilayer wiring and the manufacturing method thereof have been described, but the present invention can be applied to all the semiconductor devices having the multilayer wiring and the manufacturing method thereof.

[0058]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the through holes for connecting the wiring layers located above and below are formed without weakening the effect of the hydrogen annealing treatment for reducing the interface state between the gate insulating film of the MISFET and the semiconductor substrate. Since it can be surely formed only on the interlayer insulating film provided between the wiring layers, it is possible to reduce processing defects in the multilayer wiring without lowering the reliability of the semiconductor element.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a main part plan view of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 7 is a plan view of a principal portion of a semiconductor substrate showing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 9 is a main-portion cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device examined by the present inventors.

FIG. 11 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device examined by the present inventor.

[Explanation of symbols]

 1 semiconductor substrate 2 p-type well 3 field insulating film 4 gate insulating film 5 silicon nitride film 6 gate electrode 7 semiconductor region (source and drain region) 8 sidewall spacer 9 silicon oxide film 10 BPSG film 11 stopper silicon nitride film 12 photo Resist mask 13 Contact hole 14 Wiring 15 Interlayer insulating film 16 Through hole 17 Wiring 18 Passivation film 19 Photoresist mask

Claims (5)

[Claims] 1. A first wiring is located on the first interlayer insulating film, and a second interlayer insulating film is sandwiched between the first wiring and the second wiring.
Is located, and a through hole for connecting the second wiring and the first wiring is provided in the second interlayer insulating film, and the through hole is formed. An etching stopper layer is provided between the first wiring and the first interlayer insulating film in a region
The etching stopper layer has a pattern dimension designed with an allowance for alignment accuracy between the first wiring and the through hole, processing dimensional accuracy of the first wiring, and processing dimensional accuracy of the through hole. A semiconductor integrated circuit device characterized in that. 2. A first wiring is located on the first interlayer insulating film, and a second interlayer insulating film is sandwiched between the first wiring and the second wiring.
Wiring is located, and a through hole for connecting the second wiring and the first wiring is provided in the second interlayer insulating film, the semiconductor integrated circuit device comprising: An etching stopper layer is provided between the first interlayer insulating films, and the etching stopper layer located in a region where the through hole is formed has a positioning accuracy of the first wiring and the through hole. A semiconductor integrated circuit device having a pattern dimension designed with a margin that allows the processing dimensional accuracy of the first wiring and the processing dimensional accuracy of the through hole. 3. The semiconductor integrated circuit device according to claim 1, wherein the etching rate of the etching stopper layer is 1 / the etching rate of the second interlayer insulating film.
A semiconductor integrated circuit device characterized by being 5 or less. 4. The semiconductor integrated circuit device according to claim 1, wherein the second interlayer insulating film is a silicon oxide film, and the etching stopper layer is a silicon nitride film. Integrated circuit device. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, 2, 3 or 4, wherein low temperature hydrogen annealing treatment is performed in a step after the second wiring is formed. Manufacturing method of semiconductor integrated circuit device.