JPH07169765A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the coverage of an upper-layer interconnection film by a method wherein the cross-sectional shape of a through hole is formed to be a taper which is expanded in the upward direction regarding an interlayer insulating film using a TEOS film. CONSTITUTION:The manufacture is provided with a process wherein a silicon oxide film 4 is grown, by a vapor growth operation using tetraethyloxysilane (TEOS) as a raw-material gas, on at least the uppermost layer as an interlayer insulating film so as to cover a lower-layer interconnection 2 formed on a semiconductor substrate 1 and with a process wherein a film 5 whose etch rate is larger than that of the silicon oxide film and a resist film 6 having an opening part on the lower-layer interconnection are applied sequentially onto the silicon oxide film. In addition, the manufacture is provided with a process wherein the film inside the opening part and the silicon oxide film are etched in the longitudinal direction and the transverse direction by an isotropic etching operation by making use of the resist film as an etching mask and the interlayer insulating film which remains is then etched by an anisotropic etching operation so as to expose the surface of the lower-layer interconnection and with a process wherein an upper-layer interconnection which is connected to the lower- layer interconnection is formed on the interlayer insulating film so as to cover the opening part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for improving the coating of a through hole of a multilayer wiring device.

[0002]

Conventionally, a spin-on-glass (SOG) film was applied on a non-doped silicon dioxide (SiO ₂ ) film as an interlayer insulating film between a lower wiring and an upper wiring to improve the surface flatness, After growing a phosphosilicate glass (PSG) film on it, through holes for connecting upper and lower wirings are formed in this multilayer film.

For forming a through hole, anisotropic etching has been conventionally performed after isotropic etching.
At this time, since the uppermost layer of the inter-layer insulation film is the PSG film, lateral etching proceeds during isotropic etching, and the cross-sectional shape of the through hole becomes a tapered shape that expands in the upward direction. The film coverage was good.

However, at present, in order to simplify the process, SiO ₂ formed by plasma vapor deposition (P-CVD) on the interlayer insulating film.
On the (P-CVD SiO ₂ ) film, ozone (O ₃ ) and TEOS [Si (C ₂ H ₅ O) ₄ ]
A non-doped silicon oxide film (hereinafter, referred to as an O ₃ -TEOS film or simply a TEOS film) grown by using as a reaction gas is used.

When forming a through hole in this interlayer insulating film, the lateral etching of the O ₃ -TEOS film does not proceed by isotropic etching, so that the cross-sectional shape of the through hole is tapered upward. Absent. As a result, the problem that the aluminum (Al) film of the upper layer wiring deteriorates occurred.

[0006]

[Problems to be Solved by the Invention] O ₃ -T on P-CVD SiO ₂ film
In the interlayer insulating film with the EOS film formed, the cross-sectional shape of the through hole with a taper that expands upward as in the past cannot be obtained even if the type of etching gas is changed.

It is an object of the present invention to improve the covering of an upper wiring film by forming a taper that spreads upward in the sectional shape of a through hole when a TEOS film is used as an interlayer insulating film.

[0008]

[Means for Solving the Problems] To solve the above problems, 1) cover the lower layer wiring 2 formed on the semiconductor substrate 1,
A first step of growing a silicon oxide film 4 by vapor phase growth using tetraethyloxysilane (TEOS) as a source gas as at least an uppermost layer as an interlayer insulating film, and then etching the silicon oxide film on the silicon oxide film from the silicon oxide film. High-rate coating 5 and resist film having an opening on the lower wiring
The second step of sequentially depositing 6 and then the isotropic etching using the resist film as an etching mask to etch the film having the large etching rate and the silicon oxide film in the vertical and horizontal directions. Then, the third step of exposing the surface of the lower layer wiring by vertically etching the remaining interlayer insulating film by anisotropic etching, and then covering the opening on the interlayer insulating film. 4. A method for manufacturing a semiconductor device, which comprises a fourth step of forming an upper wiring connected to a lower wiring, or 2) a step of removing a coating film having an etching rate higher than that of the silicon oxide film before performing the fourth step. This is achieved by the semiconductor device manufacturing method described.

[0009]

In the present invention, an inorganic or organic SO film is formed between the TEOS film and the resist film having an opening which is an etching mask.
By sandwiching the G film, the etching rate of the uppermost SOG film during isotropic etching is large, so lateral etching proceeds, and the SOG film under the resist film in the opening recedes and the etching gas retreats. The TEOS film underneath is etched laterally. As a result, a through hole having a taper that spreads upward is formed in the interlayer insulating film, and the covering of the upper wiring film is improved.

[0010]

1 (A) to 1 (C) are sectional views for explaining an embodiment of the present invention. In FIG. 1 (A), a silicon (Si) substrate having a patterned insulating film deposited on the surface after the bulk process of device fabrication is used as a semiconductor substrate 1,
The lower layer wiring 2 is formed on top of that, and the interlayer insulating film is formed.

The thickness of the inter-layer insulation film is first measured by the P-CVD method.
A 2000 Å SiO ₂ film (or even a SiON film) 3 is grown, and then a 7000 Å thick O ₃ -TEOS film 4 is grown thereon.

At this time, a P-TEOS film formed by the P-CVD method may be used instead of the O ₃ -TEOS film. Then on this TE
An inorganic or organic SOG film 5 is applied as a film with a higher etch rate than the OS film, and the SOG film is cured by heating to form a film with a thickness of 1500Å.

Then, a resist film 6 is deposited on the SOG film, patterned to form an opening, and etching for forming a through hole is performed. As shown in Fig. 1 (B), first, isotropic etching is performed to etch about 1/3 of the total film thickness, and then the remaining 2/3 is anisotropic as shown in Fig. 1 (C). It is opened by reactive etching.

In the subsequent steps, the resist film 6 is removed, the SOG film 5 is removed, and an upper wiring film covering the through holes and connected to the lower wiring is deposited. At this time, SO
If the G film 5 is left attached, the flatness of the substrate surface can be improved, but degassing from the SOG film reduces the reliability of the connecting metal (Via) in the through hole. It is desirable to move to the process.

Next, an example of the etching conditions used in the examples will be shown. Isotropic etching Etching gas: CH ₄ , O ₂ Gas flow rate: 400, 100 SCCM Gas pressure: 1 Torr RF power: 1 kW Anisotropic etching Etching gas: CHF ₃ , CF ₄ , Ar gas flow rate: 60, each 60, 100 SCCM Gas pressure: 1.7 Torr RF power: 0.6 kW FIGS. 2 (A) and 2 (B) are diagrams showing the effect of the present invention.

FIG. 2 (A) is a sectional view of the embodiment, and FIG. 2 (B) is a sectional view of a conventional zero, both of which are cross-sectional photographs. In the figure, 7 is the upper layer wiring, which is an Al film. From the figure, it is apparent that the coating of the upper wiring film in the embodiment is improved.

In the embodiment, the SOG film is used as the film having a higher etching rate than the TEOS film, but the present invention is not limited to this.

[0018]

According to the present invention, the sectional shape of the through hole of the interlayer insulating film using the TEOS film can be tapered upwardly. As a result, the coating of the upper wiring film can be improved, the contact resistance of the inter-wiring connection part (Via) is reduced, and the resistance to electromigration is improved.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating an embodiment of the present invention.

FIG. 2 is a diagram showing the effect of the present invention.

[Explanation of symbols]

1 Semiconductor substrate and Si substrate 2 Lower layer wiring 3 P-CVD SiO ₂ film 4 O ₃ -TEOS film 5 SOG film 6 Resist film 7 Upper layer wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/768 H01L 21/90 C

Claims (2)

[Claims] 1. A lower layer wiring formed on a semiconductor substrate (1)
A first step of growing the silicon oxide film (4) covering the (2) by vapor phase growth using tetraethyloxysilane (TEOS) as a source gas as at least the uppermost layer as an interlayer insulating film, and then the silicon oxide film. A second step of sequentially depositing a film (5) having a higher etching rate than the silicon oxide film on the film and a resist film (6) having an opening on the lower layer wiring, and then etching masking the resist film As isotropic etching, the film and the silicon oxide film in the opening are etched, and then the remaining interlayer insulating film is etched by anisotropic etching to expose the surface of the lower layer wiring. A method of manufacturing a semiconductor device, comprising: a step of: and then a fourth step of forming an upper layer wiring on the interlayer insulating film to cover the opening and connect to the lower layer wiring. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a film having an etching rate higher than that of the silicon oxide film is removed before the fourth step is performed.