JPH06120166A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06120166A
JPH06120166A JP26569692A JP26569692A JPH06120166A JP H06120166 A JPH06120166 A JP H06120166A JP 26569692 A JP26569692 A JP 26569692A JP 26569692 A JP26569692 A JP 26569692A JP H06120166 A JPH06120166 A JP H06120166A
Authority
JP
Japan
Prior art keywords
film
semiconductor substrate
layer
wiring
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26569692A
Other languages
Japanese (ja)
Other versions
JP2845054B2 (en
Inventor
Matsutomo Mori
松倫 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26569692A priority Critical patent/JP2845054B2/en
Publication of JPH06120166A publication Critical patent/JPH06120166A/en
Application granted granted Critical
Publication of JP2845054B2 publication Critical patent/JP2845054B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prepare a semiconductor device which can suppress the generation of a void due to a TiN film of the upper layer of an Al-Si-Cu film, or, to be specific, to provide the forming of wiring. CONSTITUTION:A PSG film 4 is formed into 2 a pattern on a semiconductor substrate 5, a TiN film is deposited, and, after heat treatment in a nitrogen atmosphere, an Al film 6 is deposited. Next, a TiN film is deposited and subjected to heat treatment in a nitrogen atmosphere. Because the TiN film of the uppermost layer is completely nitrified through heat treatment, the generation of a void in the Al film 6 side wall due to an unreacted Ti is suppressed, and the wiring of a semiconductor device of high reliability is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に半導体基板に形成された半導体装置の配線の
形成方法を関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming wiring of a semiconductor device formed on a semiconductor substrate.

【0002】[0002]

【従来の技術】従来、半導体装置においては図3に示す
様に、その半導体素子間を電気的に結線する為に、所定
の膜厚に形成されたAl薄膜パターニング時の光の反射
防止膜としてのTiN膜とAl薄膜及びAl薄膜と半導
体基板との反応を抑制するTi、TiN膜とで構成され
ている。
2. Description of the Related Art Conventionally, as shown in FIG. 3, a semiconductor device has been used as a light antireflection film at the time of patterning an Al thin film having a predetermined film thickness in order to electrically connect the semiconductor elements. The TiN film and the Al thin film and the Ti and TiN films which suppress the reaction between the Al thin film and the semiconductor substrate.

【0003】半導体基板5上にPSG膜4がパターン形
成されており、このPSG膜4に設けたコンタクトホー
ルを介して、半導体基板5と接触する様にしてTi膜
1、TiN膜2の2層構造からなる配線が形成される
(図3(a))。その後、N2 雰囲気にて、熱処理をし
(図3(b))、Al−Si−Cu膜6を堆積させた後
(図3(c))、TiN膜7を堆積させる(図3
(d))。
A PSG film 4 is patterned on a semiconductor substrate 5, and two layers of a Ti film 1 and a TiN film 2 are formed so as to come into contact with the semiconductor substrate 5 through a contact hole provided in the PSG film 4. Wiring having a structure is formed (FIG. 3A). After that, heat treatment is performed in an N 2 atmosphere (FIG. 3B), the Al—Si—Cu film 6 is deposited (FIG. 3C), and then the TiN film 7 is deposited (FIG. 3).
(D)).

【0004】従来のTiN/Al−Si−Cu/TiN
/Ti膜におけるAl−Si−Cu膜下層のTiN/T
i膜は、Al−Si−Cu膜と半導体基板(コンタク
ト)との反応を抑える為に使用されていた。またAl−
Si−Cu膜上層のTiN膜は、Al−Si−Cu膜パ
ターニング時の反射防止膜として、使用されており、ま
た、最上層のTiN膜には、熱処理は行わない。
Conventional TiN / Al-Si-Cu / TiN
Ti / T under the Al-Si-Cu film in the Ti / Ti film
The i film was used to suppress the reaction between the Al-Si-Cu film and the semiconductor substrate (contact). Also Al-
The TiN film on the upper layer of the Si-Cu film is used as an antireflection film when patterning the Al-Si-Cu film, and the uppermost TiN film is not heat-treated.

【0005】[0005]

【発明が解決しようとする課題】従来の半導体装置の製
造方法により形成された配線では、Al−Si−Cu膜
の側壁にAl−Si−Cu上層にある未反応Tiが原因
で発生する直径約10〜100nmの微小なボイドが発
生し、配線材としてのAl−Si−Cu膜の信頼性を著
しく劣化させるという問題点があった。
In the wiring formed by the conventional method of manufacturing a semiconductor device, the diameter of the Al-Si-Cu film, which is caused by the unreacted Ti in the upper layer of the Al-Si-Cu film, is about the same. There is a problem in that minute voids of 10 to 100 nm are generated and the reliability of the Al-Si-Cu film as a wiring material is significantly deteriorated.

【0006】本発明の目的は、半導体基板上に形成され
た集積回路素子を接続する配線を形成するに際し、Ti
N化されていない未反応TiによるAl−Si−Cuの
側壁にボイドの発生が生ずるのを抑えられる半導体装置
の製造方法を提供することにある。
It is an object of the present invention to form Ti when connecting wirings for connecting integrated circuit elements formed on a semiconductor substrate.
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of suppressing the generation of voids on the side walls of Al—Si—Cu due to unreacted Ti that has not been converted to N.

【0007】[0007]

【課題を解決するための手段】本発明の第1の発明の半
導体装置の製造方法は、半導体基板上に形成された集積
回路素子を接続する配線を形成する方法において、半導
体基板上に形成された絶縁膜にコンタクトホールを形成
する工程と、前記コンタクトホールを介して半導体基板
と接するように第1層膜としてTi膜、第2層膜として
TiN膜からなる2層構造の配線を形成する工程と、2
層構造の配線の形成された半導体基板を窒素雰囲気にて
熱処理する工程と、第3層膜としてAl−Si−Cu
膜、第4層膜としてTiN膜を第2層膜上に形成する工
程と、前記4層構造の配線の形成された半導体基板を窒
素雰囲気中で熱処理する工程とを含んで構成される。
A method of manufacturing a semiconductor device according to a first aspect of the present invention is a method of forming wirings for connecting integrated circuit elements formed on a semiconductor substrate, wherein the wiring is formed on the semiconductor substrate. A step of forming a contact hole in the insulating film, and a step of forming a wiring having a two-layer structure including a Ti film as a first layer film and a TiN film as a second layer film so as to be in contact with the semiconductor substrate through the contact hole. And 2
A step of heat-treating the semiconductor substrate on which the wiring of the layer structure is formed in a nitrogen atmosphere, and Al--Si--Cu as a third layer film
Film, a step of forming a TiN film as a fourth layer film on the second layer film, and a step of heat-treating the semiconductor substrate on which the wiring of the four-layer structure is formed in a nitrogen atmosphere.

【0008】また、本発明の第2の発明の半導体装置の
製造方法は、半導体基板上に形成された集積回路素子を
接続する配線を形成する方法において、半導体基板上に
形成された絶縁膜にコンタクトホールを形成する工程
と、前記コンタクトホールを介して半導体基板と接する
ように第1層膜としてTi膜、第2層膜としてTiN膜
からなる2層構造の配線を形成する工程と、2層構造の
配線の形成された半導体基板を窒素雰囲気にて熱処理す
る工程と、第3層としてAl−Si−Cu膜、第4層膜
としてWSi膜を形成する工程とを有することを特徴と
して構成される。
A method of manufacturing a semiconductor device according to a second aspect of the present invention is a method of forming a wiring for connecting an integrated circuit element formed on a semiconductor substrate, wherein the insulating film formed on the semiconductor substrate is formed. A step of forming a contact hole, a step of forming a wiring having a two-layer structure composed of a Ti film as a first layer film and a TiN film as a second layer film so as to contact the semiconductor substrate through the contact hole, and two layers It is characterized in that it has a step of heat-treating a semiconductor substrate on which a wiring having a structure is formed in a nitrogen atmosphere, and a step of forming an Al-Si-Cu film as a third layer and a WSi film as a fourth layer film. It

【0009】[0009]

【実施例】次に本発明について図面を参照する。図1
は、本発明の一実施例の半導体装置の製造方法を説明す
るために工程順に示した半導体基板の断面図である。
DETAILED DESCRIPTION OF THE INVENTION Reference will now be made to the drawings of the present invention. Figure 1
FIG. 6A is a cross-sectional view of the semiconductor substrate shown in order of steps for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

【0010】まず、図1(a)に示すように、半導体基
板5上にPSG膜4がパターン形成されており、このP
SG膜4に設けたコンタクトホールを介して半導体基板
5と接触する様にして、Ti膜1、TiN膜2の2層構
造からなる配線を形成する。
First, as shown in FIG. 1A, a PSG film 4 is formed on a semiconductor substrate 5 by patterning.
A wiring having a two-layer structure of the Ti film 1 and the TiN film 2 is formed so as to come into contact with the semiconductor substrate 5 through the contact hole provided in the SG film 4.

【0011】その後図1(b)に示すように、N2 雰囲
気にて熱処理をする。次いで図1(c)に示すように、
Al−Si−Cu膜6を堆積させる。次に図1(d)に
示すように、TiN膜2を堆積させ、次いで、Alが溶
融しない温度にて、N2 雰囲気にて熱処理(600℃以
下、30秒以上)を行なう。
Thereafter, as shown in FIG. 1B, heat treatment is performed in an N 2 atmosphere. Then, as shown in FIG.
The Al-Si-Cu film 6 is deposited. Next, as shown in FIG. 1D, a TiN film 2 is deposited, and then heat treatment (600 ° C. or less, 30 seconds or more) is performed in an N 2 atmosphere at a temperature at which Al does not melt.

【0012】上述した本実施例1では、4層のTiN膜
を堆積した後、従来では実施していなかったN2 雰囲気
での熱処理を行なうので、完全に窒化されていない未反
応Tiがなくなり、未反応Tiによる直径10〜100
nmの微小なボイドがAl−Si−Cu膜6の側壁に発
生しにくいという効果がある。
In the first embodiment described above, after the TiN films of four layers are deposited, the heat treatment is performed in the N 2 atmosphere which has not been conventionally performed, so that unreacted Ti that is not completely nitrided is eliminated. Diameter 10-100 with unreacted Ti
This has the effect that minute voids of nm are unlikely to occur on the side wall of the Al-Si-Cu film 6.

【0013】図2は、本発明の他の実施例の半導体装置
の製造方法を説明するために工程順に示した半導体基板
の断面図である。図2(a)に示すように、半導体基板
5上にPSG膜4がパターン形成されており、このPS
G膜4に設けたコンタクトホールを介して半導体基板5
と接触するようにして、Ti膜1、TiN膜2の2層構
造からなる配線が形成する。その後、図2(b)に示す
ように、N2 雰囲気にて熱処理をする。次いで図2
(c)に示すように、Al−Si−Cu膜6を堆積させ
る。次に、図2(d)に示すように、WSi膜を堆積す
る。
2A to 2D are cross-sectional views of a semiconductor substrate, which are shown in the order of steps for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention. As shown in FIG. 2A, the PSG film 4 is patterned on the semiconductor substrate 5.
Semiconductor substrate 5 through the contact hole provided in G film 4
A wiring having a two-layer structure of a Ti film 1 and a TiN film 2 is formed so as to come into contact with. Then, as shown in FIG. 2B, heat treatment is performed in an N 2 atmosphere. Then Fig. 2
As shown in (c), an Al-Si-Cu film 6 is deposited. Next, as shown in FIG. 2D, a WSi film is deposited.

【0014】この実施例2では、第4層にWSi膜を用
いる為、Al−Si−Cu膜6の側壁にTiによるボイ
ドが発生しないという効果があり、かつAl消失耐性が
強いという効果がある。
In the second embodiment, since the WSi film is used for the fourth layer, there is an effect that voids due to Ti do not occur on the side wall of the Al-Si-Cu film 6 and that the Al loss resistance is strong. .

【0015】[0015]

【発明の効果】以上説明した様に、本発明によれば、A
l−Si−Cu膜の上層がN2 雰囲気で熱処理をされた
TiN膜、もしくはWSi膜となっている為、TiN化
されていない未反応Tiによる、Al−Si−Cuの側
壁にボイドの発生が抑えられるという効果を有する。従
来のN2 雰囲気で熱処理されていない最上層TiN構造
だとボイドの発生率は約50%の確率で発生するが、上
記構造にすることで、0に抑えることができる。
As described above, according to the present invention, A
Since the upper layer of the 1-Si-Cu film is a TiN film or a WSi film that has been heat-treated in an N 2 atmosphere, unreacted Ti that has not been converted to TiN causes the occurrence of voids on the side walls of Al-Si-Cu. Has the effect of being suppressed. In the TiN structure of the uppermost layer that has not been heat-treated in the conventional N 2 atmosphere, the occurrence rate of voids occurs with a probability of about 50%, but with the above structure, it can be suppressed to zero.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明するために工程順に示
した半導体基板の縦断面図である。
FIG. 1 is a vertical cross-sectional view of a semiconductor substrate shown in order of steps for explaining an embodiment of the present invention.

【図2】本発明の他の実施例を説明するために工程順に
示した半導体基板の縦断面図である。
FIG. 2 is a vertical cross-sectional view of a semiconductor substrate shown in the order of steps for explaining another embodiment of the present invention.

【図3】従来の半導体装置の製造方法を説明するために
工程順に示した半導体基板の縦断面図である。
FIG. 3 is a vertical cross-sectional view of a semiconductor substrate, which is shown in order of steps for explaining a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 Ti膜 2 TiN膜 3 WSi膜 4 PSG膜 5 半導体基板 6 Al−Si−Cu膜 1 Ti film 2 TiN film 3 WSi film 4 PSG film 5 Semiconductor substrate 6 Al-Si-Cu film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に形成された集積回路素子
を接続する配線を形成する方法において、半導体基板上
に形成された絶縁膜にコンタクトホールを形成する工程
と、前記コンタクトホールを介して半導体基板と接する
ように第1層膜としてTi膜、第2層膜としてTiN膜
からなる2層構造の配線を形成する工程と、2層構造の
配線の形成された半導体基板を窒素雰囲気にて熱処理す
る工程と、第3層膜としてAl−Si−Cu膜、第4層
膜としてTiN膜を第2層膜上に形成する工程と、前記
4層構造の配線の形成された半導体基板を窒素雰囲気中
で熱処理する工程とを含むことを特徴とする半導体装置
の製造方法。
1. A method for forming a wiring for connecting an integrated circuit element formed on a semiconductor substrate, the method comprising: forming a contact hole in an insulating film formed on the semiconductor substrate; and a semiconductor through the contact hole. A step of forming a two-layer structure wiring made of a Ti film as a first layer film and a TiN film as a second layer film so as to be in contact with the substrate, and a semiconductor substrate having the two-layer structure wiring formed thereon is heat-treated in a nitrogen atmosphere. And a step of forming an Al—Si—Cu film as a third layer film and a TiN film as a fourth layer film on the second layer film, and a semiconductor substrate on which the wiring of the four-layer structure is formed in a nitrogen atmosphere. And a step of performing heat treatment therein.
【請求項2】 半導体基板上に形成された集積回路素子
を接続する配線を形成する方法において、半導体基板上
に形成された絶縁膜にコンタクトホールを形成する工程
と、前記コンタクトホールを介して半導体基板と接する
ように第1層膜としてTi膜、第2層膜としてTiN膜
からなる2層構造の配線を形成する工程と、2層構造の
配線の形成された半導体基板を窒素雰囲気にて熱処理す
る工程と、第3層としてAl−Si−Cu膜、第4層膜
としてWSi膜を形成する工程とを有することを特徴と
する半導体装置の製造方法。
2. A method of forming a wiring for connecting an integrated circuit element formed on a semiconductor substrate, the method comprising: forming a contact hole in an insulating film formed on the semiconductor substrate; and a semiconductor through the contact hole. A step of forming a two-layer structure wiring made of a Ti film as a first layer film and a TiN film as a second layer film so as to be in contact with the substrate, and a semiconductor substrate having the two-layer structure wiring formed thereon is heat-treated in a nitrogen atmosphere. And a step of forming an Al-Si-Cu film as the third layer and a WSi film as the fourth layer film.
JP26569692A 1992-10-05 1992-10-05 Method for manufacturing semiconductor device Expired - Lifetime JP2845054B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26569692A JP2845054B2 (en) 1992-10-05 1992-10-05 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26569692A JP2845054B2 (en) 1992-10-05 1992-10-05 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH06120166A true JPH06120166A (en) 1994-04-28
JP2845054B2 JP2845054B2 (en) 1999-01-13

Family

ID=17420744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26569692A Expired - Lifetime JP2845054B2 (en) 1992-10-05 1992-10-05 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2845054B2 (en)

Also Published As

Publication number Publication date
JP2845054B2 (en) 1999-01-13

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