JPS62245641A - Structure of pad part of semiconductor device - Google Patents
Structure of pad part of semiconductor deviceInfo
- Publication number
- JPS62245641A JPS62245641A JP61089277A JP8927786A JPS62245641A JP S62245641 A JPS62245641 A JP S62245641A JP 61089277 A JP61089277 A JP 61089277A JP 8927786 A JP8927786 A JP 8927786A JP S62245641 A JPS62245641 A JP S62245641A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- low
- pad part
- semiconductor device
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims abstract description 4
- 238000004528 spin coating Methods 0.000 claims abstract description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 3
- 230000005284 excitation Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 20
- 206010040844 Skin exfoliation Diseases 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
多層配線の形成は、基板上にＰＳＧ、ＳＬＯ□等の第１
の絶縁膜が積層され、その上に第１のＡ／配線層が形成
される。□更に第２の絶縁膜、その上に第２の配線層と
積層されるが、第１の配線層の形成後、配線層の平坦化
、Ａｌの突起押さえ等のため低温で被着せる絶縁膜（低
温絶縁膜）が積層されるが、密着性が良くないためボン
ディング・パッド部で剥離を生じ易い。本発明はパッド
部領域で上記低温絶縁膜を除去することにより剥離問題
の解決を行った。[Detailed Description of the Invention] [Summary] The formation of multilayer interconnection involves the formation of a first layer of PSG, SLO□, etc. on a substrate.
Insulating films are stacked, and a first A/wiring layer is formed thereon. □Furthermore, a second insulating film and a second wiring layer are laminated thereon. After the formation of the first wiring layer, an insulating film is deposited at a low temperature to flatten the wiring layer, suppress Al protrusions, etc. (low-temperature insulating film) is laminated, but its adhesion is poor and peeling tends to occur at the bonding pad area. The present invention solves the peeling problem by removing the low temperature insulating film in the pad area.
（産業上の利用分野）
本発明は、多層配線構造を含む半導体装置のボンディン
グ・パッド部の構造に関する。(Industrial Application Field) The present invention relates to a structure of a bonding pad portion of a semiconductor device including a multilayer wiring structure.
多層配線構造の半導体装置では、第１のＡＩｌ配線層＜
ｆｉ、ｌ−１と称す）が第１のｗＡ縁膜（絶縁膜−１，
）上に形成され、更に配線層間の絶縁膜として第２の絶
縁膜（絶縁膜−■）が積層された後、第２のＡ７！配線
層（ＡＮ−ＩＩ）が形成される。In a semiconductor device with a multilayer wiring structure, the first AIl wiring layer<
fi, l-1) is the first wA edge film (insulating film-1,
), and after a second insulating film (insulating film -■) is further laminated as an insulating film between wiring layers, a second A7! A wiring layer (AN-II) is formed.
実際の多層配線構造ではＡｌ−１の形成後、基板の平坦
化、ＡＡ−Ｉ表面で発生する突起防止のため低温絶縁膜
を積層する。In an actual multilayer wiring structure, after forming Al-1, a low-temperature insulating film is laminated to flatten the substrate and prevent protrusions from occurring on the AA-I surface.
上記低温絶縁膜の被着はへβ配線層との反応を抑えるた
めに、形成温度は出来るだけ低いことが望ましい。ＰＶ
Ｄ手法、あるいはＣＶＤ手法が適用されるが通常、被着
は４００℃以下の温度で形成が行われる（本発明では、
上記の温度条件を低温と呼ぶ）。It is desirable that the formation temperature of the low-temperature insulating film be as low as possible in order to suppress reaction with the beta wiring layer. PV
D method or CVD method is applied, but deposition is usually performed at a temperature of 400°C or less (in the present invention,
The above temperature conditions are called low temperatures).
低温絶縁膜の被着は密着性が良くないので、絶縁膜−■
、低温絶縁膜、絶縁膜−■の上に形成されたＡｌ」層の
ボンディング・パッド部ではリード線をボンディング後
、低温絶縁膜よりパッド部での剥離を生じ易く改善が要
望されている。The adhesion of the low-temperature insulating film is not good, so the insulating film -■
, Low-temperature insulating film, Insulating film - In the bonding pad portion of the Al layer formed on the insulating film -1, after lead wires are bonded, peeling occurs more easily at the pad portion than the low-temperature insulating film, and improvement is desired.
Ｃ従来の技術〕
従来の技術での多層配線構造を第３図（８１，（ｂｌに
より説明する。（ａ）はパッド部の断面であり、［ｂ）
はパッド部以外の素子領域上の断面を示す。C. Prior Art] The multilayer wiring structure according to the conventional technology is explained in FIG.
shows a cross section on the element region other than the pad portion.
半導体基板１上には熱酸化による５ｊ０２膜２が形成さ
れ、更に絶縁膜−１（ＰＳＧ膜）３がＳｉＨ，。A 5J02 film 2 is formed on the semiconductor substrate 1 by thermal oxidation, and an insulating film 1 (PSG film) 3 is made of SiH.
ＰＨ３，０□を含む反応ガスを用いたＣＶＤ法により積
層される。Lamination is performed by a CVD method using a reaction gas containing PH3.0□.
絶縁膜−Ｉは基板の表面を平坦化をはかるため、Ｐの濃
度は比較的大きく選び、成長温度も素子領域に悪影響を
与えない程度に高く、例えば７００℃前後の値に選ばれ
る。In order to planarize the surface of the substrate in the insulating film-I, the concentration of P is selected to be relatively large, and the growth temperature is also selected to be high enough not to adversely affect the device region, for example, around 700°C.
次いで、スパッタ法により第１の配線層（Ａｌ−■）４
を被着して、パターンニングされる。Next, a first wiring layer (Al-■) 4 is formed by sputtering.
is applied and patterned.
／ｌ’−１の形成後、直接ＰＳＧ膜等による層間絶縁膜
を積層して、第２の配線層（ＡＡ−１））を形成する場
合もあるが、下地の段差を緩和し、更にＡｌ配線で発生
する突起による眉間ショートを防止するため、低温絶縁
膜を被着する。After the formation of /l'-1, a second wiring layer (AA-1) may be formed by directly laminating an interlayer insulating film such as a PSG film. A low-temperature insulating film is applied to prevent short-circuits between the eyebrows due to protrusions caused by wiring.
上記低温絶縁膜５の被着は、既にＡ７！−１が形成され
ているので、Ａｆｆの活性化温度より低い温度で行うこ
とが必要である。The low-temperature insulating film 5 has already been deposited on A7! -1 is formed, it is necessary to perform the process at a temperature lower than the activation temperature of Aff.
通常、ＡＪの活性化温度は約４００℃であり、上記低温
絶縁膜５の被着も、これより低い温度であることが要求
される。Normally, the activation temperature of AJ is about 400° C., and the deposition of the low-temperature insulating film 5 is also required to be at a lower temperature than this.
上記低温成長の手法として、Ｐ、ＶＤ法でターゲットに
ＳｊＯ□を用いたスパッタ法、プラズマ励起により約３
５０℃でのＣＶＤ法による５ｉＯ２１）＃成長、Ｓ ｉ
Ｏｚを含む溶液をスピンコートして乾燥する方法等の
何れかが適用される。The low-temperature growth method mentioned above includes the sputtering method using SjO□ as a target using the P, VD method, and plasma excitation.
5iO21) #growth by CVD method at 50°C, Si
Any method such as spin-coating a solution containing Oz and drying it may be applied.
上記手法により被着せる低温絶縁膜は、下地の段差を緩
和し、またＡｌ配線層をカバーして以後のプロセスで発
生するＡ７！突起を押さえ込む機能を果たす。The low-temperature insulating film deposited by the above method alleviates the level difference in the underlying layer and covers the Al wiring layer, which will cause A7! It functions to hold down protrusions.
その後、眉間絶縁膜として絶縁膜−■６を成長させる。Thereafter, an insulating film -16 is grown as an insulating film between the eyebrows.
絶縁膜−■もＰＳＧ膜が主として用いられるが、Ａ７！
−１に対する悪影響を与えることのないよう約４２５℃
のＣＶＤ法で成長させる。Insulating film-■ is also mainly a PSG film, but A7!
Approximately 425℃ to avoid any negative effects on -1.
It is grown using the CVD method.
絶縁膜−■と低温絶縁膜に必要なるスルーホール７を開
孔し、第２の配線層８ （Ａｌ」）を積層してパターン
ニングを行う。Through-holes 7 necessary for the insulating film -1 and the low-temperature insulating film are opened, and a second wiring layer 8 (Al) is laminated and patterned.
最後に保護膜９を積層し、ｋｌ−ｎのパッド部１０を開
孔して集積回路の形成を終わる。Finally, a protective film 9 is laminated, and the kl-n pad portions 10 are opened to complete the formation of the integrated circuit.
上記に述べた、従来の多層配線層の形成方法では低温絶
縁膜と上下の絶縁膜−１、絶縁膜−■との密着性が悪い
ことである。In the conventional method for forming a multilayer wiring layer as described above, the adhesion between the low-temperature insulating film and the upper and lower insulating films 1 and 2 is poor.
特にパッド部では、リード線がボンディングされる時に
機械的ストレスが加わる。In particular, mechanical stress is applied to the pad portion when the lead wire is bonded.
このため低温絶縁層の上下の界面で剥離を生じ信幀性の
低下、不良の原因となる。This causes peeling at the upper and lower interfaces of the low-temperature insulating layer, lowering reliability and causing defects.
上記剥離の問題は、リード線のボンディングの行われる
パッド部領域で発生するので、パッド部領域の下部に被
着せる低温絶縁膜を除去することよりなる本発明のパッ
ド部構造によって解決される。Since the above-mentioned peeling problem occurs in the pad area where the lead wire is bonded, it is solved by the pad structure of the present invention, which consists of removing the low-temperature insulating film deposited under the pad area.
パッド部を形成する領域は素子領域を離れた周辺部にあ
り、パッド部は寸法も比較的太きくＡＩｌの突起による
層間ショートの問題もない。The area where the pad portion is formed is located in the peripheral area away from the element area, and the pad portion is relatively thick in size and there is no problem of interlayer short circuits due to the protrusions of AI1.
パッド部には密着性の悪い低温絶縁膜が除去されている
ので、リード線のボンディングのストレスが加わっても
、これによって剥離を発生する恐れはない。Since the low-temperature insulating film with poor adhesion has been removed from the pad portion, there is no risk of peeling even if the stress of lead wire bonding is applied.
（実施例）
本発明による一実施例を図面により詳細説明する。従来
の技術の項において用いた同一符号は説明を省略する。(Example) An example according to the present invention will be described in detail with reference to the drawings. Description of the same reference numerals used in the prior art section will be omitted.
第１図はパッド部領域の低温絶縁膜５のみ除去せる例で
、低温絶縁膜を被着した後、パッド部のパターンよりな
るマスクを用い、パッド部の低温絶縁膜のみエツチング
除去するものである。以後の工程は従来の方法と特に変
わりはない。FIG. 1 shows an example in which only the low-temperature insulating film 5 in the pad area can be removed. After the low-temperature insulating film is deposited, a mask consisting of the pattern of the pad part is used to remove only the low-temperature insulating film in the pad part by etching. . The subsequent steps are not particularly different from the conventional method.
第２図は別の実施例で、スルーホール開孔時に使用する
マスクに、必要なるパッド・パターンを加えたパターン
を用いる。絶縁膜−■６を積層した後、上記マスクを用
いてスルーホールを開孔すると、同時にパッド部の絶縁
膜−■と低温絶縁膜も除去される。従って、マスク工程
の追加を必要としない。FIG. 2 shows another embodiment, in which a pattern is used in which a necessary pad pattern is added to the mask used for forming through-holes. After laminating the insulating film -16, a through hole is opened using the above mask, and at the same time, the insulating film -2 and the low-temperature insulating film at the pad portion are also removed. Therefore, no additional mask process is required.
上記実施例において、低温絶縁膜５及び絶縁膜−１）６
はそれぞれ一層の絶縁膜として説明した力（、それぞれ
複数層であってもよい。In the above embodiment, the low temperature insulating film 5 and the insulating film-1) 6
are each explained as a single layer of insulating film (each may be a plurality of layers).
また、低温絶縁膜を複数の絶縁膜−■で挟んだ構造、あ
るいは絶縁膜−■を複数の低温絶縁膜で挟んだ構造にお
いても適用可能である。Further, it is also applicable to a structure in which a low-temperature insulating film is sandwiched between a plurality of insulating films -2, or a structure in which an insulating film -2 is sandwiched between a plurality of low-temperature insulating films.
以上に説明せるごとく、本発明のノで・ノド部領域の低
温絶縁膜を除去する構造により、ノ（・ノド部しこおけ
る剥離不良の発生がなく、信頼性の高１．＞多層配線半
導体装置が得られる。As explained above, the structure of the present invention, which removes the low-temperature insulating film in the throat area, eliminates the occurrence of peeling defects in the throat area, resulting in high reliability. A device is obtained.
第１図は本発明にかかわるバ・ノド部の構造を示す断面
図、
第２図は本発明にかかわる別の実施例を示す断面図、
第３図（ａ）、 （ｂｌは従来の技術による多層配線構
造を説明する断面図、
を示す。
図面において、
１は基板、
２は熱酸化膜（Ｓ１０□膜）、
３は第１の絶縁膜（Ｐ Ｓ Ｇ膜）、
４は第１の配線層（ＡＮ−１）、
５は低温絶縁膜、
６は第２の絶縁膜（ＰＳＧ膜）、
７はスルーホール、
８は第２の配線層（Ａｌｌ−ＩＩ）、
９は保護膜、
ｌＯはパッド部、
をそれぞれ示す。
Ｉ泗月にり・り・ｂるノ〜ビ勧珊晩道Ｘ寸・巧諺晰酌図
第１図
第２図Fig. 1 is a sectional view showing the structure of the blade/nod part related to the present invention, Fig. 2 is a sectional view showing another embodiment related to the present invention, Fig. 3(a), (bl is based on the conventional technology) A cross-sectional view illustrating a multilayer wiring structure is shown. In the drawing, 1 is a substrate, 2 is a thermal oxide film (S10□ film), 3 is a first insulating film (PSG film), and 4 is a first wiring. layer (AN-1), 5 is a low-temperature insulating film, 6 is a second insulating film (PSG film), 7 is a through hole, 8 is a second wiring layer (All-II), 9 is a protective film, IO is The pads are shown respectively.
Claims (2)
に、４００℃以下で被着せる低温絶縁膜（５）、及び第
２の絶縁膜（６）を設ける多層配線構造を含む半導体装
置において、 該第２の配線層により形成されたパッド部（１０）領域
の下部に被着された、前記低温絶縁膜（５）が除去され
た構造よりなることを特徴とする半導体装置のパッド部
構造。(1) Multilayer wiring in which a low-temperature insulating film (5) deposited at 400°C or less and a second insulating film (6) are provided between the first wiring layer (4) and the second wiring layer (8) A semiconductor device including the structure, characterized in that the structure is such that the low temperature insulating film (5) deposited under the pad region (10) formed by the second wiring layer is removed. Pad structure of semiconductor device.
れるスパッタ法、プラズマ励起ＣＶＤ法、スピンコート
法の何れかのプロセスにより被着せる絶縁膜よりなるこ
とを特徴とする特許請求範囲第（１）項記載の半導体装
置のパッド部構造。(2) The low-temperature insulating film is an insulating film deposited by any one of sputtering, plasma-enhanced CVD, and spin coating at temperatures below 400°C. Pad portion structure of the semiconductor device described in (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61089277A JPS62245641A (en) | 1986-04-17 | 1986-04-17 | Structure of pad part of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61089277A JPS62245641A (en) | 1986-04-17 | 1986-04-17 | Structure of pad part of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62245641A true JPS62245641A (en) | 1987-10-26 |
Family
ID=13966231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61089277A Pending JPS62245641A (en) | 1986-04-17 | 1986-04-17 | Structure of pad part of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62245641A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02122654A (en) * | 1988-11-01 | 1990-05-10 | Fujitsu Ltd | Manufacturing method of semiconductor device |
-
1986
- 1986-04-17 JP JP61089277A patent/JPS62245641A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02122654A (en) * | 1988-11-01 | 1990-05-10 | Fujitsu Ltd | Manufacturing method of semiconductor device |
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