JPS61289649A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To check generation of cracks and disconnections of a wiring at manufacture of a semiconductor device by a method wherein a process to insertedly provide silicon oxide films between electrode and wiring layers and plasma silicon nitride films is supplemented. CONSTITUTION:After an interlayer insulating film 2 consisting of PSG is formed as to cover a circuit element on a silicon substrate 1, an under layer Al wiring 3, a silicon oxide film 10 and a plasma silicon nitride film 4 are adhered thereon. A photo resist 5 is rotatingly applied on the silicon nitride film 4 in succession, and after a solvent in the photo resist 5 is removed by applying heat treatment, the photo resist 5 is removed completely under the condition as to make the etching speeds of the silicon nitride film 4 and the photo resist 5 to be nearly the same. At this time, the silicon nitride film is left on the under layer Al wiring 3. After then, a silicon oxide film 6 is adhered on the silicon nitride film 4. Then a through hole 11 is opened, a top layer Al wiring 7 is formed as a passivation film, and a silicon oxide film 8 and a plasma silicon nitride film 9 are formed on the top layer Al wiring 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a glabella insulating film in a multilayer wiring.

(Conventional technology) In recent years, in order to increase the integration and speed of LSI devices.

The number of devices equipped with multilayer wiring structures is increasing. An alloy containing AL as a main component is generally used as a wiring material. On the other hand, as wiring becomes more multilayered, steeper steps occur,
Since it is difficult to form an upper layer wiring thereon, a step of planarizing the interlayer insulating film between the lower layer wiring and the upper layer wiring is required.

As an example of a conventional method for planarizing an interlayer insulating film, a manufacturing process of an MO3 type semiconductor device employing a photoresist etch pack will be described with reference to FIGS. 2(a) to 2Q. In addition, Figure 2 shows the manufacturing process of A/, two-layer wiring,
For clarity, transistor regions are not shown.

In FIG. 2, first, the circuit elements (
After forming a glabellar insulating film made of PSG 2 so as to cover (not shown in the figure), a lower layer U wiring 3 having a film thickness of, for example, 0.8 μm is formed [FIG. 2(a)]. Thereafter, a silicon nitride film (hereinafter referred to as plasma silicon nitride film) 4 having a thickness of 15 μm, for example, produced by plasma CVD is deposited [FIG. 2(b)]. Furthermore, a photoresist 5 is spin-coated on this silicon nitride film 4 [FIG. 2(C)]
. This was heat-treated at about 200° C. to remove the solvent in the photoresist 5, and then under conditions such that the etching rate of the silicon nitride film 4 and the photoresist 5 were almost the same.
The photoresist 5 is completely removed by etching. At this time, a part of the silicon nitride film 4 is also etched at the same time, leaving the silicon nitride film 4 with a thickness of 0.3 to 1.2 μm on the lower layer At wiring 3 [FIG. 2(d)].

Next, silicon nitride film 4 is coated with a film having a thickness of 0.6 μm, for example.

A silicon oxide film 6 is deposited [FIG. 2(e)]. Thereafter, the through hole 11 is opened and the upper layer At wiring 7 is formed [FIG. 2(f)]. Finally, Yatsushi Peshi.

As shown in FIG. 2(g), a silicon oxide film 8 and a plasma silicon nitride film 9, each having a thickness of 0.5 μm, are successively formed on the upper layer kt wiring 7 as a conductive film (FIG. 2(g)).

(Problems to be Solved by the Invention) However, in this case, the lower layer At wiring 3 is in contact with the plasma silicon nitride film 4 which has a large compressive stress, so its shape is constantly changed due to tensile force, leading to disconnection. In particular, in the case of fine wiring with a wiring width of 2 μm or less, disconnection often occurs.This phenomenon occurs during the heat treatment process after depositing the plasma silicon nitride film, and
Similar problems occur when semiconductor devices are used at high temperatures for long periods of time.

On the other hand, if after forming the lower layer At wiring, a silicon oxide film is deposited, a silicon nitride film is further deposited on top of this, and then photoresist etch pack planarization is performed, the upper layer A
When the t-wiring and the silicon nitride film come into contact with each other, it becomes busy, and a similar problem occurs with the upper layer At wiring.

In addition, if the interlayer insulating film between the lower layer At wiring and the upper layer At wiring is formed only with a silicon oxide film, there is no plasma silicon nitride film that is strong and has excellent crack resistance. A problem arises in that electrical leakage is likely to occur between the wiring lines.

(Means for Solving the Problems) In order to solve the above problems, the present invention first deposits a first silicon oxide film on a first electrode/wiring layer provided on a silicon substrate. Next, after a silicon nitride film is deposited, an organic resin is spin-coated thereon, and after drying, all of the organic resin and a portion of the silicon nitride film are etched at approximately the same rate. Next, a second silicon oxide film is deposited on the remaining silicon nitride film, and a second electrode/wiring layer is formed thereon.

(Function) According to the above steps, the lower electrode/wiring layer and the upper electrode/wiring layer
Neither the wiring layer comes into contact with the plasma silicon nitride film which has compressive stress, and the problem of disconnection can be prevented. Furthermore, since a plasma silicon nitride film is used as a part of the glabellar insulating film, electrical leakage between the lower electrode/wiring layer and the upper electrode/wiring layer can be prevented.

(Example) An example of the present invention will be described below with reference to FIG. Note that, for the sake of simplicity, only the kA two-layer wiring portion is shown in the figure, and the transistor region is not shown.

In FIG. 1, first, circuit elements (
After forming a glabellar insulating film made of KPSG 2 so as to cover (not shown in the figure), a lower layer U wiring 3 having a film thickness of 0.8 μm, for example, is formed [FIG. 1(a)].

Thereafter, a silicon oxide film 10 having a thickness of, for example, 0.3 μm is deposited by atmospheric pressure CVD, and then a silicon oxide film 10 having a thickness of, for example, 1.5 μm is deposited.
A plasma silicon nitride film 4 of m is deposited [FIG. 1(b)]
]. Subsequently, a photoresist (or polyimide resin) 5 is spin-coated on this silicon nitride film 4 [see FIG.
)]. Next, the solvent in the photoresist 5 is removed by heat treatment at about 200° C., and then the photoresist 5 is completely etched away under conditions such that the etching rates of the silicon nitride film 4 and the photoresist 5 are almost the same. . At this time, a part of the silicon nitride film 4 is also etched at the same time, leaving a silicon nitride film with a thickness of 0.3 to 1.2 μm on the lower layer At wiring 3 [FIG. 1(d)]. Thereafter, a silicon oxide film 6 having a thickness of, for example, 0.3 μm is deposited on the silicon nitride film 4 [FIG. 1(e)]. Next, the through hole 11 is opened and the upper layer At wiring 7 is formed [FIG. 1 (f
)]. Finally, a silicon oxide film 8 and a plasma silicon nitride film 9 each having a thickness of 0 and 5 μm, for example, are formed on the upper layer At wiring 7 as a pad page film [FIG. 1(g)]. . Note that silicon oxide films 6, 8, 10
may be made of glass containing impurities such as P e B g As.

In the multilayer wiring structure according to the above embodiment, both the lower and upper layer At wirings 3 and 7 are not in planar contact with the plasma silicon nitride film 4 having compressive stress, and
This can prevent the problem of wires being pulled and breaking. Further, since the intermediate layer of the glabellar insulating film is a plasma silicon nitride film that is strong and has excellent crack resistance, electrical leakage between the lower layer At wiring and the upper layer At wiring can be prevented.

In addition, in the example, explanation was made using At two-layer wiring, but
It is clear that the present invention has similar effects on At multilayer interconnections of three or more layers, and
Similar effects can be expected even when metal wiring other than the above is used.

(Effects of the Invention) As explained above, according to the present invention, cracks can be prevented by adding a step of inserting a silicon oxide film between the electrode/wiring layer and the plasma silicon nitride film, which were conventionally liquid-filled. It is possible to prevent the occurrence of wire breakage and disconnection of wiring, and it is possible to improve the reliability of the semiconductor device.

[Brief explanation of the drawing]

Figures 1(a) to ω are cross-sectional views showing a series of manufacturing steps in an embodiment of the present invention, and Figures 2(&) to (X) are sectional views showing a series of manufacturing steps in a conventional example. be. 1... Silicon substrate, 2, 6, 8, 10... Silicon oxide film (or psc), 3... Lower layer At wiring,
4゜9...Plasma silicon nitride film, 5...Photorenost, 7...Upper layer At wiring. Figure 1 1. Silicon 1 (4, 9...) Figure 1 Figure 2

Claims (3)

[Claims] (1) a step of depositing a first silicon oxide film on a first electrode/wiring layer provided on a silicon substrate; a step of depositing a silicon nitride film on the first silicon oxide film; a step of spin-coating an organic resin on the silicon nitride film; a step of etching all of the organic resin and a part of the silicon nitride film at approximately the same rate; and a step of etching a second organic resin on the remaining silicon nitride film. A method for manufacturing a semiconductor device, comprising the steps of depositing a silicon oxide film and forming a second electrode/wiring layer on the second silicon oxide film. (2) Claim (1) characterized in that the first and second silicon oxide films are made of glass containing impurities such as phosphorus (P), boron (B), and arsenic (As). A method of manufacturing the semiconductor device described above. (3) The method for manufacturing a semiconductor device according to claim (1), wherein the organic resin is made of photoresist or polyimide.