JPS59117133A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59117133A JPS59117133A JP22616582A JP22616582A JPS59117133A JP S59117133 A JPS59117133 A JP S59117133A JP 22616582 A JP22616582 A JP 22616582A JP 22616582 A JP22616582 A JP 22616582A JP S59117133 A JPS59117133 A JP S59117133A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- silicon nitride
- semiconductor device
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は絶縁ケート電界効果トランジスタ（ＭＩＳＦＥ
Ｔ）におけるホットキャリアによる特性劣化の防止を図
った半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (MISFE).
The present invention relates to a semiconductor device in which deterioration of characteristics due to hot carriers in T) is prevented.
従来技術について第１図を用いて説明をする。The prior art will be explained using FIG. 1.
一般にＭＩＳＦＥＴを飽和領域で動作させると、ドレイ
ン領域２２近傍の空乏層内に多数のホットキャリアが発
生し、このキャリア（エレクトロン）が例えば５ｉＱ７
からなるゲート絶縁膜８中に注入されしきい値電圧”ｔ
ｈをシフト（変動）させＭ ｌ５ＦＥＴの特性劣化を生
じることが知られている。Generally, when a MISFET is operated in the saturation region, a large number of hot carriers are generated in the depletion layer near the drain region 22, and these carriers (electrons) are, for example, 5iQ7
The threshold voltage "t" is injected into the gate insulating film 8 consisting of
It is known that h is shifted (varied) and the characteristics of the M15FET are deteriorated.
これは、ゲート絶縁膜８中に存在している水素Ｈがゲー
ト絶縁膜８中に注入されたキャリアにより活性化され、
活性化されたＨが８ｉ−Ｑの結合を切ることによりタン
クリングボンドを形成し、しきい値電圧Ｖｔｈに影響な
与えるものと考えられている。This is because hydrogen H existing in the gate insulating film 8 is activated by carriers injected into the gate insulating film 8.
It is believed that the activated H forms a tank ring bond by cutting the 8i-Q bond and has no effect on the threshold voltage Vth.
一方、牛導体基板１を薇５最上層の絶縁膜すなワチファ
イナルパシベーション膜７として、プラズマ気相化学反
応法（プラズマＣｖｌ）法）で形成された窒化シリコン
膜（以下、Ｐ−８ｉＮ膜という）を用いるときがある。On the other hand, the conductive substrate 1 is used as the final passivation film 7, which is the uppermost insulating film of the conductive substrate 5, and is a silicon nitride film (hereinafter referred to as P-8iN film) formed by plasma vapor phase chemical reaction method (plasma Cvl method). ) is sometimes used.
これは、Ｐ −８ｉＮ膜が機械的強度および耐湿性に優
れているためである。This is because the P-8iN film has excellent mechanical strength and moisture resistance.
ところが、Ｐ−８ｉＮ膜７中には多猷の水素が台まれて
おり、この水素がリンシリケートガラス膜（Ｐ２Ｏ膜）
６，４およびポリシリコンゲート９を通って拡散し、ゲ
ート絶縁膜８に＋Ｕ達することがわかった。However, there is a lot of hydrogen in the P-8iN film 7, and this hydrogen is absorbed into the phosphosilicate glass film (P2O film).
6, 4 and the polysilicon gate 9, and reached the gate insulating film 8 at +U.
本発明は、Ｐ −ＳｉＮ膜７に存在する水素が、ゲート
絶縁膜まで到達するのを防ぐことな目的としている。The purpose of the present invention is to prevent hydrogen present in the P-SiN film 7 from reaching the gate insulating film.
以下本発明の実施例について第２図を用いて説明する。Examples of the present invention will be described below with reference to FIG.
なお、第１図と同一の部分は同一符号で示しである。Note that the same parts as in FIG. 1 are indicated by the same reference numerals.
本実施例によれば、ゲート電極９としてのポリシリコン
層とアルミニウム配線５の間の絶縁膜として、気相化学
反応法（ＣＶＤ法）により形成される窒化シリコン膜１
４を絶縁膜の一部として使用する。この窒化シリコン膜
１４は、電気的に不安定なことから、ケート電極９とア
ルミニウム配線５との短絡を防ぐため、電気的安定なＰ
ＳＧ膜１３．１５ではさみ込む。According to this embodiment, a silicon nitride film 1 formed by a vapor phase chemical reaction method (CVD method) is used as an insulating film between a polysilicon layer as a gate electrode 9 and an aluminum wiring 5.
4 is used as part of the insulating film. Since this silicon nitride film 14 is electrically unstable, in order to prevent a short circuit between the gate electrode 9 and the aluminum wiring 5, an electrically stable P film is used.
It is sandwiched between SG films 13 and 15.
ＣＶＩ）法により形成された窒化シリコン膜】４は、緻
密であり、水素は（５００Ｃ以下で窒化シリコン膵１４
中を拡散することができない。即ち、ファイナルパシベ
ーション膜７としてＰ−８ｉＮ膜を使用したとしても、
この膜中の水素は窒化シリコン膜１４により拡散が阻止
され、ゲート絶縁膜８に到達することができない。ファ
イナルパシベーション膜形成後は６００Ｃを越えろ加熱
上程はなく、したがってＭＯＳＦＥＴのしきい値電圧■
ｔｈは変動せず、回路の不良動作カーなくなることとな
る。The silicon nitride film formed by the CVI) method is dense, and hydrogen is
cannot be diffused inside. That is, even if a P-8iN film is used as the final passivation film 7,
Hydrogen in this film is prevented from diffusing by the silicon nitride film 14 and cannot reach the gate insulating film 8. After the final passivation film is formed, there is no heating process beyond 600C, so the threshold voltage of the MOSFET is
th does not change, and there are no circuit malfunctions.
本発明によれば、機械的強度および耐湿性に優しタＰ
−Ｓ ｉ Ｎ 膜ラフアイナルパシベーション膜トして
用いることによって半導体装置の（言頼性を向上できる
と同時に、ホットキャリアによるｉ＼４ＩＳＰＥＴのし
きい値電圧の変動を防止することができろ。According to the present invention, the material has good mechanical strength and moisture resistance.
-By using the S i N film as a rough passivation film, it is possible to improve the reliability of a semiconductor device and at the same time prevent fluctuations in the threshold voltage of the i\4ISPET due to hot carriers.
本発明は上記実施例に限定さイｔないっ例えばＰＳけ膜
１３．１５に変えて電気的に安定な５ｉＱ２膜を用いる
等種々の変形が可能である。The present invention is not limited to the above-mentioned embodiments; for example, various modifications can be made, such as using an electrically stable 5iQ2 film instead of the PS film 13.15.
第１図は、従来の半導体装置を示す断面図、第２図は、
本発明の半導体装れを示す断面図を表わす。
１・・・Ｐ型シリコン半導体基板、２１・・−Ｎ＋型ソ
ース領域、２２パ・Ｎ 型ドレイン領域、３・・・フィ
ールド（？；？化膜、４・・・ＰＳＵ膜、５・・・アル
ミニウム「１己に９１．６・・・ＰＳＵ１毒、７・・・
Ｐ−８ｉＮ膜、８・・・ゲート絶縁膜、９・・・ポリシ
リコンゲート、１３・・・ＰＳＵＩＩ□’％、１４・・
・窒化シリコン膜、１５・・・ＰＳＧ膜。FIG. 1 is a sectional view showing a conventional semiconductor device, and FIG. 2 is a cross-sectional view showing a conventional semiconductor device.
1 is a cross-sectional view showing a semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon semiconductor substrate, 21... -N+ type source region, 22 P-N type drain region, 3... Field (?;? chemical film, 4... PSU film, 5... Aluminum “91.6 for 1 person…PSU1 poison, 7…
P-8iN film, 8... Gate insulating film, 9... Polysilicon gate, 13... PSUII□'%, 14...
- Silicon nitride film, 15...PSG film.
Claims (1)
ランジスタと、これを薇５よ５に前記基板上に形成され
た絶縁膜と、前記基板を覆うファイナルパシベーション
膜であるプラズマ気相化学反応法によって形成された窒
化シリコン膜とを有する半導体装置において、前記絶縁
膜は気相化学反応法によって形成された窒化シリコン膜
を電気的に安定な絶縁膜で挾んでなる３層構造の絶縁膜
であることをｔ時機とする半導体装置っ1. An insulated gate field effect transistor formed on a conductor split plate, an insulating film formed on the substrate, and a final passivation film covering the substrate using plasma vapor phase chemistry. In a semiconductor device having a silicon nitride film formed by a reaction method, the insulating film has a three-layer structure in which a silicon nitride film formed by a vapor phase chemical reaction method is sandwiched between electrically stable insulating films. Semiconductor devices that take advantage of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22616582A JPS59117133A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22616582A JPS59117133A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59117133A true JPS59117133A (en) | 1984-07-06 |
Family
ID=16840881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22616582A Pending JPS59117133A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117133A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61226930A (en) * | 1985-03-30 | 1986-10-08 | Sony Corp | Semiconductor device |
| JPS61287151A (en) * | 1985-06-14 | 1986-12-17 | Matsushita Electronics Corp | Semiconductor device |
| JPS61289649A (en) * | 1985-06-17 | 1986-12-19 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS62264662A (en) * | 1986-04-17 | 1987-11-17 | Mitsubishi Electric Corp | Semiconductor device |
| JPH09139383A (en) * | 1995-10-30 | 1997-05-27 | Sony Corp | Semiconductor device |
-
1982
- 1982-12-24 JP JP22616582A patent/JPS59117133A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61226930A (en) * | 1985-03-30 | 1986-10-08 | Sony Corp | Semiconductor device |
| JPS61287151A (en) * | 1985-06-14 | 1986-12-17 | Matsushita Electronics Corp | Semiconductor device |
| JPS61289649A (en) * | 1985-06-17 | 1986-12-19 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS62264662A (en) * | 1986-04-17 | 1987-11-17 | Mitsubishi Electric Corp | Semiconductor device |
| JPH09139383A (en) * | 1995-10-30 | 1997-05-27 | Sony Corp | Semiconductor device |
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