CA1123122A - High voltage dielectrically isolated dual gate solid-state switch - Google Patents
High voltage dielectrically isolated dual gate solid-state switchInfo
- Publication number
- CA1123122A CA1123122A CA340,787A CA340787A CA1123122A CA 1123122 A CA1123122 A CA 1123122A CA 340787 A CA340787 A CA 340787A CA 1123122 A CA1123122 A CA 1123122A
- Authority
- CA
- Canada
- Prior art keywords
- region
- layer
- localized
- semiconductor body
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000009977 dual effect Effects 0.000 title description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 101000595669 Homo sapiens Pituitary homeobox 2 Proteins 0.000 description 1
- 102100036090 Pituitary homeobox 2 Human genes 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 201000008633 iridogoniodysgenesis syndrome Diseases 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- ZFXYFBGIUFBOJW-UHFFFAOYSA-N theophylline Chemical compound O=C1N(C)C(=O)N(C)C2=C1NC=N2 ZFXYFBGIUFBOJW-UHFFFAOYSA-N 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
- H01L29/7392—Gated diode structures with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
Abstract
Abstract of the Disclosure The present invention relates to a structure comprising a semiconductor body whose bulk is of one conductivity type and which has a major surface, a localized first region which is of the one conductivity type, and a localized second region and a localized third region which are both of the opposite conductivity type.
Each of the localized first, second and third regions are of relatively low resistivity as compared to the bulk portion of the semiconductor body and are spaced apart from the others. Separate electrodes are connected to each of the first, second and third regions The localized first, second and third regions each have a portion thereof which forms a part of the major surface.
The semiconductor body is separated from a semiconductor wafer (substrate) by a dielectric layer. The semiconductor wafer (substrate) is adapted to facilitate connection to an electrode and is characterized by a localized fourth layer of the same conductivity type as the third region.
The fourth layer is sandwiched between the dielectric layer and the semiconductor body.
Each of the localized first, second and third regions are of relatively low resistivity as compared to the bulk portion of the semiconductor body and are spaced apart from the others. Separate electrodes are connected to each of the first, second and third regions The localized first, second and third regions each have a portion thereof which forms a part of the major surface.
The semiconductor body is separated from a semiconductor wafer (substrate) by a dielectric layer. The semiconductor wafer (substrate) is adapted to facilitate connection to an electrode and is characterized by a localized fourth layer of the same conductivity type as the third region.
The fourth layer is sandwiched between the dielectric layer and the semiconductor body.
Description
Hartman-14 1.
IIIGll VOLTAGE DIELECTRICALLY
ISOLATED DUAL GATE SOLID-STATE SWITCH
Technical Field This invention relatesto solid-state structures and, in particular, to higl1 voltage solid-state structures useful in telephone switching systems and 5 many other applications.
Background of the Invention In an article entitled "A Field Terminated Diode"
by Douglas B. Houston et al, published in IEEE
Transactions on Electronc Devices, Vol. ED-23, No. 8, lO August 1976, there is described a discrete solid-state high voltage switch that has a vertical goemetry and which includes a region which can be pinched off to provide an "OFF" state or which can be made highly conductive with dual carrier injection to provide an 15 "ON" state. One problem with this switch is that it is not easily manufacturable with other like switching devices on a common substrate. Another problem is that the spacing between the grids and the cathode should be small to limit the magnitude of the control ~O grid voltage; however, this limits the useful voltage range because it decreases grid-to-cathode breakdown voltage. This limitation effectively limits the use of two of the devices with the cathode of each coupled to the anode of the other to relatively low voltages.
~5 Sucn a dual device sLructure would be useful as a high voltage bidirectional solid-state switch. An additional problem is that the base region should ideally be highly doped to avoid punch-through from the anode to the grid; however, this leads to a low 30 voltage breakdown between anode and cathode. ~idening of the base region limits the punch-through effect;
however, it also increases the resistance of the device in the "ON" state.
It is desirable to have a ~lid-state structure 35 which is easily integratable such that two or more structures can be simultaneously fabricated on a common substrate and wherein each switch is capable of 3~
bilateral blocking of relatively high voltages. One such structure is described in Canadian application Serial No.
342,165 filed in the names of A. R. Hartman, T. J. Riley and P. W. Shackle, Case 6-5-~ on December 18, 1979, having a common assignee. This present application relates to a subsequent improvement over such structure.
Summary of the Invention The present invention relates to a structure comprising a semiconductor body whose bulk is of one conductivity type and which has a major surface and within the semiconductor body is a localized first region which is of the one conductivity type, and localized second and third regions which are both of the opposite conductivity type. The first, second, and third regions are spaced apart from each other, have separate electrode connections thereto, and are of relatively low resistivity as compared to the bulk of the semiconductor body. Each of the three regions has a portion which forms part of the major surface of the semiconductor body. The structure is so adapted that during operation there is dual carrier injection. The semiconductor body is separated from a semiconductor support tsubstrate) by a dielectric layer.
The support is adapted to facilitate an electrode being coupled thereto. The invention is characterized in that there is sandwiched between the dielectric layer and the semiconductor body a semiconductor layer of the opposite conductivity type of the semiconductor body.
In a preferred embodiment the first, second, and third regions serve as the anode, gate, and cathode, respectively, of the structure.
The structure of the present invention, when suitably designed, can be operated as a switch that is characterized by a low impedance path between anode and cathode when in an ON (conducting) state and by a high impedance path between said regions when in the OFF
Hart an-14
IIIGll VOLTAGE DIELECTRICALLY
ISOLATED DUAL GATE SOLID-STATE SWITCH
Technical Field This invention relatesto solid-state structures and, in particular, to higl1 voltage solid-state structures useful in telephone switching systems and 5 many other applications.
Background of the Invention In an article entitled "A Field Terminated Diode"
by Douglas B. Houston et al, published in IEEE
Transactions on Electronc Devices, Vol. ED-23, No. 8, lO August 1976, there is described a discrete solid-state high voltage switch that has a vertical goemetry and which includes a region which can be pinched off to provide an "OFF" state or which can be made highly conductive with dual carrier injection to provide an 15 "ON" state. One problem with this switch is that it is not easily manufacturable with other like switching devices on a common substrate. Another problem is that the spacing between the grids and the cathode should be small to limit the magnitude of the control ~O grid voltage; however, this limits the useful voltage range because it decreases grid-to-cathode breakdown voltage. This limitation effectively limits the use of two of the devices with the cathode of each coupled to the anode of the other to relatively low voltages.
~5 Sucn a dual device sLructure would be useful as a high voltage bidirectional solid-state switch. An additional problem is that the base region should ideally be highly doped to avoid punch-through from the anode to the grid; however, this leads to a low 30 voltage breakdown between anode and cathode. ~idening of the base region limits the punch-through effect;
however, it also increases the resistance of the device in the "ON" state.
It is desirable to have a ~lid-state structure 35 which is easily integratable such that two or more structures can be simultaneously fabricated on a common substrate and wherein each switch is capable of 3~
bilateral blocking of relatively high voltages. One such structure is described in Canadian application Serial No.
342,165 filed in the names of A. R. Hartman, T. J. Riley and P. W. Shackle, Case 6-5-~ on December 18, 1979, having a common assignee. This present application relates to a subsequent improvement over such structure.
Summary of the Invention The present invention relates to a structure comprising a semiconductor body whose bulk is of one conductivity type and which has a major surface and within the semiconductor body is a localized first region which is of the one conductivity type, and localized second and third regions which are both of the opposite conductivity type. The first, second, and third regions are spaced apart from each other, have separate electrode connections thereto, and are of relatively low resistivity as compared to the bulk of the semiconductor body. Each of the three regions has a portion which forms part of the major surface of the semiconductor body. The structure is so adapted that during operation there is dual carrier injection. The semiconductor body is separated from a semiconductor support tsubstrate) by a dielectric layer.
The support is adapted to facilitate an electrode being coupled thereto. The invention is characterized in that there is sandwiched between the dielectric layer and the semiconductor body a semiconductor layer of the opposite conductivity type of the semiconductor body.
In a preferred embodiment the first, second, and third regions serve as the anode, gate, and cathode, respectively, of the structure.
The structure of the present invention, when suitably designed, can be operated as a switch that is characterized by a low impedance path between anode and cathode when in an ON (conducting) state and by a high impedance path between said regions when in the OFF
Hart an-14
2;~:
3.
(blocking) state. The potential applied to the gate region relative to the anode and cathode regions determines the state of the structure. During the ON
state there is dual carrier injection which results in 5 the resistance between anode ancl cathode regions to be relatively low.
This structure, which is to be denoted as a gated diode switch IGDS)~ when suitably designed, is capable of blocking relatively large potential 10 differences between anode and cathode in the OFF
state, independent of polarity, and is capable of conducting relatively large amounts of current with a relatively low voltage drop between the anode and cathode in the ON state. The semiconductor layer 15 sandwiched between the dielectric layer and the first region acts to isolate the first region from the properties of the dielectric layer.
Arrays of these bodies can be fabricated on a single or common silicon substrate together with 20 other high voltage circuit components. The bi-lateral blocking characteristic of the present structure facilitates its use as a bidirectional switch comprising two of the bodies with the anode of each coupled to the cathode of the other and the 25 gates being coupled together.
These and other novel features of the present invention are better understood from consideration of the following detailed description taken in conjunction with the accompanying drawings.
30 Brief Description of the Drawing FIG. 1 illustrates a structure in accordance with one embodiment of the invention; and FIG. 2 illustrates a proposed electrical symbol for the structure of FIG. 1.
35 Detailed Description Referring now to FIG. 1~ there is illustrated a structure 10 comprising a support member 12 having a Hart~an-14
(blocking) state. The potential applied to the gate region relative to the anode and cathode regions determines the state of the structure. During the ON
state there is dual carrier injection which results in 5 the resistance between anode ancl cathode regions to be relatively low.
This structure, which is to be denoted as a gated diode switch IGDS)~ when suitably designed, is capable of blocking relatively large potential 10 differences between anode and cathode in the OFF
state, independent of polarity, and is capable of conducting relatively large amounts of current with a relatively low voltage drop between the anode and cathode in the ON state. The semiconductor layer 15 sandwiched between the dielectric layer and the first region acts to isolate the first region from the properties of the dielectric layer.
Arrays of these bodies can be fabricated on a single or common silicon substrate together with 20 other high voltage circuit components. The bi-lateral blocking characteristic of the present structure facilitates its use as a bidirectional switch comprising two of the bodies with the anode of each coupled to the cathode of the other and the 25 gates being coupled together.
These and other novel features of the present invention are better understood from consideration of the following detailed description taken in conjunction with the accompanying drawings.
30 Brief Description of the Drawing FIG. 1 illustrates a structure in accordance with one embodiment of the invention; and FIG. 2 illustrates a proposed electrical symbol for the structure of FIG. 1.
35 Detailed Description Referring now to FIG. 1~ there is illustrated a structure 10 comprising a support member 12 having a Hart~an-14
4.
major surface 11 and a monocrystalline semiconductor body 16 whose bulk is of one conductivity type and which is separated from support member 12 by a dielectric layer 14. The monocrystalline semi-
major surface 11 and a monocrystalline semiconductor body 16 whose bulk is of one conductivity type and which is separated from support member 12 by a dielectric layer 14. The monocrystalline semi-
5 conductor body has a portion that is common with surface11. Sandwiched between body 16 and dielectric layer 14 is a semiconductor region (layer) 38. Alternately, a portion of layer 38, illustrated by dashed lines and denoted as layer 38a, can be used instead of the lO entire layer 38.
A localized first anode region 18, which is of the one type conductivity, is included in body 16 and has a portion thereof that extends to surface 11.
A localized second gate region 20, which is of the 15 opposite conductivity type, also is included in body 16 and has a portion thereof which extends to surface 11.
A localized third cathode region 24, which is of the opposite type conductivity of body 16, also is included in body 16 and has a portion which extends 20 to surface 11. A region 22, which is of one type conductivity and has a portion which extends to surface 11, encircles region 24 and acts as a depletion layer punch-through shield and to inhibit inversion of the portions of body 16 close thereto. Gate region 20 25 exists between anode region 18 and region 22 and is separated from both by bulk portionsof body 16. The resistivities of regions 18, 20 and 24 are low compared to that of the bulk portions of body 16. The resistivity of region 22 is intermediate between that 30 of region 24 and that of the bulk portions of body 16.
Electrodes 28, 30 and 32 are conductors which make low resistance contact to the surface portions of regions 18, 20, and 24, respectively. A dielectric layer 26 covers major surface 11 so as to isolate 35 electrodes 28, 30, and 32 from all regions other than those intended to be electrically contacted. Electrode .
Hartman-14 5, 30 makes electrical contact to region 38 (38a) at surface ll in the rear or front ~not illustrated) of body 16.
Layer 38a can be modified such that it exists 5 only on the lower portion of body 16. With such modification an appropriate diffused or ion implanted region~s) ~not illustrated) is formed between surface 11 and modified layer 38a. Electrode 30 would extend to make electrical contact to this region at lO sur~ace 11.
Advantageously, the support member 12 can be of silicon either of n or ~ type conductivity. If it is of n-type conductivity then a region 34 of n+ type conductivity is formed in substrate 12. An electrode 15 36 makes low resistance contact to region 34. Each of electrodes 28, 30 and 32 advantageously overlaps the semiconductor region to which they make low resistance contact. Electrode 32 also overlaps region 22. This overlapping, which is known as field plating~
20 facilitates high voltage operation because it increases the voltage at which breakdown occurs.
In one illustrative embodiment, substrate 12, body 16, and regions 18, 20, 22, 24, and 34 are of n-, p-, p+, n+, ~, n+ and n~ type conductivity, respectively.
25 Dielectric layer 14 is silicon dioxide and electrodes 28, 30, 32, and 36 are all aluminum.
A plurality of separate bodies 16 can be formed in common support member 12 to provide a plurality of switches.
Structure 10 is typically operated as a switch which is characterized by a low impedance path between anode region 18 and cathode region 24 when in the ON
~conduction) state and as a high impedance between said two regions when in the OFF ~blocking) state. The 35 potential applied to gate region 20 determines the state of the switch. Conduction between anode region 18 and .
.: , ;
~. . . .
.... .
:: ' , :: - ' ' :
Hartman-l~
A localized first anode region 18, which is of the one type conductivity, is included in body 16 and has a portion thereof that extends to surface 11.
A localized second gate region 20, which is of the 15 opposite conductivity type, also is included in body 16 and has a portion thereof which extends to surface 11.
A localized third cathode region 24, which is of the opposite type conductivity of body 16, also is included in body 16 and has a portion which extends 20 to surface 11. A region 22, which is of one type conductivity and has a portion which extends to surface 11, encircles region 24 and acts as a depletion layer punch-through shield and to inhibit inversion of the portions of body 16 close thereto. Gate region 20 25 exists between anode region 18 and region 22 and is separated from both by bulk portionsof body 16. The resistivities of regions 18, 20 and 24 are low compared to that of the bulk portions of body 16. The resistivity of region 22 is intermediate between that 30 of region 24 and that of the bulk portions of body 16.
Electrodes 28, 30 and 32 are conductors which make low resistance contact to the surface portions of regions 18, 20, and 24, respectively. A dielectric layer 26 covers major surface 11 so as to isolate 35 electrodes 28, 30, and 32 from all regions other than those intended to be electrically contacted. Electrode .
Hartman-14 5, 30 makes electrical contact to region 38 (38a) at surface ll in the rear or front ~not illustrated) of body 16.
Layer 38a can be modified such that it exists 5 only on the lower portion of body 16. With such modification an appropriate diffused or ion implanted region~s) ~not illustrated) is formed between surface 11 and modified layer 38a. Electrode 30 would extend to make electrical contact to this region at lO sur~ace 11.
Advantageously, the support member 12 can be of silicon either of n or ~ type conductivity. If it is of n-type conductivity then a region 34 of n+ type conductivity is formed in substrate 12. An electrode 15 36 makes low resistance contact to region 34. Each of electrodes 28, 30 and 32 advantageously overlaps the semiconductor region to which they make low resistance contact. Electrode 32 also overlaps region 22. This overlapping, which is known as field plating~
20 facilitates high voltage operation because it increases the voltage at which breakdown occurs.
In one illustrative embodiment, substrate 12, body 16, and regions 18, 20, 22, 24, and 34 are of n-, p-, p+, n+, ~, n+ and n~ type conductivity, respectively.
25 Dielectric layer 14 is silicon dioxide and electrodes 28, 30, 32, and 36 are all aluminum.
A plurality of separate bodies 16 can be formed in common support member 12 to provide a plurality of switches.
Structure 10 is typically operated as a switch which is characterized by a low impedance path between anode region 18 and cathode region 24 when in the ON
~conduction) state and as a high impedance between said two regions when in the OFF ~blocking) state. The 35 potential applied to gate region 20 determines the state of the switch. Conduction between anode region 18 and .
.: , ;
~. . . .
.... .
:: ' , :: - ' ' :
Hartman-l~
6.
cathode region 24 occurs if the potential of gate region 20 is below that of the potential of anode region 18 and cathode region 24. During the ON state holes are injected into body 16 from anode region 18 and 5 electrons are injected into body 16 from cathode region 24. These holes and electrons can be in sufficient numbers to form a p:lasma which conductivity modulates body 16. This effectively lowers the resistance of body 16 such that the resistance between 10 anode region 18 and cathode region 24 is relatively low when structure 10 is operating in the ON state.
This type of operation is denoted as dual carrier injection. The type of structure described herein is denoted as a gated diode switch (GDS).
Region 22 helps limit the punch-through of a depletion layer formed during operation between gate region 20 and cathode region 24 and helps inhibit - formation of a surface inversion layer between these two regions. In addition, it facilitates gate region 20 20 and cathode region 24 being relatively closely spaced apart. This facilitates relatively ~ow resistance between anode region 18 and cathode region 24 during the ON state.
Substrate 12 is held at the most positive 25 potential level available. Conduction between anode region 18 and cathode region 24 is inhibited or cut off if the potential of gate region 20 is sufficiently more positive than that of anode region 18. The amount of excess positive potential needed to inhibit or 30 cut off conduction is a function of the geometry and impurity concentration (doping~ levels of structure 10. This positive gate potential causes the portion of body 16 between gate region 20 and layer 38, 38a to be depleted such that the potential 35 of this portion of body 16 is more positive than that of anode region 18 and cathode region 24. This positive , ~ :
, . - ... : .
potential barrier inhibits the conduction of holes Erom anode region 18 to cathode region 24. It essentially pinches off body 16 against dielectric layer 14 in the bulk portion thereof below gate reclion 20 and extending down to dielectric layer 14. It also serves to collect electrons emitted at cathode region 24 before they can reach anode region 18. Control circuitry capable of supplying the needed gate potentials and absorbing the electrons is illustrated and described in Canadian patent application Serial No. 342,083, in the names of A. R.
Hartman, T. J. Riley and P. W. Shackle, Case 9-7-7, on December 17, 1979.
During the ON state of structure 10, the junction diode comprising body 16 and region 20 becomes forward-biased. Current limiting means (not illustrated) are normally included to limit the conduction through the forward-biased diode. One example of such current limiting means is illustrated and described in above mentioned Canadian patent application Serial No. 342,083.
Layer 38 serves to isolate body 16 from the properties of dielectric layer 14 and is thus believed to aid the fabrication process in the tolerances in the formation of the dielectric layer 14 can be relaxed somewhat. This is believed to help increase fabrication yields and thus reduce costs. In addition layer 38 serves as a lower gate region which aids in reducing the magnitude of the gate potential needed to inhibit or cut off conduction between the anode (18) and cathode (24) regions. The use of only portion 38a of layer 38 serves to isolate body 16 from region 14 in the portion of body 16 which is under region 20. This particular portion of body 16 is the most critical portion since body 16 is essentially "pinched off" in this portion when structure 10 is operated in the OFF state.
Layer 38a does not provide complete isolation from dielectric layer 14 but is be]ieved to be the .~' 8.
preferred embodiment because it provides an improvement in the magnitude of the gate potential while essentially not effecting the breakdown voltage of the structure. Layer 38 provides complete isolation from dielectric layer 14 but does reduce the breakdown voltage of the structure somewhat. If layer 38 is used, then generally body 16 is increased in thickness in order to maintain breakdown voltages at preselected levels.
A structure which does not use a layer 38, 38a is described in the aforementioned Canadian patent application Serial No. 342,165.
It is believed that layer 38 need not necessarily be directly connected to electrode 30. Because positive charge resides in layer 26, a surface inversion layer will 15 form near the surface 11 of body 16 between layer 38 and gate region 20 which will electrically couple the two.
Even without said positive charge it is believed that due to punch-through electrode 30 and layer 38 would be electrically coupled.
A proposed electrical symbol for this type of switch is illustrated in FIG. 2. The anode, gate, and cathode electrodes are denoted as terminals 28, 30 and 32, respectively.
The embodiments described herein are intended to be illustrative of the general principles of the invention.
Various modifications are possible consistent with the spirit of the invention. For example, for the designs described, support regions 12 can be p-type conductivity silicon, gallium arsenide, sapphire, or an electrically inactive material. Further, the electrodes can be doped polysilicon, gold titanium, or other types of conductors.
Still further, the concentration levels, spacings between different regions, and other dimensions of the regions can be adjusted to allow significantly higher operating voltages and currents than are described. Additionally, . <
9.
other types of dielectric materials, such as silicon nitride, can be substituted for silicon dioxide. Still further the conductivity type of all regions can be reversed provided the voltage polarities are appropriately changed in the manner well known in the art. The structure can be utilized for alternating or direct current operation. Still further, the semiconductor region 22 which surrounds the cathode can be moditied to also include a guard ring region as is illustrated in Canadian patent application Serial No. 342,165.
'~ ' . ,, ' :
....
cathode region 24 occurs if the potential of gate region 20 is below that of the potential of anode region 18 and cathode region 24. During the ON state holes are injected into body 16 from anode region 18 and 5 electrons are injected into body 16 from cathode region 24. These holes and electrons can be in sufficient numbers to form a p:lasma which conductivity modulates body 16. This effectively lowers the resistance of body 16 such that the resistance between 10 anode region 18 and cathode region 24 is relatively low when structure 10 is operating in the ON state.
This type of operation is denoted as dual carrier injection. The type of structure described herein is denoted as a gated diode switch (GDS).
Region 22 helps limit the punch-through of a depletion layer formed during operation between gate region 20 and cathode region 24 and helps inhibit - formation of a surface inversion layer between these two regions. In addition, it facilitates gate region 20 20 and cathode region 24 being relatively closely spaced apart. This facilitates relatively ~ow resistance between anode region 18 and cathode region 24 during the ON state.
Substrate 12 is held at the most positive 25 potential level available. Conduction between anode region 18 and cathode region 24 is inhibited or cut off if the potential of gate region 20 is sufficiently more positive than that of anode region 18. The amount of excess positive potential needed to inhibit or 30 cut off conduction is a function of the geometry and impurity concentration (doping~ levels of structure 10. This positive gate potential causes the portion of body 16 between gate region 20 and layer 38, 38a to be depleted such that the potential 35 of this portion of body 16 is more positive than that of anode region 18 and cathode region 24. This positive , ~ :
, . - ... : .
potential barrier inhibits the conduction of holes Erom anode region 18 to cathode region 24. It essentially pinches off body 16 against dielectric layer 14 in the bulk portion thereof below gate reclion 20 and extending down to dielectric layer 14. It also serves to collect electrons emitted at cathode region 24 before they can reach anode region 18. Control circuitry capable of supplying the needed gate potentials and absorbing the electrons is illustrated and described in Canadian patent application Serial No. 342,083, in the names of A. R.
Hartman, T. J. Riley and P. W. Shackle, Case 9-7-7, on December 17, 1979.
During the ON state of structure 10, the junction diode comprising body 16 and region 20 becomes forward-biased. Current limiting means (not illustrated) are normally included to limit the conduction through the forward-biased diode. One example of such current limiting means is illustrated and described in above mentioned Canadian patent application Serial No. 342,083.
Layer 38 serves to isolate body 16 from the properties of dielectric layer 14 and is thus believed to aid the fabrication process in the tolerances in the formation of the dielectric layer 14 can be relaxed somewhat. This is believed to help increase fabrication yields and thus reduce costs. In addition layer 38 serves as a lower gate region which aids in reducing the magnitude of the gate potential needed to inhibit or cut off conduction between the anode (18) and cathode (24) regions. The use of only portion 38a of layer 38 serves to isolate body 16 from region 14 in the portion of body 16 which is under region 20. This particular portion of body 16 is the most critical portion since body 16 is essentially "pinched off" in this portion when structure 10 is operated in the OFF state.
Layer 38a does not provide complete isolation from dielectric layer 14 but is be]ieved to be the .~' 8.
preferred embodiment because it provides an improvement in the magnitude of the gate potential while essentially not effecting the breakdown voltage of the structure. Layer 38 provides complete isolation from dielectric layer 14 but does reduce the breakdown voltage of the structure somewhat. If layer 38 is used, then generally body 16 is increased in thickness in order to maintain breakdown voltages at preselected levels.
A structure which does not use a layer 38, 38a is described in the aforementioned Canadian patent application Serial No. 342,165.
It is believed that layer 38 need not necessarily be directly connected to electrode 30. Because positive charge resides in layer 26, a surface inversion layer will 15 form near the surface 11 of body 16 between layer 38 and gate region 20 which will electrically couple the two.
Even without said positive charge it is believed that due to punch-through electrode 30 and layer 38 would be electrically coupled.
A proposed electrical symbol for this type of switch is illustrated in FIG. 2. The anode, gate, and cathode electrodes are denoted as terminals 28, 30 and 32, respectively.
The embodiments described herein are intended to be illustrative of the general principles of the invention.
Various modifications are possible consistent with the spirit of the invention. For example, for the designs described, support regions 12 can be p-type conductivity silicon, gallium arsenide, sapphire, or an electrically inactive material. Further, the electrodes can be doped polysilicon, gold titanium, or other types of conductors.
Still further, the concentration levels, spacings between different regions, and other dimensions of the regions can be adjusted to allow significantly higher operating voltages and currents than are described. Additionally, . <
9.
other types of dielectric materials, such as silicon nitride, can be substituted for silicon dioxide. Still further the conductivity type of all regions can be reversed provided the voltage polarities are appropriately changed in the manner well known in the art. The structure can be utilized for alternating or direct current operation. Still further, the semiconductor region 22 which surrounds the cathode can be moditied to also include a guard ring region as is illustrated in Canadian patent application Serial No. 342,165.
'~ ' . ,, ' :
....
Claims (8)
1. A structure comprising a semiconductor body whose bulk is of one conductivity type and which has a major surface, a localized first region which is of the one conductivity type, and a localized second region and a localized third region which are both of the opposite conductivity type, each of the localized first, second and third regions being of relatively low resistivity as compared to the bulk portion of semiconductor body and being spaced apart from the others, and separate electrodes, being connected to each of the first, second and third regions, the localized first, second and third regions each having a portion thereof which forms a part of said major surface, the semiconductor body is separated from a semiconductor wafer (substrate) by a dielectric layer, the semiconductor wafer (substrate) is adapted to facilitate connection to an electrode and is characterized by a localized fourth layer of the same conductivity type as the third region, the fourth layer being sandwiched between the dielecric layer and the semiconductor body.
2. The structure of claim 1 further characterized in that the semiconductor body includes a fifth region of the one conductivity type and of resistivity intermediate between that of the bulk of semiconductor body and the first region, the fifth region encircling the third region.
3. The structure of claim 1 further characterized by a plurality of the semiconductor bodies dielectrically isolated from one another within the semiconductor wafer (substrate).
4. The structure of claim 2 characterized in that the conductivity of the semiconductor body, the first region, the second region, the third region, and the fourth layer is p-, p+, n+, n+, and n+ type, respectively, and the dielectric layer is silicon dioxide.
5. The structure of claim 4 characterized in that the semiconductor wafer (substrate) is of n type conductivity.
6. The structure of claim 4 characterized in that the semiconductor wafer (substrate) is of p type conductivity.
7. The structure of claim 1 further characterized in that the fourth layer completely separates the semi-conductor body from the dielectric layer.
8. The structure of claim 1 further characterized in that the fourth layer only exists between a portion of the semiconductor body and dielectric layer, the fourth layer being located approximately below the second region.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US97202178A | 1978-12-20 | 1978-12-20 | |
| US972,021 | 1978-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1123122A true CA1123122A (en) | 1982-05-04 |
Family
ID=25519059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA340,787A Expired CA1123122A (en) | 1978-12-20 | 1979-11-28 | High voltage dielectrically isolated dual gate solid-state switch |
Country Status (3)
| Country | Link |
|---|---|
| BE (1) | BE880728A (en) |
| CA (1) | CA1123122A (en) |
| TR (1) | TR21056A (en) |
-
1979
- 1979-11-28 CA CA340,787A patent/CA1123122A/en not_active Expired
- 1979-12-18 TR TR21056A patent/TR21056A/en unknown
- 1979-12-19 BE BE0/198641A patent/BE880728A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| BE880728A (en) | 1980-04-16 |
| TR21056A (en) | 1983-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4742380A (en) | Switch utilizing solid-state relay | |
| KR100780967B1 (en) | Structure of schottky diode for high voltage | |
| US3512058A (en) | High voltage transient protection for an insulated gate field effect transistor | |
| EP0111803B1 (en) | Lateral insulated-gate rectifier structures | |
| US4743952A (en) | Insulated-gate semiconductor device with low on-resistance | |
| US3806773A (en) | Field effect transistor having back-to-back diodes connected to the gate electrode and having a protective layer between the source and the diodes to prevent thyristor action | |
| US4608590A (en) | High voltage dielectrically isolated solid-state switch | |
| EP0071335B1 (en) | Field effect transistor | |
| US5077590A (en) | High voltage semiconductor device | |
| US5587595A (en) | Lateral field-effect-controlled semiconductor device on insulating substrate | |
| US4630092A (en) | Insulated gate-controlled thyristor | |
| US3590343A (en) | Resonant gate transistor with fixed position electrically floating gate electrode in addition to resonant member | |
| US4587545A (en) | High voltage dielectrically isolated remote gate solid-state switch | |
| JP2687163B2 (en) | Turn-off thyristor | |
| US4587656A (en) | High voltage solid-state switch | |
| EP0115098B1 (en) | Lateral dmos transistor device having an injector region | |
| US4602268A (en) | High voltage dielectrically isolated dual gate solid-state switch | |
| US4309715A (en) | Integral turn-on high voltage switch | |
| CA1123122A (en) | High voltage dielectrically isolated dual gate solid-state switch | |
| EP0099926B1 (en) | Field-effect controlled bi-directional lateral thyristor | |
| US5532502A (en) | Conductivity-modulated-type MOSFET | |
| WO1980001337A1 (en) | High voltage dielectrically isolated solid-state switch | |
| US4586073A (en) | High voltage junction solid-state switch | |
| US4641163A (en) | MIS-field effect transistor with charge carrier injection | |
| US4467344A (en) | Bidirectional switch using two gated diode switches in a single dielectrically isolated tub |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |