JP3296936B2 - Power semiconductor device - Google Patents
Power semiconductor deviceInfo
- Publication number
- JP3296936B2 JP3296936B2 JP06296095A JP6296095A JP3296936B2 JP 3296936 B2 JP3296936 B2 JP 3296936B2 JP 06296095 A JP06296095 A JP 06296095A JP 6296095 A JP6296095 A JP 6296095A JP 3296936 B2 JP3296936 B2 JP 3296936B2
- Authority
- JP
- Japan
- Prior art keywords
- glass
- power semiconductor
- etching
- semiconductor device
- glass structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000011521 glass Substances 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 9
- 238000005245 sintering Methods 0.000 claims description 7
- 230000005684 electric field Effects 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000000725 suspension Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000010276 construction Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005219 brazing Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 230000002779 inactivation Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、１２００Ｖ以上の高耐
逆電圧及び高温定格用の少なくとも１個のｐｎ遷移域及
びプレーナ構造を有する電力半導体素子に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device having at least one pn transition region and a planar structure for a high reverse voltage resistance of 1200 V or more and a high temperature rating.
【０００２】[0002]
【従来の技術】高耐電圧半導体素子は、大電力の電気・
電子回路の発展に伴い、特に駆動技術の回路装置の新た
な創生に益々重要になっている。電力定格が大きくなる
のと並行して、半導体素子の高耐電圧も高度になるべき
である。安定度の要求と共に、高動作電圧及び高周波の
動作範囲についても当業者は新たな課題に直面してい
る。2. Description of the Related Art A high withstand voltage semiconductor device is a high-power
With the development of electronic circuits, they have become increasingly important, especially for the creation of new circuit devices for driving technology. As the power rating increases, the high withstand voltage of the semiconductor device should also increase. Those skilled in the art are facing new challenges for high operating voltage and high frequency operating ranges as well as stability requirements.
【０００３】Solid State Electronics, Vol.25, No.5,
pp.423-427,1982では、”電界制限リング電位リング
（Field limiting ring)”構造により、高耐電圧プレー
ナ層の達成の可能性に対する技術的な考察が行われてい
る。[0003] Solid State Electronics, Vol. 25, No. 5,
In pp. 423-427, 1982, technical considerations are made on the possibility of achieving a high withstand voltage planar layer by using a "field limiting ring" structure.
【０００４】"IEEE, Vol.ed.26, No.7 von 1979"には、
電界効果電極によるプレーナ構造の酸化物層の強度の影
響について記載されている。この概略した従来技術は、
この分野での固有の動作に鑑みて、パラメータを改良す
るための多数の発想の基礎になっている。いずれの場合
にも、それぞれの新たな課題により従来技術を改良し、
別の知識が得られ、公開されている。[0004] "IEEE, Vol. Ed. 26, No. 7 von 1979"
The effect of the field effect electrode on the strength of the oxide layer having a planar structure is described. This outlined prior art is:
In view of the inherent behavior in this area, it is the basis for a number of ideas for improving parameters. In each case, each new challenge improves upon the prior art,
Another knowledge is gained and published.
【０００５】ドイツ特許第 3024939 号公報には、例え
ばサイリスタについて表面不活性化（Oberflaechenpass
ivierung）の特性の意味が詳細に説明されている。耐逆
電圧の劣化の発生が不活性化材料の不純物イオンに起因
するという認識は、メサー構造を有するサイリスタだけ
でなく、プレーナ構造に対しても同様に適用される。[0005] DE 3024939 discloses, for example, surface passivation of thyristors (Oberflaechenpass).
ivierung) properties are explained in detail. The recognition that the deterioration of the reverse voltage is caused by the impurity ions of the passivation material applies not only to the thyristor having the mesa structure but also to the planar structure.
【０００６】ドイツ特許第 3338718 号公報には、チャ
ネルストッパを特徴とし、また互に関連する所定の絶縁
値を有する少なくとも１つの別の絶縁層が、縁構造の絶
縁層に成層されているプレーナ半導体構造の耐電圧が記
載されている。[0006] DE-A 33 38 718 discloses a planar semiconductor which is characterized in that it has a channel stop and at least one further insulation layer having a predetermined insulation value associated therewith is laminated to the insulation layer of the edge structure. The withstand voltage of the structure is described.
【０００７】ドイツ特許第 3542166 号公報には、ガラ
ス不活性化及び部分的なメサー構造を有する高電圧トラ
ンジスタを形成するための高価ではあるが非常に興味の
ある製造方法が記載されている。この方法は、他の類似
の目標機能を有する方法も、LTO、CVD、窒化物、TEOS 又は
SIPOS 層を形成するための不活性化方法だけを述べてお
り、製造上非常に高価で、製品が高コストになる。[0007] German Patent No. 3542166 describes an expensive but very interesting manufacturing method for forming high-voltage transistors with glass passivation and partial mesa structures. This method can be used with other similar target functions, such as LTO, CVD, nitride, TEOS or
It describes only the passivation method for forming the SIPOS layer, which is very expensive to manufacture and expensive.
【０００８】チップの外側境界に電位リングを構成する
ことは、高耐電圧の非常に安定した半導体素子をもたら
す。これは、耐電圧を高くする素子の形成に際して他の
方法と並んで最近の文献にしばしば利用されている。既
述の文献の他に、課題が非常に近似するので、ドイツ特
許第 3721001 号公報及び欧州特許公開第 0485648 号公
報も挙げることができる。同様に、メサー構造、熱形成
された酸化物の全ての不活性化方法及び有機的な"Junct
ion coating"による不活性化は、従来技術に属する。The construction of a potential ring on the outer boundary of the chip results in a very stable semiconductor device with a high withstand voltage. This is often used in recent literature along with other methods in forming devices with high withstand voltage. In addition to the above-mentioned documents, German Patent No. 3721001 and European Patent Publication No. 0485648 can also be cited, since the problems are very similar. Similarly, mesa structures, all methods of passivation of thermoformed oxides and organic "Junct"
Inactivation by "ion coating" belongs to the prior art.
【０００９】[0009]
【発明が解決しようとする課題】本発明は、製造方法が
技術的に不可欠な他の製造過程及び方法に適合可能で、
かつ非常に経済的に有利に製造可能な高電力及び高耐逆
電圧用の半導体素子を形成することを課題にする。SUMMARY OF THE INVENTION The present invention is compatible with other manufacturing processes and methods whose manufacturing method is technically essential,
It is another object of the present invention to form a semiconductor element for high power and high withstand voltage that can be manufactured very economically and advantageously.
【００１０】[0010]
【課題を解決するための手段】この課題は、高電圧及び
高温定格用の、電位リング構造、少なくとも１個のｐｎ
−遷移域、及びプレーナ構造を有する電力半導体素子に
して、付加的にコーティングされただけのガラス不活性
化層を有する電力半導体素子において、熱的な酸化によ
ってケイ素表面から形成された酸化物層全てを平坦な素
子表面から除去した後に、前記付加構成されたガラス構
造全体が、ガラスを含むサスペンションのスピンオン並
びにスピンオンに引き続いての焼結によって形成されて
おり、且つ当該ガラス構造が境界縁にそれぞれ傾斜した
段部を所定のエッチング縁として有するようにフォトエ
ッチングマスク及びエッチング化学薬品を用いたガラス
エッチングにより構造化されており、当該境界縁上で、
重なる電界プレートがチップ内側領域において構成され
且つシールド電極がチップエッジ領域に構成されている
ことにより解決される。SUMMARY OF THE INVENTION The object is to provide a potential ring structure for high voltage and high temperature ratings, at least one pn.
All oxide layers formed from the silicon surface by thermal oxidation in power semiconductor devices having a transition zone and a glass passivation layer which is only additionally coated as a power semiconductor device having a planar structure. after removal from the planar device surface, overall the additional configuration glass structure, the glass is formed by sintering the following the spin to spin parallel <br/> beauty of the suspension including, and the glass structure It is structured by glass etching using a photo-etching mask and an etching chemical so as to have a step portion inclined at a boundary edge as a predetermined etching edge, and on the boundary edge,
The problem is solved by the fact that the overlapping electric field plates are formed in the chip inner region and the shield electrodes are formed in the chip edge region.
【００１１】本発明はダイオードの例について説明する
が、従来技術を基に得られた認識が本発明の解決につな
がっている。実施例では、電力半導体回路装置の整流回
路におけるフライホイールダイオードとして採用される
電力ダイオードについて説明する。このようなダイオー
ドは、整流回路に採用されるトランジスタ回路にパラメ
ータ的に適合可能で、製造技術的には回路装置の製造の
技術過程に耐える必要がある。この高度な技術的な要請
は、経済的に実現されねばならない。このような電力ダ
イオードの必要なパラメータは、一方では従来技術に対
応した手段の使用により、他方では次に説明する本発明
の手段により達成される。Although the present invention will be described with reference to an example of a diode, the recognition obtained based on the prior art has led to the solution of the present invention. In the embodiment, a power diode used as a flywheel diode in a rectifier circuit of a power semiconductor circuit device will be described. Such a diode must be parametrically compatible with the transistor circuit employed in the rectifier circuit and must withstand the technical process of manufacturing the circuit device in terms of manufacturing technology. This high technical demand must be realized economically. The required parameters of such a power diode are achieved on the one hand by the use of means corresponding to the prior art, and on the other hand by the means of the invention described below.
【００１２】[0012]
【作用】付加構成されたガラス構造により、プレーナ構
造の全ての表面不活性化が行われ、高い逆耐電圧特性及
び高い動作温度での高い電圧安定度が得られる。With the additional glass structure, all surface inactivation of the planar structure is performed, and a high reverse withstand voltage characteristic and a high voltage stability at a high operating temperature can be obtained.
【００１３】[0013]
【実施例】図１乃至図６を基に本発明のプレーナ構造の
ダイオードの製造過程を概略的に説明する。図１は本発
明の電力ダイオードの拡散後の断面図である。図２は、
拡散されたケイ素ディスクに対する、スピンオン技術に
よるガラスサスペンションの成層状態を示すもので、ガ
ラスは半導体技術で要求され、かつ従来技術で使用され
ているように、良好な絶縁特性を有する通常の鉛ケイ酸
塩ガラスである。図３はガラス層の焼結後のウエハの状
態を示すもので、サスペンションの焼結用処理パラメー
タは周知であり、最大密度が８７０℃の焼結温度で生じ
るガラスが使用される。図４はガラスの写真構成後の状
態を示すもので、使用されるフォトエッチングマスク及
びエッチング化学薬品は従来技術のもので、エッチング
過程で所定のエッチング縁を形成するようなガラスエッ
チングの使用を参考にするのが重要である。図５はアノ
ード側のその構成前の金属被覆（Metallisierung）の状
態を示すもので、アノード金属の選択は素子のさらに別
の処理に従い、例えば陽極側にボンドにより外側の接触
部を設ける場合、アルミニウムの蒸着が好ましい。図６
はカソード側をも金属被覆された素子の断面図を示すも
ので、素子の外側の接触部用にろう付け技術を使用する
際にはカソード側に従来技術に対応するろう付け可能な
接点を用いる。ここで、ガラス構造は、電位リング上に
おいて、金属被覆することにより電気力線作用を及ぼし
且つエッチングにより形成される開口部を有する。 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of a diode having a planar structure according to the present invention will be schematically described with reference to FIGS. FIG. 1 is a sectional view of a power diode of the present invention after diffusion. Figure 2,
For diffused silicon disc, it indicates the stratified state of the glass suspension by spin-on techniques, the glass is required in semiconductor technology, and as used in the prior art, typically lead silicic having good insulation properties It is a silicate glass. FIG. 3 shows the state of the wafer after sintering of the glass layer, the processing parameters for sintering the suspension are well known, and glass produced at a sintering temperature with a maximum density of 870 ° C. is used. FIG. 4 shows the state of the glass after the photographic construction. The photo-etching mask and the etching chemistry used are those of the prior art, and refer to the use of glass etching to form a predetermined etching edge in the etching process. It is important to FIG. 5 shows the state of the metallization before its construction on the anode side, the choice of the anode metal being in accordance with a further treatment of the device, for example, when the outer contact is provided by bonding on the anode side, aluminum Is preferred. FIG.
Figure 2 shows a cross-sectional view of a device with metallization on the cathode side as well, using brazing contacts corresponding to the prior art on the cathode side when using brazing technology for the contacts outside the device. . Here, the glass structure is placed on the potential ring
In the case of metal coating,
And it has an opening formed by etching.
【００１４】図６はダイオードの横断面の等尺によらな
い基本的な構成を示すもので、電力ダイオードの縁領域
の断面を示す。ダイオードの原材料は、５０及び１００
Ωｃｍ間の耐電圧条件に応じたグランドドーピング部
（２）を有し、ｎにドープされている。ダイオード特性
を改良するために、周知の方法により３Ｄ方法で陰極側
に追加的に負の電荷キャリア（１）が拡散されている。FIG. 6 shows a basic structure of the diode, not depending on the scale of the cross section, and shows a cross section of an edge region of the power diode. Diode raw materials are 50 and 100
It has a ground doping portion (2) corresponding to a withstand voltage condition of Ωcm, and is doped n. In order to improve the diode properties, negative charge carriers (1) are additionally diffused on the cathode side in a known manner in a 3D manner.
【００１５】陽極ドーピング部（３）の形成のために、
拡散過程でｐの電位リング（３）の並列形成を可能にす
るフォトマスクが使用される。本発明の電力ダイオード
では、素子の切り離し後にダイオードの外側縁になる領
域にｎ++のストップ電極（４）が拡散される。For the formation of the anode doping part (3),
A photomask is used that allows the parallel formation of p potential rings (3) during the diffusion process. In the power diode of the present invention, the n ++ stop electrode (4) is diffused in a region which becomes the outer edge of the diode after the device is separated.
【００１６】本発明による素子の高安定度は、前述の拡
散に続く不活性化により得られる。拡散中に熱的に膨張
する全ての酸化物は、エッチング技術により除去され、
表面が高度に純化される。The high stability of the device according to the invention is obtained by the above-mentioned diffusion followed by passivation. All oxides that thermally expand during diffusion are removed by etching techniques,
The surface is highly purified.
【００１７】電位ポテンシャルリングの領域には、約１
２μｍの均一に形成された層厚のガラス状の高耐電圧の
絶縁層が構成される。エッチング技術により、シールド
電極（６）もしくは電界板（７）の下方に酸化物層が４
０°程度の角度で突出するように、所与の角度で付加構
成されたガラスの縁を形成することが可能である。In the region of the potential ring, about 1
A glass-like high withstand voltage insulating layer having a uniform thickness of 2 μm is formed. An oxide layer is formed under the shield electrode (6) or the electric field plate (7) by an etching technique.
It is possible to form an edge of the glass additionally formed at a given angle so as to project at an angle of the order of 0 °.
【００１８】絶縁層の前述の規定のガラス層厚（５）
は、逆電圧の印加及び高動作温度（１５０℃の接合温
度）に際して、チップ周囲及びガラス絶縁層の下方にお
ける素子表面間のイオン変動を回避させる。これは、ポ
リイミド又は接合コーティングの成層に際して常に観察
される。The above specified glass layer thickness of the insulating layer (5)
Prevents application of a reverse voltage and a high operating temperature (150 ° C. junction temperature) to avoid ion fluctuation between the element surface around the chip and below the glass insulating layer. This is always observed during the deposition of the polyimide or bonding coating.
【００１９】電界板構造（７）とストップ電極（４、
６）との組み合せは、ケイ素表面での導電チャネルの形
成を防止する。図６において符号８は、素子裏面に形成
された金属被覆部を示す。金属被覆部８はろう付け可能
な金属（例えば銀）から成り、モジュールまたは回路を
組み立てる際に回路装置の適当な基部（例えば絶縁体の
銅層）にろう付けされる。The electric field plate structure (7) and the stop electrodes (4,
The combination with 6) prevents the formation of conductive channels on the silicon surface. In FIG. 6, reference numeral 8 denotes a metal covering portion formed on the back surface of the element . The metallization 8 consists of a brazeable metal (for example silver) and is brazed to a suitable base of the circuit arrangement (for example an insulating copper layer) when assembling the module or the circuit.
【００２０】本発明のダイオードは、製造の単純化に加
えて別の顕著な特徴を有する。つまり、このタイオード
はさらにろう付け技術の処理を行う際に丈夫である。ま
た、絶縁特性を損なうことなく、キャリヤ寿命期間を設
定するために他の不純物拡散を行うこともできる。The diode of the present invention has another significant feature in addition to simplification of manufacture. That is, the tie is durable for further brazing techniques. In addition, other impurity diffusion can be performed to set the carrier lifetime without impairing the insulating characteristics.
【００２１】絶縁層は、電子照射又はヘリウム核の注入
のような照射の利用に対して制限なく適合する。充分に
高い耐逆電圧特性を達成するためのダイオードの例につ
いての技術は、一般的に同様な方法により１個以上のｐ
ｎ遷移域を有する素子にも適用される。The insulating layer is adapted without limitation to the use of irradiation, such as electron irradiation or implantation of helium nuclei. Techniques for the diode example to achieve sufficiently high reverse voltage resistance are generally achieved in a similar manner with one or more p-types.
It also applies to devices having n transition regions.
【００２２】したがって、同様な方法でバイポーラトラ
ンジスタ、インセル、ゲート、バイポーラトランジスタ
又はMOSFETが、部分的に"Spin on" ガラス領域を伴って
製造され得る。Thus, in a similar manner, a bipolar transistor, in-cell, gate, bipolar transistor or MOSFET can be manufactured with a partial "Spin on" glass region.
【００２３】電位リング構造用の空間は、幾何学形状の
縮小に際して重要な意味を果たす。本発明のガラス不活
性化には、電極の成層はドイツ特許第 3338718 号公報
で符号（７）で示されているような電極の成層が適合す
る。本発明のガラスにこのように形成された電極は、そ
こに説明されているのと同じ作用を果たす。この電極
は、併せて図５に対応して金属被覆可能であり、続いて
図６に示すように構成可能である。The space for the potential ring structure plays an important role in reducing the geometry. For the passivation of the glass according to the invention, the electrode layer is adapted to the electrode layer as indicated by reference (7) in DE 3338718. The electrodes thus formed on the glass of the present invention perform the same functions as described therein. This electrode can also be metallized in accordance with FIG. 5 and subsequently configured as shown in FIG.
【００２４】[0024]
【発明の効果】以上、本発明によれば、経済的に有利に
製造可能な高電力・高耐逆電圧・高温下の高電圧安定度
用半導体素子が実現される。As described above, according to the present invention, a semiconductor device for high power, high reverse voltage resistance and high voltage stability under high temperature, which can be produced economically and advantageously, is realized.
【図１】本発明の電力ダイオードの拡散後の要素の断面
図である。FIG. 1 is a cross-sectional view of a diffused element of a power diode of the present invention.
【図２】同電力ダイオードのスピンオン技術によるガラ
スサスペンションの成層状態を示す。FIG. 2 shows a stratified state of a glass suspension by a spin-on technique of the power diode.
【図３】同電力ダイオードのガラス層の焼結後のウエハ
の状態を示す。FIG. 3 shows a state of a wafer after sintering a glass layer of the power diode.
【図４】同電力ダイオードのガラスの写真構成後の状態
を示す。FIG. 4 shows a state of the glass of the power diode after photographic construction.
【図５】同電力ダイオードのアノード側のその構成前の
金属被覆部を示す。FIG. 5 shows the metallization on the anode side of the power diode before its construction.
【図６】同電力ダイオードのカソード側をも金属被覆さ
れた状態の断面図を示す。FIG. 6 is a sectional view showing a state where the cathode side of the power diode is also metal-coated.
３ 電位リング構造 ５ ガラス構造 ６ シールド電極 ７ 電界板 3 Potential ring structure 5 Glass structure 6 Shield electrode 7 Electric field plate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ヴェルナー ジッヒェルシュティール ドイツ連邦共和国 デー・90552 レー テンバッハ／ぺーグニツ フリードリヒ フォン フューラーシュトラーセ 11 (72)発明者 ハインツ・オーラフ ヘーネル ドイツ連邦共和国 デー・96152 ブル クハスラッハ リンデンヴェーク １ (56)参考文献 特開 昭58−151068（ＪＰ，Ａ) 特開 昭51−110272（ＪＰ，Ａ) 特開 昭55−6875（ＪＰ，Ａ) 特開 昭63−5575（ＪＰ，Ａ) 特開 昭63−5574（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/06 H01L 29/861 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Werner Zichelstil Germany 90905 Rehtenbach / Eugnitz Friedrich von Fühlerstraße 11 (72) Inventor Heinz Olaf Henneel Germany 96152 Bruchslach Lindenweg 1 (56) Reference JP-A-58-151068 (JP, A) JP-A-51-110272 (JP, A) JP-A-55-6687 (JP, A) JP-A-63-5575 (JP) , A) JP-A-63-5574 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/06 H01L 29/861
Claims (6)
造、少なくとも１個のｐｎ−遷移域、及びプレーナ構造
を有する電力半導体素子にして、付加的にコーティング
されただけのガラス不活性化層を有する電力半導体素子
において、 熱的な酸化によってケイ素表面から形成された酸化物層
全てを平坦な素子表面から除去した後に、前記付加構成
されたガラス構造（５）全体が、ガラスを含むサスペン
ションのスピンオン並びにスピンオンに引き続いての焼
結によって形成されており、且つ当該ガラス構造（５）
が境界縁にそれぞれ傾斜した段部を所定のエッチング縁
として有するようにフォトエッチングマスク及びエッチ
ング化学薬品を用いたガラスエッチングにより構造化さ
れており、当該境界縁上で、重なる電界プレート（７）
がチップ内側領域において構成され且つシールド電極
（６）がチップエッジ領域に構成されていることを特徴
とする電力半導体素子。1. A glass passivation layer which is only additionally coated in a power semiconductor component having a potential ring structure, at least one pn-transition region, and a planar structure for high voltage and high temperature ratings. After removing all oxide layers formed from the silicon surface by thermal oxidation from the flat device surface, the entirety of the additional glass structure (5) is a suspension of glass containing glass. The glass structure formed by spin- on and sintering subsequent to spin- on , and the glass structure (5)
Are structured by glass etching using a photo-etching mask and etching chemistry so that each has a sloped step as a predetermined etching edge at the boundary, on which the electric field plate (7) overlaps
Are formed in a chip inner region, and the shield electrode (6) is formed in a chip edge region.
より形成されていることを特徴とする請求項１に記載の
電力半導体素子。2. The power semiconductor device according to claim 1, wherein the glass structure (5) is formed from lead-silicate glass.
部を所定のエッチング縁として有することを特徴とする
請求項２に記載の電力半導体素子。3. The power semiconductor device according to claim 2, wherein the glass structure has a step which is inclined to a boundary edge as a predetermined etching edge.
を有するダイオードであり、カソード側に、ガラス構造
（５）にその内側の傾斜領域で重なる電界プレート
（７）を有し、ガラス構造（５）の外側の段部を覆うシ
ールド電極（６）を所持することを特徴とする請求項３
に記載の電力半導体素子。4. The power semiconductor device has a potential ring structure (3).
A shield electrode (6) on the cathode side, which has an electric field plate (7) overlapping the glass structure (5) in an inclined region inside the glass structure (5), and covers a step portion outside the glass structure (5). Claim 3 which possesses
A power semiconductor device according to item 1.
酸化物層の除去後に、拡散されたケイ素ディスクへスピ
ンオンされるサスペンションから生じるものであり、且
つ当該ガラス構造（５）が８７０℃での当該サスペンシ
ョンの焼結後にフォトエッチングマスク及びエッチング
化学薬品を用いたガラスエッチングにより形成されるこ
とを特徴とする請求項２に記載の電力半導体素子。5. The glass structure (5) spins on the diffused silicon disk after removal of the thermally generated oxide layer.
Wherein the glass structure (5) is formed by glass etching using a photo-etching mask and etching chemistry after sintering the suspension at 870 ° C. Item 3. A power semiconductor device according to item 2.
上において、金属被覆することにより電気力線作用を及
ぼし且つエッチングにより形成される開口部を有するこ
と特徴とする、請求項２に記載の電力半導体素子。6. The method according to claim 1, wherein the glass structure (5) comprises a potential ring (3).
3. The power semiconductor device according to claim 2, wherein the power semiconductor device has an opening formed by applying a line of electric force by being metal-coated thereon and being formed by etching.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4410354A DE4410354C2 (en) | 1994-03-25 | 1994-03-25 | Power semiconductor component |
| DE4410354:9 | 1994-03-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07273309A JPH07273309A (en) | 1995-10-20 |
| JP3296936B2 true JP3296936B2 (en) | 2002-07-02 |
Family
ID=6513818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06296095A Expired - Fee Related JP3296936B2 (en) | 1994-03-25 | 1995-03-22 | Power semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3296936B2 (en) |
| DE (1) | DE4410354C2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19606983C2 (en) * | 1996-02-24 | 2000-01-20 | Semikron Elektronik Gmbh | Power semiconductor component with a planar structure |
| US6870201B1 (en) | 1997-11-03 | 2005-03-22 | Infineon Technologies Ag | High voltage resistant edge structure for semiconductor components |
| DE19837944A1 (en) * | 1998-08-21 | 2000-02-24 | Asea Brown Boveri | Method of manufacturing a semiconductor device |
| DE10022384B4 (en) * | 1998-11-09 | 2004-07-22 | Semikron Elektronik Gmbh | Process for passivation of a fast power diode |
| DE19851461C2 (en) * | 1998-11-09 | 2003-07-31 | Semikron Elektronik Gmbh | Fast power diode and process for its passivation |
| DE10047152B4 (en) * | 2000-09-22 | 2006-07-06 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | High-voltage diode and method for its production |
| DE102006013076A1 (en) * | 2006-03-22 | 2007-09-27 | Semikron Elektronik Gmbh & Co. Kg | Power semiconductor component with passivation layer and associated production method |
| DE102006013077A1 (en) * | 2006-03-22 | 2007-09-27 | Semikron Elektronik Gmbh & Co. Kg | Power semiconductor component with secondary passivation layer and associated manufacturing method |
| DE102009017732A1 (en) | 2009-04-11 | 2010-10-21 | Semikron Elektronik Gmbh & Co. Kg | Power semiconductor component with an edge passivation and method for its production |
| JP5510908B2 (en) | 2010-02-26 | 2014-06-04 | 株式会社ピーアイ技術研究所 | Polyimide resin composition for semiconductor device, film forming method in semiconductor device using the same, and semiconductor device |
| JP2012069594A (en) | 2010-09-21 | 2012-04-05 | Pi R & D Co Ltd | Polyimide resin composition for forming insulating film in solar cell and method of forming insulating film in solar cell by using the same |
| FR3049770B1 (en) * | 2016-03-31 | 2018-07-27 | Stmicroelectronics (Tours) Sas | VERTICAL POWER COMPONENT |
| US10211326B2 (en) | 2016-03-31 | 2019-02-19 | Stmicroelectronics (Tours) Sas | Vertical power component |
| FR3049769B1 (en) * | 2016-03-31 | 2018-07-27 | Stmicroelectronics (Tours) Sas | VERTICAL POWER COMPONENT |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3024939C3 (en) * | 1979-07-02 | 1994-08-11 | Hitachi Ltd | Semiconductor device |
| JPS5976466A (en) * | 1982-10-25 | 1984-05-01 | Mitsubishi Electric Corp | Planar type semiconductor device |
| DE3542166A1 (en) * | 1985-11-29 | 1987-06-04 | Telefunken Electronic Gmbh | SEMICONDUCTOR COMPONENT |
| DE3721001A1 (en) * | 1987-06-25 | 1989-01-05 | Bosch Gmbh Robert | HIGHLY LOCKING SEMICONDUCTOR COMPONENT |
| DE3832750A1 (en) * | 1988-09-27 | 1990-03-29 | Asea Brown Boveri | PERFORMANCE SEMICONDUCTOR COMPONENT |
| DE3832731A1 (en) * | 1988-09-27 | 1990-03-29 | Asea Brown Boveri | PERFORMANCE SEMICONDUCTOR DIODE |
| DE59009155D1 (en) * | 1990-11-12 | 1995-06-29 | Siemens Ag | Semiconductor component for high reverse voltage. |
-
1994
- 1994-03-25 DE DE4410354A patent/DE4410354C2/en not_active Expired - Fee Related
-
1995
- 1995-03-22 JP JP06296095A patent/JP3296936B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE4410354A1 (en) | 1995-10-19 |
| DE4410354C2 (en) | 1996-02-15 |
| JPH07273309A (en) | 1995-10-20 |
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