KR100744601B1 - Method for forming copper line in semiconductor device - Google Patents
Method for forming copper line in semiconductor device Download PDFInfo
- Publication number
- KR100744601B1 KR100744601B1 KR1020010088334A KR20010088334A KR100744601B1 KR 100744601 B1 KR100744601 B1 KR 100744601B1 KR 1020010088334 A KR1020010088334 A KR 1020010088334A KR 20010088334 A KR20010088334 A KR 20010088334A KR 100744601 B1 KR100744601 B1 KR 100744601B1
- Authority
- KR
- South Korea
- Prior art keywords
- copper
- forming
- cmp process
- semiconductor device
- wiring
- Prior art date
Links
- 239000010949 copper Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 56
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 55
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 239000007800 oxidant agent Substances 0.000 claims abstract description 17
- 230000001590 oxidative effect Effects 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 239000007788 liquid Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 239000002002 slurry Substances 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 6
- 230000003628 erosive effect Effects 0.000 abstract description 3
- 239000003082 abrasive agent Substances 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 4
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 3
- 229910001431 copper ion Inorganic materials 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 구리배선 형성방법에 관한 것으로, 반도체 소자의 구리배선 형성방법은, 반도체 기판 상에 비아홀 및 트랜치를 포함한 다수의 배선 형성 영역을 갖는 산화막을 형성하는 단계; 상기 산화막 상에 배리어막을 형성하는 단계; 상기 비아홀 및 트랜치가 매립되도록 상기 배리어막 상에 구리층을 형성하는 단계; 상기 배리어막이 노출되지 않도록 상기 구리층에 1차 CMP 공정을 진행하는 단계; 상기 배선 형성 영역 간에 형성된 배리어막이 노출되도록 상기 잔류 구리층을 연마제를 포함하지 않는 산화제를 사용하는 2차 CMP 공정으로 제거하는 단계; 및 상기 배선 형성 영역 간의 산화막이 노출되도록 상기 배리어막을 3차 CMP 공정으로 제거하는 단계를 포함하며, 배리어막 상부의 구리를 제거하는 경우 연마제 없이 구리산화제로만 CMP 공정을 진행함으로써 슬러리 연마제로 인한 스크래치, 슬러리 잔류물, 슬러리의 낮은 선택비(selectivity)로 인한 디싱(dishing) 및 침식(erosion)과 같은 CMP 결함들을 현저히 줄일 수 있어 소자의 품질을 향상시킬 수 있으며, 제조수율 또한 높일 수 있는 것이다.The present invention relates to a method for forming copper wiring of a semiconductor device, the method for forming copper wiring of a semiconductor device comprising the steps of: forming an oxide film having a plurality of wiring formation regions including via holes and trenches on a semiconductor substrate; Forming a barrier film on the oxide film; Forming a copper layer on the barrier layer to fill the via hole and the trench; Performing a first CMP process on the copper layer so that the barrier layer is not exposed; Removing the residual copper layer by a second CMP process using an oxidant containing no abrasive so that the barrier film formed between the wiring forming regions is exposed; And removing the barrier film by a third CMP process so that the oxide film between the wiring forming regions is exposed, and when removing the copper on the barrier film, the CMP process is performed only with the copper oxidant without the abrasive, thereby causing scratches due to slurry abrasives. CMP defects such as slurry residues, dishing and erosion due to the low selectivity of the slurry can be significantly reduced to improve device quality and yield.
Description
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 구리배선 형성방법을 설명하기 위한 공정별 단면도.1 to 4 are cross-sectional views for each process for explaining a method of forming copper wirings of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10; 산화막 20; 배리어막10;
30,30a; 구리층 30b; 구리배선30,30a;
본 발명은 반도체 소자의 구리배선 형성방법에 관한 것으로, 보다 상세하게는 구리 산화제를 이용한 구리 CMP 공정을 진행함으로써 결함 발생을 줄이는 반도체 소자의 구리배선 형성방법에 관한 것이다.The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly, to a method for forming a copper wiring of a semiconductor device to reduce defects by performing a copper CMP process using a copper oxidant.
최근 반도체 소자의 고집적화가 되어감에 따라 웨이퍼 표면의 평탄화에 대한 요구는 더욱 절실해지는 것이 주지의 사실이다. 따라서, 현재까지 개발된 기술중 가장 효과적인 웨이퍼 표면 평탄화 기술인 CMP 공정의 적용범위는 점차로 확대되어 가고 있다. It is well known that the demand for planarization of the wafer surface becomes more urgent as the semiconductor devices become more integrated in recent years. Therefore, the application range of the CMP process, which is the most effective wafer surface planarization technology developed to date, is gradually expanding.
CMP란 화학적 기계적 연마공정을 뜻하는 것으로, 웨이퍼 표면에 연마액인 슬러리와 기계적 압력을 가하면서 웨이퍼와 패드를 마찰시켜 웨이퍼 표면에 형성된 수천Å의 단차를 제거하거나 금속배선을 형성하는 기술이다.CMP refers to a chemical mechanical polishing process, and is a technique for removing thousands of steps of steps formed on the wafer surface or forming metal wiring by rubbing the wafer and the pad while applying mechanical pressure with the slurry, which is a polishing liquid, on the wafer surface.
종래 기술에 따른 반도체 소자의 구리배선 형성방법은, 금속배선이 형성될 지역의 산화막층 식각하는 단계와, 구리이온 확산방지 및 결합(adhesion) 증가를 위한 구리 배리어막을 증착하는 단계와, 전기도금법 적용을 위한 CVD 구리 씨드막(Cu seed layer) 증착하는 단계와, Cu 전기도금 및 어닐링 단계와, Cu CMP를 이용한 잉여 Cu 및 배리어막 제거 단계로써 이루어진다.The method for forming a copper wiring of a semiconductor device according to the related art includes etching an oxide layer in a region where a metal wiring is to be formed, depositing a copper barrier film for preventing copper ion diffusion and increasing adhesion, and applying an electroplating method. CVD Cu seed layer deposition, Cu electroplating and annealing step, and removing the excess Cu and barrier film using Cu CMP.
그러나, 종래 기술에 따른 반도체 소자의 구리배선 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the copper wiring forming method of the semiconductor device according to the prior art has the following problems.
종래 기술에 있어서는, Cu CMP 공정 적용으로 인한 구리배선의 디싱, 침식, 산화막 박형화, 스크래치, 및 슬러리 잔유물 등의 결함이 발생하게 된다. 이러한 Cu CMP 결함들은 구리배선 두께를 일정하게 제어할 수 없게 하고, 또한 배선간 브릿지를 유발하게 하여 설계 단계에서 원하던 안정적인 전기적 특성을 얻을 수 없게 만들어 소자의 기능이나 안정성, 수명 및 수율 등에 악영향을 끼치게 된다는 문제점이 있다.In the prior art, defects such as dishing, erosion, thinning of the oxide film, scratches, and slurry residues of the copper wiring due to the application of the Cu CMP process occur. These Cu CMP defects make it impossible to control the thickness of the copper wiring uniformly, and also cause bridges between the wires, and thus do not obtain the desired stable electrical characteristics at the design stage, which adversely affects the function, stability, lifespan and yield of the device. There is a problem.
이에, 본 발명은 상기 종래 기술의 제반 문제점들을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 구리 산화제를 이용하여 CMP 공정을 진행함으로써 CMP 결함을 줄여 수율을 향상시키는 반도체 소자의 구리배선 형성방법을 제공함에 있 다.Accordingly, the present invention has been made to solve the above problems of the prior art, an object of the present invention is to provide a method for forming a copper wiring of a semiconductor device to improve the yield by reducing the CMP defects by the CMP process using a copper oxidant In the provision.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 구리배선 형성방법은, 반도체 기판 상에 비아홀 및 트랜치를 포함한 다수의 배선 형성 영역을 갖는 산화막을 형성하는 단계; 상기 산화막 상에 배리어막을 형성하는 단계; 상기 비아홀 및 트랜치가 매립되도록 상기 배리어막 상에 구리층을 형성하는 단계; 상기 배리어막이 노출되지 않도록 상기 구리층에 1차 CMP 공정을 진행하는 단계; 상기 배선 형성 영역 간에 형성된 배리어막이 노출되도록 상기 잔류 구리층을 연마제를 포함하지 않는 산화제를 사용하는 2차 CMP 공정으로 제거하는 단계; 및 상기 배선 형성 영역 간의 산화막이 노출되도록 상기 배리어막을 3차 CMP 공정으로 제거하는 단계;를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a copper wiring of a semiconductor device, the method including: forming an oxide film having a plurality of wiring forming regions including a via hole and a trench on a semiconductor substrate; Forming a barrier film on the oxide film; Forming a copper layer on the barrier layer to fill the via hole and the trench; Performing a first CMP process on the copper layer so that the barrier layer is not exposed; Removing the residual copper layer by a second CMP process using an oxidant containing no abrasive so that the barrier film formed between the wiring forming regions is exposed; And removing the barrier film by a third CMP process so that an oxide film between the wiring forming regions is exposed.
이하, 본 발명에 따른 반도체 소자의 구리배선 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming copper wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 구리배선 형성방법을 설명하기 위한 공정별 단면도이다.1 to 4 are cross-sectional views for each process for explaining a method of forming copper wirings of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 구리배선 형성방법은, 도 1에 도시된 바와 같이, 반도체 기판(미도시)상에 형성된 산화막(10)을 선택적으로 제거한 비아홀(15)과 트렌치(17)를 포함한 상기 산화막(10) 전면상에 배리어막(20)을 형성한다. 상기 배리어막(20)은 구리 이온의 확산을 방지하며 또한 접착력(adhesion)을 증가시키기 위하여 Ta 또는 TaN을 증착하여 형성한다.In the method of forming a copper wiring of a semiconductor device according to the present invention, as illustrated in FIG. 1, the method including a
이후에, 도에는 도시한지 않았지만 전기도금법(electroplating) 적용을 위해 CVD 구리 씨드막(Cu seed layer)을 증착한 다음 전극도금법 및 열처리(annealing)로 상기 산화막(10) 상에 구리층(30)을 형성한다.Subsequently, although not shown in the drawings, a CVD copper seed layer is deposited for electroplating, and then the
이어서, 도 2에 도시된 바와 같이, 상기 배리어막(20)이 노출되지 않을 정도 로 상기 구리층(30)의 약 70 내지 90%를 1차 CMP 공정으로 제거한다. 상기 1차 CMP 공정은 연마제(abrasive)를 포함하는 슬러리(slurry)를 사용하는데, 2 내지 7psi 하향력(down force)과 50 내지 500의 분당회전수(rpm) 조건으로 진행한다. 이때, 상기 슬러리의 유동 속도(flow rate)를 약 분당 50 내지 70ml 정도로 하여 공급한다.Next, as shown in FIG. 2, about 70 to 90% of the
그다음, 도 3에 도시된 바와 같이, 상기 배리어막(20)이 노출될 때까지 상기 잔류 구리층(30a)을 2차 CMP 공정으로 제거한다. 상기 2차 CMP 공정은 전단계와는 달리 슬러리를 대신하여 연마제가 없는 구리 산화제(Cu oxidizer)를 사용하는데, 상기 구리산화제는 구리를 산화시키는 물질로서 구리와 결합하여 구리를 CuX(여기서, X는 구리산화제)로 존재하게 하거나 구리 이온(Cu2+ 또는 Cu+)으로 만들어 용해될 수 있도록 하는 역할이다.3, the
상기 구리산화제로서는, H2O, DTA, F, K3Fe(CN)6, C4H4 O4, C6H5O7, C4H5ON, C4H4O5N, C4H5O6N, Cl, 또는 HNO3 에서 선택하여 사용한다. 한편, 상기 구리산화제 공급시점은 구리 제거 속도(removal rate)와 구리 도금의 증착량을 고려하여 CMP 공정 적용시간으로 결정하거나, 또는 적절한 시스템, 예를 들면, AMA사에서 공급하는 EPD 시스템을 이용하여 적절한 공급 시점을 결정할 수 있다.Examples of the copper oxidizing agent include H 2 O, DTA, F, K 3 Fe (CN) 6 , C 4 H 4 O 4 , C 6 H 5 O 7 , C 4 H 5 ON, C 4 H 4 O 5 N, C 4 H 5 O 6 N, Cl, or HNO 3 It is used to choose. Meanwhile, the copper oxidant supply point is determined by the CMP process application time in consideration of the removal rate of copper and the deposition amount of copper plating, or by using an appropriate system, for example, an EPD system supplied by AMA. An appropriate supply point can be determined.
이때, 상기 2차 CMP 공정은, 1 내지 7psi 하향력과 50 내지 500 의 분당회전수를 조건으로 진행하는데, 상기 구리산화제의 유동속도를 분당 50 내지 700ml로 하여 공급한다. At this time, the secondary CMP process, but the 1-7 psi down force and 50 to 500 RPM per condition, but the flow rate of the copper oxidant is supplied at 50 to 700 ml per minute.
한편, 상기 2차 CMP 공정후 3차 CMP 공정전에 잔류하는 구리산화제를 제거할 목적으로 린싱(rinsing) 단계를 더 포함할 수 있다. 상기 린싱 단계는 린싱액으로 DI(deionized) 워터와 BTA 혼합액을 사용하는데, 상기 린싱액에 포함된 BTA는 약 0.5 내지 10 중량%가 되도록 혼합하고 유동 속도를 분당 100 내지 600ml로 하여 공급하여 약 10 내지 60초 동안 진행한다.Meanwhile, a rinsing step may be further included for the purpose of removing the copper oxidant remaining after the second CMP process and before the third CMP process. The rinsing step uses a mixed solution of DI (deionized) water and BTA as a rinsing liquid, and the BTA contained in the rinsing liquid is mixed so as to be about 0.5 to 10 wt% and supplied at a flow rate of 100 to 600 ml per minute to about 10 For 60 seconds.
이어서, 도 4에 도시된 바와 같이, 상기 산화막(10) 상에 남아있는 배리어막(20)을 3차 CMP 공정으로 제거하여 구리배선(30b)을 완성한다. 상기 3차 CMP 공정은 연마제가 포함된 배리어막 제거용 슬러리를 사용하는데, 1 내지 4psi 하향력과 50 내지 500의 분당회전수 조건을 진행한다. 이때, 상기 슬러리는 유동속도를 분당 약 50 내지 700ml로 하여 공급한다.Next, as shown in FIG. 4, the
계속하여, 세정공정과 같은 예정된 후속공정을 진행하여 구리배선을 포함한 반도체 소자를 완성한다.Subsequently, a predetermined subsequent process such as a cleaning process is performed to complete a semiconductor device including copper wiring.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 구리배선 형성방 법에 있어서는 다음과 같은 효과가 있다.As described above, the copper wiring formation method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 배리어막 상부의 구리를 제거하는 경우에는 연마제 없이 구리산화제로만 CMP 공정을 진행함으로써 슬러리 연마제로 인한 스크래치, 슬러리 잔류물, 슬러리의 낮은 선택비(selectivity)로 인한 디싱(dishing) 및 침식(erosion)과 같은 CMP 결함들을 현저히 줄일 수 있어 소자의 품질을 향상시킬 수 있으며, 제조수율 또한 높일 수 있다.In the present invention, when the copper on the barrier film is removed, the CMP process is performed only with the copper oxidant without the abrasive, thereby causing dishing due to scratches, slurry residues, and low selectivity of the slurry. CMP defects, such as erosion, can be significantly reduced, improving device quality and increasing manufacturing yield.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010088334A KR100744601B1 (en) | 2001-12-29 | 2001-12-29 | Method for forming copper line in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010088334A KR100744601B1 (en) | 2001-12-29 | 2001-12-29 | Method for forming copper line in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030059471A KR20030059471A (en) | 2003-07-10 |
| KR100744601B1 true KR100744601B1 (en) | 2007-08-01 |
Family
ID=32215905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010088334A KR100744601B1 (en) | 2001-12-29 | 2001-12-29 | Method for forming copper line in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100744601B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040043383A (en) * | 2002-11-18 | 2004-05-24 | 주식회사 하이닉스반도체 | Method for forming Cu wiring of semiconductor device |
| KR100840475B1 (en) * | 2006-12-05 | 2008-06-20 | 동부일렉트로닉스 주식회사 | Metallization method of semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1056060A (en) * | 1996-08-09 | 1998-02-24 | Hitachi Ltd | Manufacture of semiconductor device |
| US6315883B1 (en) * | 1998-10-26 | 2001-11-13 | Novellus Systems, Inc. | Electroplanarization of large and small damascene features using diffusion barriers and electropolishing |
| JP2001358105A (en) * | 2000-06-12 | 2001-12-26 | Mitsubishi Electric Corp | Forming method of embedded wiring, cmp device, and semiconductor device and manufacturing method thereof |
-
2001
- 2001-12-29 KR KR1020010088334A patent/KR100744601B1/en active IP Right Grant
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1056060A (en) * | 1996-08-09 | 1998-02-24 | Hitachi Ltd | Manufacture of semiconductor device |
| US6315883B1 (en) * | 1998-10-26 | 2001-11-13 | Novellus Systems, Inc. | Electroplanarization of large and small damascene features using diffusion barriers and electropolishing |
| JP2001358105A (en) * | 2000-06-12 | 2001-12-26 | Mitsubishi Electric Corp | Forming method of embedded wiring, cmp device, and semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030059471A (en) | 2003-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20180182665A1 (en) | Processed Substrate | |
| US6521574B1 (en) | Copper-based metal polishing solution and method for manufacturing a semiconductor device | |
| US6946397B2 (en) | Chemical mechanical polishing process with reduced defects in a copper process | |
| US6943112B2 (en) | Defect-free thin and planar film processing | |
| US6774041B1 (en) | Polishing method, metallization fabrication method, method for manufacturing semiconductor device and semiconductor device | |
| KR100396883B1 (en) | Slurry for chemical mechanical polishing and manufacturing method of copper metal interconnection layer using the same | |
| JP2012191226A (en) | Copper interconnect seed layer treatment method and apparatus for treating the same | |
| CN100419963C (en) | Forming a semiconductor structure using a combination of planarizing methods and electropolishing | |
| US20060118425A1 (en) | Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate | |
| US20040253809A1 (en) | Forming a semiconductor structure using a combination of planarizing methods and electropolishing | |
| CN109148356A (en) | Semiconductor structure and forming method thereof | |
| US7361582B2 (en) | Method of forming a damascene structure with integrated planar dielectric layers | |
| US20050016861A1 (en) | Method for planarizing a work piece | |
| US6984582B2 (en) | Method of making semiconductor device by polishing with intermediate clean polishing | |
| TW200535987A (en) | Reverse-tone mask method for post-cmp elimination of copper overburden humps | |
| KR100744601B1 (en) | Method for forming copper line in semiconductor device | |
| US6670272B2 (en) | Method for reducing dishing in chemical mechanical polishing | |
| US20030203705A1 (en) | Chemical-mechanical polishing slurry with improved defectivity | |
| KR100567913B1 (en) | Method of forming a metal wiring in a semiconductor device | |
| US6211060B1 (en) | Method for planarizing a damascene structure | |
| KR19980048378A (en) | Planarization method of semiconductor device | |
| KR20010058992A (en) | Method for fabricating using chemical mechanical polishing | |
| JP2003193300A (en) | Method of manufacturing semiconductor device, electrolytic etching apparatus and apparatus for manufactured semiconductor | |
| JP2001257188A (en) | Method of manufacturing semiconductor integrated circuit device | |
| KR100537207B1 (en) | Chemical mechanical polishing of noble metal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| G170 | Re-publication after modification of scope of protection [patent] | ||
| FPAY | Annual fee payment |
Payment date: 20130620 Year of fee payment: 7 |
|
| FPAY | Annual fee payment |
Payment date: 20140618 Year of fee payment: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20150617 Year of fee payment: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20160620 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20170626 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20180618 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20190619 Year of fee payment: 13 |