US20030203705A1 - Chemical-mechanical polishing slurry with improved defectivity - Google Patents

Chemical-mechanical polishing slurry with improved defectivity Download PDF

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US20030203705A1
US20030203705A1 US10/132,572 US13257202A US2003203705A1 US 20030203705 A1 US20030203705 A1 US 20030203705A1 US 13257202 A US13257202 A US 13257202A US 2003203705 A1 US2003203705 A1 US 2003203705A1
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slurry
copper
rodel
aged
cmp
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Yaojian Leng
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • the present invention relates generally to the field of chemical mechanical polishing (CMP) process used to fabricate semiconductor devices. Specifically, the invention relates to the treatment of slurry used in CMP processes where copper is used as interconnecting material in the semiconductor devices.
  • CMP chemical mechanical polishing
  • damascene is typically used to create the copper interconnect on chip.
  • dual damascene when the trench and via are formed simultaneously on the wafer, the process is called dual damascene, and when the trench or via are formed separately on the wafer, the process is called single damascene.
  • trench and/or via is etched into dielectric layer, barrier (typically Ta, TaN) and seed copper are deposited into the trench and/or via, and bulk copper is deposited by electroplating.
  • the electro-chemically plated copper not only filled the desired area on the wafer (trench and/or via), it also over burden on the other area, leaving an un-planarized wafer surface.
  • Chemical mechanical polishing is used to remove the redundant copper and to planarize the wafer surface.
  • Copper CMP is a multi-step process. During the 1 st step, a slurry of high selectivity of copper to barrier is used in the removal of a majority or all redundant copper from the wafer surface. The high selectivity of copper removal rate to barrier removal rate is designed so the polish can stop on the barrier layer. Hence, the non-uniformity form electro-chemical deposition will not be transferred into the final copper thickness variation.
  • the copper layer disposed inside the trenches also may become polished with the high selectivity copper-polishing slurry.
  • This over-polishing of the copper layer disposed inside the trenches causes a depression of the copper layer, such that the copper layer becomes uneven, an effect which is known as dishing.
  • a barrier slurry is used to polish off the barrier.
  • the barrier polish removes barrier material, dielectric material, and copper at similar rates to improve process margin and to reduce dishing.
  • a 3 rd step called buff step, is also used to improve defectivity on the wafer.
  • the defectivity in copper CMP is one of the most difficult challenges due to the softness of the copper film.
  • the defectivity from copper CMP is mainly scratch, sometime residue coming from the degraded polishing pads, mostly when a soft pad is used to buff out scratches.
  • the defectivity in copper CMP is a major concern because it causes yield lost, and some reliability concern.
  • Effort has been focused to reduce the copper CMP defectivity. Slurry filtration, including filtration in a re-circulation loop and point of use, is routinely used. However, the benefit of slurry filtration is limited.
  • the filter removes not only the unwanted large particles/agglomerates, it might also remove the primary abrasive particles suspended in the slurry, hence change the polish characterization. Also, over aggressive filtering of slurry causes the sheering of the slurry, introducing more defects. It also clogs the filter easier to make it much less manufacturable. Soft pads are also used to buff out the micro-scratches at the top surface. However, the soft pad has lower planarization efficiency, relative shorter life, and generates residue during its degradation.
  • the barrier is polished with improved defectivity during the CMP process with an aged barrier slurry.
  • the treatment of slurry used to polish copper barrier includes the steps of mixing the components of the slurry, aging the mixture for at least five days, and polishing the wafer with the aged slurry.
  • the mixed slurry is re-circulated in a slurry supply loop for a period of at least five days before used for polishing.
  • FIGS. 1 a - 1 d are cross-sectional schematics depicting general concept of the utilization of copper CMP.
  • FIG. 2 illustrates an improved method according to one embodiment of the present invention.
  • FIGS. 3 a - 3 b are the data obtained from aging study wherein FIG. 3 a is a plot of Sum of Defect (SOD) vs. age in days and FIG. 3 b is a chart of age, sample size, average defect count, and standard deviation.
  • SOD Sum of Defect
  • FIG. 4 illustrates copper defect improvement due to slurry aging, demonstrated in a manufacturing environment.
  • FIGS. 1 a - 1 d a schematic diagram demonstrating the concept of copper CMP is provided.
  • a wafer substrate with prior layer of interconnect ( 102 ) is provided.
  • the dielectric layer ( 106 ) is also provided.
  • the wafer is patterned and etched, trench ( 103 ), ( 104 ) is formed.
  • Barrier layer ( 110 ) and copper seed layer ( 112 ) is deposited.
  • the wafer is then subjected to electro-chemical plating, and copper ( 120 ) is deposited and fill the trench.
  • 1 c represents two typically filling characteristics, conformal filling with wide trench ( 103 ) and bottom-up filling with narrow trench ( 104 ).
  • CMP is then used to planarize the surface.
  • a slurry of high selectivity of copper to barrier is used in the removal of a majority or all redundant copper from the wafer surface.
  • the high selectivity of copper removal rate to barrier removal rate is designed so the polish can stop on the barrier layer. Hence, the non-uniformity form electro-chemical deposition will not be transferred into the final copper thickness variation.
  • the high selectivity slurry removes the copper layers, the copper layer disposed inside the trenches also may become polished with the high selectivity copper-polishing slurry.
  • This over-polishing of the copper layer disposed inside the trenches causes a depression of the copper layer, such that the copper layer becomes uneven, an effect which is known as dishing.
  • the resulting wafer is illustrated in FIG. 1 d .
  • a barrier slurry is used to polish off the barrier.
  • LSS low selectivity slurry
  • the barrier polish removal barrier, dielectric material, and copper at similar rates to improve process margin and reduce dishing.
  • buff step is also used to improved defectivity on the wafer.
  • a slurry composition that includes Electrapolish (Rodel electrapolish, blended from Rodel CUS1201A, Rodel CUS1201B, and DI water) is stable for about 1 week after mixing, but it is preferable to mix fresh every day. It is also generally believed that as a slurry ages, the contaminants (unwanted particle existing in the slurry) tend to grow and/or coalesce, causing substantial defectivity on the polished wafer. Contrary to that, applicants' have discovered that it is better for use after aging the slurry for at least about 5 to 6 days. It is also found that polishing performance is not sensitive to the degradation of oxidizer due to aging. The impact of oxidizer degradation can be further minimized by adding a stabilizing agent, which reduces the degradation rate of the oxidizer.
  • a stabilizing agent which reduces the degradation rate of the oxidizer.
  • a method of providing an improved slurry used for copper barrier CMP processing as illustrated in FIG. 2 comprises the Step 1 of mixing abrasive part and chemical part of said slurry and Step 2 of aging said abrasive part and chemical part that has been mixed for at least five days or the equivalent thereof before being used for copper barrier CMP processing.
  • the abrasive part is colloid silica (SiO2) and the chemical part contains a corrosion inhibitor such as BTA ((Benzotriazole).
  • BTA (Benzotriazole)
  • the slurry is Rodel electrapolish, blended from Rodel CUS1201A, Rodel CUS1201B, and DI (de-ionized ) water.
  • the slurry composition includes Electrapolish that is aged for at least six days. During this time the slurry may be mechanically stirred and re-circulated in a slurry supply loop. It is further recognized that the aging may be enhanced by an elevated temperature above normal room temperature, mechanical stirring and re-circulation.
  • FIGS. 3 a and 3 b demonstrate the improvement of defectivity by barrier slurry aging.
  • the electro-chemically plated blank copper wafers were used in the experiment to monitor the defectivity improvement.
  • the experiment conditions are listed below: Equipment: Applied Materials Mirra Polisher Polish pad: Rodel IC1010 on all three platens Monitor Wafers: 12,000 A copper Pilots, annealed at 400 C.
  • the blended slurry is aged by days as indicated before polishing.
  • Slurry Delivery Drawn by peristaltic pump from buckets behind tool, without point of use filter.
  • FIG. 4 is a demonstration of defectivity improvement by barrier slurry aging. Each data point in the graph represents a run to qualify the defectivity performance of the polisher.
  • the Vertical axis represents the sum of defects (SOD) on polished blank copper pilots measured by SP1 with 0.24 um sensitivity.
  • the horizontal axis is the date, when the qualification run was performed in the format of YYMMDD. The qualification run is typically performed daily.
  • the polishing condition used to collect data on FIG. 4 is similar to that outlined for FIGS. 3 a and 3 b except the slurry being delivered from loop, with a loop filter (Mykrolis, Planargard, CMP701E06) and POU filter (Mykrolis, Solaris, SLR0313E1).
  • the day tank is re-filled with slurry when it is dropped below a designated level.
  • the refilling slurry is blended before refill.
  • the arrow in the graph indicate the onset of the using of the aged slurry. A clear improvement of defect

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The copper CMP in a damascene structure composes of copper removal step, which removes majority or all of the redundant copper, and subsequent barrier removal step. The embodiment of the present invention includes the removal of the barrier layer with a slurry blended from abrasive silica particles, chemical materials, and de-ionized water. The blended slurry is aged for at least 4 days before use to achieve an improved defect performance.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates generally to the field of chemical mechanical polishing (CMP) process used to fabricate semiconductor devices. Specifically, the invention relates to the treatment of slurry used in CMP processes where copper is used as interconnecting material in the semiconductor devices. [0002]
  • 2. Description of Related Art [0003]
  • Over last decade, copper has gradually become the interconnecting material of choice for the integrated circuits in semiconductor industry due to its lower resistivity and better resistance to electro-migration. Due to the difficulty of etching copper using plasma, the method of damascene is typically used to create the copper interconnect on chip. When the trench and via are formed simultaneously on the wafer, the process is called dual damascene, and when the trench or via are formed separately on the wafer, the process is called single damascene. In a typical damascene structure, trench and/or via is etched into dielectric layer, barrier (typically Ta, TaN) and seed copper are deposited into the trench and/or via, and bulk copper is deposited by electroplating. Typically, the electro-chemically plated copper not only filled the desired area on the wafer (trench and/or via), it also over burden on the other area, leaving an un-planarized wafer surface. Chemical mechanical polishing (CMP) is used to remove the redundant copper and to planarize the wafer surface. Copper CMP is a multi-step process. During the 1[0004] st step, a slurry of high selectivity of copper to barrier is used in the removal of a majority or all redundant copper from the wafer surface. The high selectivity of copper removal rate to barrier removal rate is designed so the polish can stop on the barrier layer. Hence, the non-uniformity form electro-chemical deposition will not be transferred into the final copper thickness variation. However, after the high selectivity slurry removes the copper layers, the copper layer disposed inside the trenches also may become polished with the high selectivity copper-polishing slurry. This over-polishing of the copper layer disposed inside the trenches causes a depression of the copper layer, such that the copper layer becomes uneven, an effect which is known as dishing. In the 2nd step, a barrier slurry is used to polish off the barrier. In a low selectivity slurry (LSS) integration scheme, the barrier polish removes barrier material, dielectric material, and copper at similar rates to improve process margin and to reduce dishing. Sometime, a 3rd step, called buff step, is also used to improve defectivity on the wafer.
  • The defectivity in copper CMP is one of the most difficult challenges due to the softness of the copper film. The defectivity from copper CMP is mainly scratch, sometime residue coming from the degraded polishing pads, mostly when a soft pad is used to buff out scratches. The defectivity in copper CMP is a major concern because it causes yield lost, and some reliability concern. Effort has been focused to reduce the copper CMP defectivity. Slurry filtration, including filtration in a re-circulation loop and point of use, is routinely used. However, the benefit of slurry filtration is limited. If a very aggressive filter is chosen, the filter removes not only the unwanted large particles/agglomerates, it might also remove the primary abrasive particles suspended in the slurry, hence change the polish characterization. Also, over aggressive filtering of slurry causes the sheering of the slurry, introducing more defects. It also clogs the filter easier to make it much less manufacturable. Soft pads are also used to buff out the micro-scratches at the top surface. However, the soft pad has lower planarization efficiency, relative shorter life, and generates residue during its degradation. [0005]
  • Therefore, a need has arisen for processes that overcome these and other shortcomings of the related art. [0006]
    • SUMMARY OF THE INVENTION
  • In accordance with an embodiment of the present invention the barrier is polished with improved defectivity during the CMP process with an aged barrier slurry. [0007]
  • In an embodiment of the present invention, the treatment of slurry used to polish copper barrier includes the steps of mixing the components of the slurry, aging the mixture for at least five days, and polishing the wafer with the aged slurry. [0008]
  • In another embodiment of the present invention, the mixed slurry is re-circulated in a slurry supply loop for a period of at least five days before used for polishing. [0009]
  • Other features and advantages will be apparent to persons of ordinary skill in the art in view of the following detailed description of the invention and the accompanying drawings. [0010]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present invention, needs satisfied thereby, and the features and advantages thereof, reference now is made to the following descriptions taken in connection with the accompanying drawings. [0011]
  • FIGS. 1[0012] a-1 d are cross-sectional schematics depicting general concept of the utilization of copper CMP.
  • FIG. 2 illustrates an improved method according to one embodiment of the present invention. [0013]
  • FIGS. 3[0014] a-3 b are the data obtained from aging study wherein FIG. 3a is a plot of Sum of Defect (SOD) vs. age in days and FIG. 3b is a chart of age, sample size, average defect count, and standard deviation.
  • FIG. 4 illustrates copper defect improvement due to slurry aging, demonstrated in a manufacturing environment.[0015]
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Referring to FIGS. 1[0016] a-1 d, a schematic diagram demonstrating the concept of copper CMP is provided. For the sake of simplicity, only single damascene with trench is illustrated, although the same concept applies to the dual damascene structures. A wafer substrate with prior layer of interconnect (102) is provided. The dielectric layer (106) is also provided. The wafer is patterned and etched, trench (103), (104) is formed. Barrier layer (110) and copper seed layer (112) is deposited. The wafer is then subjected to electro-chemical plating, and copper (120) is deposited and fill the trench. The copper profile in FIG. 1c represents two typically filling characteristics, conformal filling with wide trench (103) and bottom-up filling with narrow trench (104). CMP is then used to planarize the surface. In the 1st step of CMP, a slurry of high selectivity of copper to barrier is used in the removal of a majority or all redundant copper from the wafer surface. The high selectivity of copper removal rate to barrier removal rate is designed so the polish can stop on the barrier layer. Hence, the non-uniformity form electro-chemical deposition will not be transferred into the final copper thickness variation. However, after the high selectivity slurry removes the copper layers, the copper layer disposed inside the trenches also may become polished with the high selectivity copper-polishing slurry. This over-polishing of the copper layer disposed inside the trenches causes a depression of the copper layer, such that the copper layer becomes uneven, an effect which is known as dishing. The resulting wafer is illustrated in FIG. 1d. In the 2nd step, a barrier slurry is used to polish off the barrier. In a low selectivity slurry (LSS) integration scheme, the barrier polish removal barrier, dielectric material, and copper at similar rates to improve process margin and reduce dishing. Sometime, a 3rd step, called buff step is also used to improved defectivity on the wafer.
  • In the prior art, it is suggested that a slurry composition that includes Electrapolish (Rodel electrapolish, blended from Rodel CUS1201A, Rodel CUS1201B, and DI water) is stable for about 1 week after mixing, but it is preferable to mix fresh every day. It is also generally believed that as a slurry ages, the contaminants (unwanted particle existing in the slurry) tend to grow and/or coalesce, causing substantial defectivity on the polished wafer. Contrary to that, applicants' have discovered that it is better for use after aging the slurry for at least about 5 to 6 days. It is also found that polishing performance is not sensitive to the degradation of oxidizer due to aging. The impact of oxidizer degradation can be further minimized by adding a stabilizing agent, which reduces the degradation rate of the oxidizer. [0017]
  • In accordance with one embodiment of the present invention a method of providing an improved slurry used for copper barrier CMP processing as illustrated in FIG. 2 comprises the [0018] Step 1 of mixing abrasive part and chemical part of said slurry and Step 2 of aging said abrasive part and chemical part that has been mixed for at least five days or the equivalent thereof before being used for copper barrier CMP processing. In one embodiment the abrasive part is colloid silica (SiO2) and the chemical part contains a corrosion inhibitor such as BTA ((Benzotriazole). In Step 3 of FIG. 2, the aged slurry is used for copper barrier polishing.
  • In accordance with a preferred embodiment of the present invention the slurry is Rodel electrapolish, blended from Rodel CUS1201A, Rodel CUS1201B, and DI (de-ionized ) water. In particular the slurry composition includes Electrapolish that is aged for at least six days. During this time the slurry may be mechanically stirred and re-circulated in a slurry supply loop. It is further recognized that the aging may be enhanced by an elevated temperature above normal room temperature, mechanical stirring and re-circulation. [0019]
  • FIGS. 3[0020] a and 3 b demonstrate the improvement of defectivity by barrier slurry aging. The electro-chemically plated blank copper wafers were used in the experiment to monitor the defectivity improvement. The experiment conditions are listed below:
    Equipment: Applied Materials Mirra Polisher
    Polish pad: Rodel IC1010 on all three platens
    Monitor Wafers: 12,000 A copper Pilots, annealed at 400 C.
    Defect Metrology: KLA-Tencor SP1
    Slurry: Rodel CUS1201 or electrapolish, blended by volume
    partA:partB:DIW = 33%:50%:17%. The blended
    slurry is aged by days as indicated before polishing.
    Slurry Delivery: Drawn by peristaltic pump from buckets behind
    tool, without point of use filter.
  • FIG. 4 is a demonstration of defectivity improvement by barrier slurry aging. Each data point in the graph represents a run to qualify the defectivity performance of the polisher. The Vertical axis represents the sum of defects (SOD) on polished blank copper pilots measured by SP1 with 0.24 um sensitivity. The horizontal axis is the date, when the qualification run was performed in the format of YYMMDD. The qualification run is typically performed daily. The polishing condition used to collect data on FIG. 4 is similar to that outlined for FIGS. 3[0021] a and 3 b except the slurry being delivered from loop, with a loop filter (Mykrolis, Planargard, CMP701E06) and POU filter (Mykrolis, Solaris, SLR0313E1). The day tank is re-filled with slurry when it is dropped below a designated level. The refilling slurry is blended before refill. The arrow in the graph indicate the onset of the using of the aged slurry. A clear improvement of defectivity can be observed.
  • While the invention has been described in connecting with preferred embodiments, it will be understood by those of ordinary skill in the art that other variations and modifications of the preferred embodiments described above may be made without departing from the scope of the invention. Other embodiments will be apparent to those of ordinary skill in the art from a consideration of the specification or practice of the invention disclosed herein. [0022]

Claims (18)

What I claim is:
1. A method of providing a slurry used for CMP process comprising the steps of:
mixing abrasive part and chemical part of said slurry and
aging said mixture at least five days or the equivalent before polishing a wafer using the aged slurry.
2. The method of claim 1, wherein said CMP process is copper CMP barrier removal.
3. The method of claim 1, wherein said abrasive part is silica (SiO2).
4. The method of claim 1, wherein said abrasive part is a colloid silica.
5. The method of claim 1, wherein said chemical part contains a corrosion inhibitor.
6. The method of claim 1, wherein said chemical part contains a corrosion inhibitor know as BTA (Benzotriazole).
7. The method of claim 1, wherein said slurry is Rodel electrapolish, blended from Rodel CUS1201A, Rodel CUS1201B, and DI water.
8. The method of claim 1, wherein said aged slurry composition includes Electrapolish. aged for at least six days.
9. The method of claim 1, wherein said equivalent aging process is by one or more accelerated steps of elevated temperature, mechanical stirring or re-circulation in a slurry supply loop.
10. A method of CMP processing a wafer using a slurry comprising the steps of:
mixing abrasive part and chemical part of said slurry;
aging said mixture at least five days or the equivalent thereof by an accelerating step; and
polishing the wafer using the aged slurry.
11. The method of claim 10, wherein said CMP process is copper CMP barrier removal.
12. The method of claim 10, wherein said abrasive part is silica (SiO2).
13. The method of claim 10, wherein said abrasive part is a colloid silica.
14. The method of claim 10, wherein said chemical part contains a corrosion inhibitor.
15. The method of claim 10, wherein said chemical part contains a corrosion inhibitor know as BTA (Benzotriazole).
16. The method of claim 10, wherein said slurry is Rodel electrapolish, blended from Rodel CUS1201A, Rodel CUS1201B, and DI water.
17. The method of claim 10, wherein said aged slurry composition includes Electrapolish. aged for at least six days.
18. The method of claim 10, wherein said equivalent aging process is by one or more accelerated steps of elevated temperature, mechanical stirring or re-circulation.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030190799A1 (en) * 2002-04-09 2003-10-09 Moriss Kung Pattern formation process for an integrated circuit substrate
US20060057945A1 (en) * 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US20060057944A1 (en) * 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US20070039246A1 (en) * 2005-08-17 2007-02-22 Zhendong Liu Method for preparing polishing slurry
US20140234649A1 (en) * 2011-09-30 2014-08-21 Robert Bosch Gmbh Layered composite of a substrate film and of a layer assembly comprising a sinterable layer made of at least one metal powder and a solder layer
CN112175523A (en) * 2019-07-03 2021-01-05 富士胶片电子材料美国有限公司 Polishing composition for reducing defects and method of using the same

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030190799A1 (en) * 2002-04-09 2003-10-09 Moriss Kung Pattern formation process for an integrated circuit substrate
US6881662B2 (en) * 2002-04-10 2005-04-19 Via Technologies, Inc. Pattern formation process for an integrated circuit substrate
US20060057945A1 (en) * 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US20060057944A1 (en) * 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US7025661B2 (en) 2004-09-16 2006-04-11 United Microelectronics Corp. Chemical mechanical polishing process
US20070039246A1 (en) * 2005-08-17 2007-02-22 Zhendong Liu Method for preparing polishing slurry
US20140234649A1 (en) * 2011-09-30 2014-08-21 Robert Bosch Gmbh Layered composite of a substrate film and of a layer assembly comprising a sinterable layer made of at least one metal powder and a solder layer
CN112175523A (en) * 2019-07-03 2021-01-05 富士胶片电子材料美国有限公司 Polishing composition for reducing defects and method of using the same
WO2021002880A1 (en) * 2019-07-03 2021-01-07 Fujifilm Electronic Materials U.S.A., Inc. Polishing compositions for reduced defectivity and methods of using the same
US10907074B2 (en) 2019-07-03 2021-02-02 Fujifilm Electronic Materials U.S.A., Inc. Polishing compositions for reduced defectivity and methods of using the same
US11407923B2 (en) 2019-07-03 2022-08-09 Fujifilm Electronic Materials U.S.A., Inc Polishing compositions for reduced defectivity and methods of using the same
JP2022551022A (en) * 2019-07-03 2022-12-07 フジフイルム エレクトロニック マテリアルズ ユー．エス．エー．， インコーポレイテッド Polishing composition for defect reduction and method of use thereof
US12065587B2 (en) 2019-07-03 2024-08-20 Fujifilm Electronic Materials U.S.A., Inc Polishing compositions for reduced defectivity and methods of using the same
JP7544755B2 (en) 2019-07-03 2024-09-03 フジフイルム エレクトロニック マテリアルズ ユー．エス．エー．， インコーポレイテッド Polishing composition for reducing defects and method of use thereof

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