JP2001257188A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of reducing the occurrence of dishing or erosion in a manufacturing step of a damascene wiring layer. SOLUTION: A metal layer is deposited on an insulating film on which a recessed pattern is formed. Then, after the insulating film is polished with slurry for metal polishing to expose the surface of the insulating film, the surface of the insulating film is polished by using slurry for polishing an insulating film. Subsequently, a protruded stepped part is polished in a process using the slurry for metal polishing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device capable of reducing dishing and erosion of a damascene wiring layer.

[0002]

2. Description of the Related Art The following is a technique studied by the present inventor, and its outline is as follows.

That is, in a method of manufacturing a wiring layer on a semiconductor substrate, a groove is formed in an insulating film made of a silicon oxide film, and a barrier metal layer made of a tantalum (Ta) film or the like and copper (Cu) are formed inside the groove. In some cases, a wiring layer (a wiring layer including an aspect of a wiring layer called a damascene wiring layer) formed by sequentially depositing a wiring metal film made of a film or the like from a lower layer is formed. .

In this case, the barrier metal layer and the wiring metal film formed on the surface thereof are formed by a CMP (Chemical Mecha).
A manufacturing process is used in which a wiring metal film in an unnecessary area and a barrier metal layer thereunder are polished using an nical polishing technique to form a patterned wiring layer as a damascene wiring layer. I have.

[0005] For example, "Semiconductor flattening CMP technology" issued by the Industrial Research Institute, published July 15, 1998,
Toshio Kasai and Takeo Nakagawa, CM of metal film in P26-P30
P is described.

[0006]

However, in a method of manufacturing a damascene wiring layer forming a multilayer wiring, a step is easily generated in an insulating film on the damascene wiring layer, and the step is difficult to be eliminated. During the formation of the layer, there are problems such as an electrical short-circuit caused by the polishing residue of the wiring metal film.

Further, in metal CMP, the polishing rate of the wiring metal film tends to be higher than the polishing rate of the barrier metal layer. If the over-polishing amount is increased to completely polish the barrier metal film formed outside the trench for the wiring layer, the polishing metal film having a high polishing rate is excessively polished. It has become clear that dishing occurs inside the groove and erosion occurs in which the insulating film around the damascene wiring layer is simultaneously polished.

An object of the present invention is to provide a technique capable of reducing dishing and erosion in a process of manufacturing a damascene wiring layer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after a metal film is deposited on an insulating film on which a concave pattern is formed, a CMP process using a metal polishing slurry and the insulating film polishing slurry are performed. The metal film is buried inside the concave pattern by using the CMP process used in combination. (2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, first, a metal film is deposited on an insulating film on which a concave pattern is formed, and then the surface of the metal film is subjected to a first CMP process using a slurry for metal polishing. After polishing to expose the surface of the insulating film, the surface of the insulating film is polished by a second CMP process using a slurry for insulating film polishing, and then a convex step is formed by a third CMP process using a slurry for metal polishing. It is to be polished. (3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, first, a metal film is deposited on an insulating film on which a concave pattern is formed, and then the surface of the metal film is subjected to a first CMP process using a slurry for metal polishing. After polishing to expose the surface of the insulating film, the surface of the insulating film is polished by a second CMP process using a slurry for insulating film polishing, and then a convex step is formed by a third CMP process using a slurry for metal polishing. The first to third CMP processes are continuously performed by changing a chemical solution contained in the slurry on a polishing pad containing abrasive grains. (4) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, first, a metal film is deposited on an insulating film on which a concave pattern is formed, and then the surface of the metal film is subjected to a first CMP process using a metal polishing slurry. After polishing to expose the surface of the insulating film, the surface of the insulating film is polished by a second CMP process using a slurry for insulating film polishing, and then a convex step is formed by a third CMP process using a slurry for metal polishing. The polishing is performed, and the first to third CMP processes are continuously performed by a CMP apparatus having a plurality of polishing plates. (5) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, first, a metal film is deposited on an insulating film on which a concave pattern is formed, and then the surface of the metal film is subjected to a first CMP process using a slurry for metal polishing. After polishing to expose the surface of the insulating film, the surface of the insulating film is polished by a second CMP process using a slurry for insulating film polishing, and then a convex step is formed by a third CMP process using a slurry for metal polishing. The polishing is performed, and the oxidizing agent concentration of the metal polishing slurry is changed during the first CMP process. (6) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device described above, wherein the metal film is formed by a laminated film of a barrier metal layer and a wiring metal film. Things.

According to the above means, the C on the surface of the metal film is
By using the CMP process in combination with the CMP process on the surface of the insulating film, dishing that easily occurs on the surface of the metal film inside the groove and erosion that easily occurs on the surface of the insulating film around the groove in which the metal film is embedded are generated. Is suppressed.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 7 are schematic sectional views showing steps of manufacturing a Cu wiring according to an embodiment of the present invention. In addition,
In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

First, as shown in FIG. 1, a first interlayer insulating film 2 is formed on a semiconductor substrate 1 on which a semiconductor element (not shown) is formed. Next, a second interlayer insulating film 3 having an etching selectivity with respect to the first interlayer insulating film 2 is formed on the first interlayer insulating film 2.

Next, a plurality of groove patterns 4 having a width of about 0.25 to 50 μm and a depth of about 0.4 μm are formed by etching the second interlayer insulating film 3 using the resist pattern as a mask. A barrier layer 5 having a thickness of about 0.05 μm, for example, a Ta film, a TaN film, a TiN film, etc., capable of preventing Cu diffusion is formed on the semiconductor substrate 1 by a sputtering method or a CVD (Chemical Vapor Deposit) method.
ion), followed by sputtering or CV
The Cu film 6 is deposited by the film formation by the method D or the continuous film formation of the sputtering method and the subsequent electrolytic plating method. The thickness of the Cu film 6 at the flat portion is, for example, 0.6 μm.
m.

Next, the semiconductor substrate 1 is subjected to a heat treatment,
The Cu atoms constituting the Cu film 6 are flowed into the groove pattern 4 by a flow phenomenon (reflow processing). The reflow process is performed, for example, by heating the semiconductor substrate 1 to about 450 ° C. in a hydrogen atmosphere for about 2 minutes.

Thereafter, the Cu film 6 and the barrier layer 5 outside the groove pattern 4 are polished and removed using the CMP apparatus CE shown in FIG.
By embedding the u film 6, the first Cu shown in FIG.
To form the wiring ML _1.

Next, a single wafer type CMP apparatus CE for processing one semiconductor wafer with one polishing platen used in the present embodiment will be briefly described with reference to FIG. In the figure,
7 is a semiconductor wafer, 8 is a pressure head, 9 is a polishing platen, 1
0 is a polishing pad, 11 is a dresser, 12 is a supply nozzle,
13 is a slurry (abrasive).

A semiconductor wafer 7 to be polished is held by a pressure head 8, and the surface of a metal film formed on the semiconductor wafer 7 is polished by a polishing pad 10 attached to a rotating polishing platen 9. Is done. The pressurizing head 8 can pressurize the semiconductor wafer 7 and has a rotation function. The surface of the polishing pad 10 is cut using a dresser 11 to regenerate its function. During polishing, a supply nozzle 12 installed above the polishing pad 10
A slurry 13 composed of a chemical solution in which fine particles (abrasive grains) are suspended is supplied. When changing the slurry,
After flowing the pure water, a slurry replacement operation is performed on the polishing pad 10.

By the way, as shown in FIG.
Dishing CMP occurs in a wide wiring structure width of the wiring ML _1. That is, at the stage of overpolishing for completely polishing and removing the barrier layer 5 formed outside the groove pattern 4, the polishing rate of the barrier layer 5 and the Cu film 6
When the wiring width is increased due to the difference from the polishing rate of
Is selectively polished so that the central portion becomes concave. This depends on the hardness of the polishing pad or the polishing pressure, but also on the distance from the end of the second interlayer insulating film 3, and the farther the distance, the greater the dishing depth ΔX.

According to the study by the present inventors, it was found that Cu
The polishing rate ratio of the barrier layer 5 such as a Ta film to the film 6 is about 1/12, and the polishing rate ratio of the second interlayer insulating film 3 such as a silicon oxide film to the Cu film 6 is about 1/1.
It is about 00. Therefore, in this case, in order to completely remove the barrier layer 5 by polishing, it is necessary to polish about 0.6 μm in terms of a Cu film. For this reason, while the barrier layer 5 is being polished and removed, the polishing of the Cu film 6 inside the groove pattern 4 proceeds, and dishing of about 0.05 to 0.2 μm occurs depending on the wiring width. If overpolishing of 20% or more is performed, the second interlayer insulating film 3 around the _first Cu wiring ML1 is simultaneously polished, and erosion of about 0.05 to 0.1 μm may occur. .

Next, as shown in FIG. 4, a third interlayer insulating film 14 made of, for example, a silicon oxide film having a thickness of about 1.0 μm is formed on the semiconductor substrate 1. First
The influence of dishing generated in Cu wiring ML ₁ of concave step 15 is generated on the surface of the first Cu interconnection ML ₁ on the third interlayer insulating film 14.

Next, as shown in FIG. 5, a plurality of groove patterns 16 are formed by etching the third interlayer insulating film 14 using the resist pattern as a mask, and then, as shown in FIG. 1, a barrier layer 17 capable of preventing the diffusion of Cu, for example, a Ta film, TaN
A film, a TiN film or the like is deposited by a sputtering method or a CVD method, and then a Cu film 18 is deposited by a sputtering method or a CVD method, or a continuous film formation of a sputtering method and a subsequent electrolytic plating method.

Next, a reflow process is performed on the semiconductor substrate 1 to flow the Cu film 18 into the groove pattern 16.
The reflow process is performed, for example, by heating the semiconductor substrate 1 to about 450 ° C. in a hydrogen atmosphere for about 2 minutes.

Next, using a slurry for metal polishing in the CMP apparatus CE, as shown in FIG.
6, the barrier layer 17 and the Cu film 18 are buried in the groove pattern 16 by polishing and removing the Cu film 18 outside the groove pattern 16 and then polishing and removing the barrier layer 17 outside the groove pattern 16 as shown in FIG. (First CMP process). Here, in a region where a plurality of groove patterns 16 are formed in the concave steps 15 generated in the third interlayer insulating film 14, the barrier layer 17 is polished on the surface of the third interlayer insulating film 14 between the groove patterns 16. There are 19 remaining.

In the first CMP treatment, an oxidizing agent, for example, a hydrogen peroxide solution (H
Concentrations such as ₂ O ₂ ) or potassium iodate (KIO ₃ ) may be varied during polishing removal, thereby providing the first CM
The dishing of the Cu film 18 in the P processing can be reduced.

Next, the surface of the third interlayer insulating film 14 is polished and removed by using a slurry for polishing an alkaline oxide film having a pH of about 10 such as a fumed silica slurry or a colloidal silica slurry in the CMP apparatus CE. (Second CMP process). The polishing amount is, for example, about 0.05 μ.
m. As a result, as shown in FIG. 9, the Cu film 18 and the barrier layer 17 embedded in the groove pattern 16 are not polished, and a convex step 20 is generated.

Subsequently, the pH value of pH 2
Using a slurry for polishing about 4 acidic or neutral metals, for example, an alumina-based slurry, the convex step 20 is used.
Perform polishing removal until no (second 3CMP processing), as shown in FIG. 10, a second Cu wiring ML _2.

In the present embodiment, the first to third CMP processes described with reference to FIGS. 7 to 10 are performed by a CMP apparatus CE having one polishing platen 9 shown in FIG.
However, the first to third CMP processes may be continuously performed using a CMP apparatus having a plurality of polishing plates.

The first to third CMP processes described in the present embodiment with reference to FIGS. 7 to 10 are performed using the slurry 13 composed of a chemical solution in which abrasive grains are suspended. The first to third CMP processes may be performed by changing the chemical solution of the slurry on a polishing pad having abrasive grains fixed on the surface.

In this embodiment, the third interlayer insulating film 14 above the _first Cu wiring ML1 is made of a silicon oxide film. However, the third interlayer insulating film 14 is made of a silicon nitride film and a silicon oxide film. It may be constituted by a film.

[0032] Thus, according to the present embodiment, the dishing occurs in the first Cu wiring ML ₁ of the lower layer, the third interlayer insulating film deposited on the first Cu interconnection ML ₁ 14 Even if a step occurs in the surface of the Cu film 18,
By using the CMP process together with the CMP process on the surface of the third interlayer insulating film 14, the second Cu wiring ML _{2 in the} upper layer is formed.
Is more likely to occur on the surface of the third interlayer insulating film 14 around the _second Cu wiring ML2 and about one-half of the conventional technology.
It can be suppressed to about 0. Thereby, the second C
Cu film 18 or barrier layer 17 during formation of u wiring ML ₂
It is possible to avoid a problem such as an electrical short circuit caused by the polishing residue.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0034]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the CMP of the surface of the insulating film is used in combination with the CMP of the surface of the metal film.
Dishing that easily occurs on the surface of the damascene wiring layer and erosion that easily occurs on the surface of the insulating film around the damascene wiring layer can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a damascene Cu wiring layer according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a CMP apparatus used in a process of manufacturing a damascene Cu wiring layer according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the damascene Cu wiring layer according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the damascene Cu wiring layer according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the damascene Cu wiring layer according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the damascene Cu wiring layer according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the damascene Cu wiring layer according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the damascene Cu wiring layer according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the damascene Cu wiring layer according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the damascene Cu wiring layer according to one embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 first interlayer insulating film 3 second interlayer insulating film 4 groove pattern 5 barrier layer 6 Cu film 7 semiconductor wafer 8 pressure head 9 polishing platen 10 polishing pad 11 dresser 12 supply nozzle 13 slurry 14 third Interlayer insulating film 15 concave step 16 groove pattern 17 barrier layer 18 Cu film 19 polished residue 20 step ML ₁ first Cu wiring ML ₂ second Cu wiring CE CMP apparatus ΔX dishing depth

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (5)

[Claims] After a metal film is deposited on an insulating film on which a concave pattern has been formed, CMP using a metal polishing slurry is performed.
A method of manufacturing a semiconductor integrated circuit device, comprising: embedding the metal film inside the concave pattern by using a combination of a treatment and a CMP treatment using an insulating film polishing slurry. 2. A process of: (a) depositing a metal film on an insulating film on which a concave pattern is formed; and (b) polishing the surface of the metal film by a CMP process using a slurry for metal polishing. A step of exposing the surface of the insulating film; (c) a step of polishing the surface of the insulating film by a CMP process using a slurry for polishing an insulating film; and (d) a CMP process using a slurry for metal polishing. Polishing the protruding step portion by using the method. 3. A process of: (a) depositing a metal film on the insulating film on which the concave pattern is formed; and (b) polishing the surface of the metal film by a CMP process using a slurry for metal polishing. A step of exposing the surface of the insulating film; (c) a step of polishing the surface of the insulating film by a CMP process using a slurry for polishing an insulating film; and (d) a CMP process using a slurry for metal polishing. And polishing the convex step portion with the step (b) .- (d) .The step is performed by changing the chemical solution contained in the slurry on the polishing pad containing the abrasive grains. A method for manufacturing a semiconductor integrated circuit device. 4. A step of: (a) depositing a metal film on the insulating film on which the concave pattern is formed; and (b) polishing the surface of the metal film by CMP using a slurry for metal polishing. A step of exposing the surface of the insulating film; (c) a step of polishing the surface of the insulating film by a CMP process using a slurry for polishing an insulating film; and (d) a CMP process using a slurry for metal polishing. And polishing the convex step portion with the step (b) .- (d).
A method of manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is continuously processed by the device. 5. A step of: (a) depositing a metal film on an insulating film having a concave pattern formed thereon; and (b) polishing the surface of the metal film by CMP using a metal polishing slurry, A step of exposing the surface of the insulating film; (c) a step of polishing the surface of the insulating film by a CMP process using a slurry for polishing an insulating film; and (d) a CMP process using a slurry for metal polishing. And polishing the convex step portion by changing the oxidizing agent concentration of the metal polishing slurry during the CMP process of the step (b).