JP2001345324A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time required for flattening thick film. SOLUTION: This method for manufacturing a semiconductor device includes a process for forming a hole 31 at an Si wafer 10 and an interlayer insulating film 13, a process for forming Cu films 33 and 34 so that the inside of the hole can be buried, a process for performing wet etching to the Cu films 33 and 34, and a process for eliminating the Cu films 33 and 34 other than the hole 31 by performing the chemical mechanical polishing to the Cu films 33 and 34 and flattening the surface of the Cu films 33 and 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device for flattening a film formed on a substrate to be processed.

[0002]

2. Description of the Related Art With miniaturization of design rules, attention has been paid to Cu having a small specific resistance as an amount of wiring material.

When forming a Cu thick film wiring and a contact plug of a semiconductor device by a damascene process, first, a barrier metal for suppressing the diffusion of Cu is formed on the surface of the via plug, and then a thin Cu film is formed by a sputtering method. After that, the via plug is formed so as to be entirely embedded with the Cu plating film, and then the plug and the wiring portion are removed using chemical mechanical polishing.
The u film was removed.

In this case, in chemical mechanical polishing, 1 μm / m
Since a polishing rate of about in can be obtained, there is a problem that throughput is deteriorated. In particular, when the thickness of the Cu film is 10 μm or more, it is necessary to dress the polishing cloth several times in the middle to prevent clogging of the pad.
For this reason, there is a problem that the throughput is further deteriorated when the thickness is 10 μm or more.

[0005]

As described above, since the polishing rate of the chemical mechanical polishing is low, there is a problem that the throughput deteriorates particularly when the chemical mechanical polishing is performed on a thick film. .

An object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce the time required for a step of flattening a thick film.

[0007]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object. (1) In the method for manufacturing a semiconductor device according to the present invention, a step of depositing a film on a substrate to be processed including a semiconductor substrate, and etching and chemical mechanical polishing are sequentially performed on the film to form the film. Flattening the surface of the substrate.

(2) The method of manufacturing a semiconductor device according to the present invention
Forming a hole in a substrate to be processed including a semiconductor substrate; depositing a film on the substrate to be processed so as to fill the hole; and etching and chemically mechanically polishing the film. And sequentially removing the film other than the holes while flattening the surface of the film.

Preferred embodiments of the present invention are described below.
As the etching method, wet etching using a chemical solution is used. The metal film is made of Cu or Cu
It must be composed of a material whose main component is In the step of depositing a metal film so that the inside of the hole is buried, the average film thickness of the metal film on the hole and its periphery from the plane of the substrate to be processed is an average thickness of the metal film other than the hole and its periphery. Thicker than film thickness. Before etching the metal film, a protective film for protecting the metal film from the etching is formed on at least the metal film immediately above the hole.

[Operation] The present invention has the following operation and effects by the above configuration. Before performing chemical mechanical polishing on the film, the surface of the film is retreated by etching with a high removal rate compared to the removal rate of chemical mechanical polishing, and the film thickness is reduced by chemical etching. By performing mechanical polishing, it is possible to reduce the time required for the step of flattening a thick film, as compared with the case where only chemical mechanical polishing is performed for planarization.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a process sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1A, after an element isolation insulating film 11 and an element 12 such as a MOS transistor are formed on a Si wafer 10, a first interlayer insulating film 13 for protecting the element 12 is formed. Next, as shown in FIG.
Then, a plug 14 connected to the element 12 is formed. And
After forming a resist pattern having a window in a region where a through plug is to be formed, the interlayer insulating film 13 and the Si wafer 10 are etched using the resist pattern as a mask to form a hole having a depth of 65 μm and a total aperture of 40 μm in the Si wafer 10. I do. After removing the resist pattern, a silicon oxide film is formed by plasma enhanced chemical vapor deposition or the like, and an insulating film 15 is formed on the side surface of the hole. And in this hole Cu
Is formed by burying.

After forming this hole, the through plug 1
Steps up to the step of burying 6 will be described in detail with reference to FIG. FIG. 2 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG.
After forming a resist pattern having a window in a region where a through plug is to be formed on the insulating film 3, the insulating film 13 and the Si wafer 10 are etched using the resist pattern as a mask,
Hole 3 having a depth of 65 μm and an opening diameter of 40 μm in the wafer 10
Form one. After forming the insulating film 15 on the surface of the hole 31, a TaN film 32 and a Cu film 33 are formed by a sputtering method of 1 μm or more. The TaN film 32 also serves as both a Cu diffusion preventing layer and an adhesion layer, and any material other than the TaN film may be used as long as it satisfies this purpose.

Next, as shown in FIG. 2B, a 20 μm-thick Cu plating film 34 is formed on the Cu sputtering film 33 without any voids in the holes 31 by electrolytic plating. It should be noted that the Cu plating film 34 is formed so as to swell up to several μm immediately above and around the hole 31. This is the ratio of carrier and leveler contained in the electrolytic plating solution,
By increasing the proportion of the carrier, the Cu plating film 34 can be raised immediately above and around the through plug.

Next, the Cu films 33 and 34 are etched using an etching solution having a mixing ratio of nitric acid: water = 1: 2 to 10 using a spin etching apparatus shown in FIG. Since the Cu plating film 34 on the upper portion of the hole 31 and its peripheral portion is raised, even when the Cu plating film 34 is wet-etched, the material in the hole 31 is sufficiently protected.

Since nitric acid etches Cu at a supply rate at room temperature, in order to perform uniform etching, an etching solution is uniformly supplied to a substrate to be processed by a spin etching apparatus, or a reaction is performed by lowering the temperature. It is effective to perform etching in a rate-determined state.

Further, when the TaN film 32 is exposed,
Since the etching rate of the Cu film around the exposed portion becomes extremely high, it is necessary to lower the concentration of the chemical solution and improve the uniformity of the etching. It is also effective to increase the number of rotations of the stage during etching to improve uniformity. Alternatively, it goes without saying that the uniformity of etching can be improved by changing the method of supplying the chemical solution into a shower shape or changing the nozzle supply position.

Next, as shown in FIG.
Using the film 32 as an etching stopper, the Cu films 33, 3
4 is subjected to chemical mechanical polishing. By using the TaN film as a stopper for chemical mechanical polishing of the Cu film, the raised Cu plating film on the plug and its peripheral portion is planarized.

Then, as shown in FIG. 2E, the TaN film 32 remaining on the insulating film 15 is removed by chemical mechanical polishing, and the through plug 16 is buried in the hole 31.

As described above, wet etching and chemical mechanical polishing are sequentially performed on the Cu film to planarize the thick Cu film and bury the Cu film in the holes. This can be performed in a much shorter time than when the Cu film is flattened.

After the through plug 16 containing Cu as a main component is buried in the hole 31 through the above-described steps, the wiring 17 is formed on the plug and the element region as shown in FIG. I do. Then, a plug 19 connected to the interlayer insulating film 18 and the wiring 17 is formed. After forming the wiring 20, the interlayer insulating film 21 and the plug 22 on the interlayer insulating film 18, the pad 23 and the protective film 2 made of polyimide are formed.
4 is formed.

Next, as shown in FIG. 1D, grinding and RIE are performed on the back side of the Si wafer 10 to expose the through plug 16.

Then, as shown in FIG. 3, a three-dimensional LSI is formed by connecting through plugs of chips 41 obtained by cutting out the wafer on which the above-described steps are formed with barrier metals 42 and solders 43. In FIG. 3, the information is a circuit formation surface.

The present invention is not limited to the above embodiment. For example, although Cu is used as the metal layer, the same effect can be obtained as long as the film can be formed by plating with another metal, for example, Ni, Pd, Ru, or the like, and can be polished by the chemical mechanical polishing method. .

Further, it is not necessary to bury the entire inside of the through plug with a conductive material, and there is no problem even if the through plug is filled with an insulating film.

[Second Embodiment] In the present embodiment, the first
A method of embedding a wiring member, which is different from the embodiment, will be described. In this embodiment, after a hole is formed in the metal film immediately above the plug, a protective film for protecting the metal film from etching is formed in this hole, and then the etching and chemical mechanical polishing are sequentially performed on the metal film. .

In this embodiment, only the process of forming a through plug will be described. FIG. 4 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention. First, as shown in FIG. 4A, the Si wafer 10 and the interlayer insulating film 13 are formed in the same manner as in the process described with reference to FIG.
After forming a hole 31 in the insulating film 15, the TaN film 3
2. A Cu sputter film 33 is formed.

Next, as shown in FIG. 4B, a Cu plating film 54 having a thickness of 20 μm is formed on the Cu sputtering film 33 without any voids in the holes 31 by electrolytic plating. The surface of the Cu plating film 54 on the hole 31 forms a concave portion 55 lower than its periphery. This is because the concave portion 55 can be formed in the Cu plating film 54 immediately above the hole 31 by increasing the ratio of the leveler among the carrier and the leveler included in the electrolytic plating solution. In addition,
It is preferable that the height of the side wall of the concave portion 55 be 100 nm or more.

Next, as shown in FIG. 4C, after forming a Cu oxide or a material containing a Cu oxide on the surface of the Cu plating film 54, a chemical mechanical polishing is performed, so that the protective film 56 is buried.

Next, as shown in FIG. 4D, Cu etching is performed using an etching solution containing glycine and aqueous hydrogen peroxide.
The films 33 and 54 are etched. Cu oxide or C
When the thickness of the protective film 56 containing u oxide is 100 nm or more, glycine has no ability to remove the protective film 56,
Since etching does not proceed, the Cu oxide functions as a mask material. Therefore, the height of the side wall of the concave portion 55 is 1
It is preferable that the thickness be 00 nm or more.

Glycine + hydrogen peroxide aqueous solution is 7
By heating to about 0 ° C., the etching rate for Cu increases and Cu can be etched at 2 to 10 μm / min. After this etching step, Cu
When moving to the chemical mechanical polishing step of the film, it is desirable that the processing is finished in a time that does not require dressing of the chemical mechanical polishing pad during the chemical mechanical polishing processing, and the remaining film thickness of the Cu film after etching. Is preferably about 1 μm or less.

Next, as shown in FIG.
Using the film 32 as an etching stopper, the Cu films 33, 5
4 is subjected to chemical mechanical polishing. Then, the insulating film 15
The TaN film 32 remaining on the upper surface is removed by chemical mechanical polishing, the chip through plug is flattened, and a through plug is formed in the hole (FIG. 2E).

In this embodiment, a chemical solution containing nitric acid, glycine + hydrogen peroxide solution is used as the Cu etching solution, but the present invention is not limited to this, and hydrochloric acid + hydrogen peroxide solution, sulfuric acid + peroxide solution is used. Cu can be etched even with a chemical solution containing hydrogen water. Needless to say, the Cu film can be etched with other chemicals, and potassium persulfate,
It was feasible with ferrous nitrate and cerium ammonium nitrate. In particular, due to the problem of chemical treatment after etching the Cu film, a chemical such as nitric acid + hydrogen peroxide solution capable of recovering Cu is effective only by cooling the etched chemical such that copper sulfate is deposited. . When using a Cu recovery method that does not change the composition of the chemical itself, such as cooling, the chemical can be circulated by adding a stabilizer to the etchant,
The consumption of the chemical can be drastically reduced.

In each of the above embodiments, the present invention is applied to a method of processing a chip through plug. However, the present invention is not limited to this, and is applicable to the formation of a thick film embedded wiring, a plug, and the like. Needless to say.

In the present invention, it is essential that wet etching and chemical mechanical polishing are sequentially performed, and the number of repetitions is not limited, and may be repeated several times.

It should be noted that the present invention is not limited to the above-described embodiments, and can be variously modified in the practical stage without departing from the scope of the invention.

For example, in each of the above embodiments, a Cu film is used as a film for flattening. However, the present invention is not limited to the Cu film.
Other metal films may be used. Further, the present invention can be applied to an insulating film such as an interlayer insulating film.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0039]

As described above, according to the present invention, before chemical mechanical polishing is performed on a film, the surface of the film is etched by a removal rate higher than that of chemical mechanical polishing. By retreating the film and making the film thinner and performing the chemical mechanical polishing, the time required for the step of flattening the thick film can be shortened as compared with the case where only the chemical mechanical polishing is planarized. it can.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a sectional view showing the configuration of the semiconductor device according to the first embodiment;

FIG. 4 is a process sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Wafer 11 ... Element isolation insulating film 12 ... Element 13 ... First interlayer insulating film 14 ... Plug 15 ... Insulating film 15. Ta ... silicon oxide film 16 ... through plug 17 ... wiring 18 ... interlayer insulating film 19 ... plug 20 ... wiring 21 ... interlayer insulating film 22 ... plug 23 ... pad 24 ... protective film 31 ... hole 32 ... TaN film 33 ... Cu sputter film 34: Cu plating film 41: Chip 42: Barrier metal 43: Solder 54: Cu plating film 55: Depression 56: Protective film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Nobuo Hayasaka, Inventor No. 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in Toshiba Yokohama Office (reference) 5F033 JJ07 JJ11 JJ21 MM30 PP15 PP27 QQ08 QQ09 QQ19 QQ48 QQ49 XX01 5F043 AA26 BB18 DD12 DD16 EE07 EE08 FF07 GG02

Claims (7)

[Claims] 1. A step of depositing a film on a substrate to be processed including a semiconductor substrate, and a step of sequentially performing etching and chemical mechanical polishing on the film to flatten the surface of the film. And a method of manufacturing a semiconductor device. 2. A step of forming a hole in a substrate to be processed including a semiconductor substrate, a step of depositing a film on the substrate to be processed so as to fill the hole, and etching the film. And removing the film other than the holes while flattening the surface of the film by sequentially performing the chemical mechanical polishing and chemical mechanical polishing. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the etching is performed by wet etching using a chemical solution. 4. The method according to claim 1, wherein said film is made of a metal material. 5. The method according to claim 4, wherein the metal material contains Cu or Cu as a main component. 6. The step of depositing a film so that the inside of the hole is buried, wherein the average film thickness of the metal film on the hole and its periphery from the plane of the substrate to be processed is other than that of the hole and its periphery. 3. The method according to claim 2, wherein the thickness of the semiconductor device is larger than an average thickness of the film. 7. The semiconductor according to claim 2, wherein a protective film for protecting the film from the etching is formed at least on the film immediately above the hole before etching the film. Device manufacturing method.