CN109887880B - Semiconductor connection structure and manufacturing method thereof - Google Patents
Semiconductor connection structure and manufacturing method thereof Download PDFInfo
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- CN109887880B CN109887880B CN201910007779.2A CN201910007779A CN109887880B CN 109887880 B CN109887880 B CN 109887880B CN 201910007779 A CN201910007779 A CN 201910007779A CN 109887880 B CN109887880 B CN 109887880B
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Abstract
The invention discloses a semiconductor connecting structure and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a first groove in the first dielectric layer at a position corresponding to the metal wire; wherein the depth of the first groove is not more than the thickness of the first dielectric layer; depositing at least one second dielectric layer on the top of the first dielectric layer, and forming second grooves based on the appearance of the first grooves; and etching the at least one second dielectric layer, the first dielectric layer and the third dielectric layer below the second groove to form a hole exposing the metal wire, wherein the metal wire is positioned below the third dielectric layer. The manufacturing method of the semiconductor connection structure provided by the embodiment can enable the at least one second dielectric layer to be used as a hard mask layer to etch the hole, and an additional hard mask layer is not required to be introduced during etching the hole, so that the process cost is reduced, and the preparation efficiency is improved.
Description
Technical Field
The embodiment of the invention relates to the field of integrated circuits, in particular to a semiconductor connecting structure and a manufacturing method thereof.
Background
In the field of integrated circuits, connection between metals is realized through a semiconductor connection structure, and further circuit interconnection is realized. With the continuous increase of the requirement on the integration level, the height of the semiconductor connecting structure is higher and higher, so that the requirement of the etching process of the semiconductor connecting structure on the etching uniformity is higher. Therefore, a method for improving the etching uniformity of the semiconductor connection structure, improving the quality of the semiconductor connection structure, and further improving the product quality is needed.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor connection structure and a method for fabricating the same.
A first aspect of an embodiment of the present invention provides a method for manufacturing a semiconductor connection structure, including:
forming a first groove in the first dielectric layer at a position corresponding to the metal wire; wherein the depth of the first groove is not more than the thickness of the first dielectric layer;
depositing at least one second dielectric layer on the top of the first dielectric layer, and forming second grooves based on the appearance of the first grooves;
and etching the at least one second dielectric layer, the first dielectric layer and the third dielectric layer below the second groove to form a hole exposing the metal wire, wherein the metal wire is positioned below the third dielectric layer.
According to an embodiment, the method comprises:
depositing metal in the hole to form a metal pillar that contacts the metal line through the at least one second dielectric layer, the first dielectric layer, and the third dielectric layer;
and carrying out planarization treatment, wherein after planarization, the upper surface of the metal column is flush with the top of the at least one second dielectric layer.
According to an embodiment, the step of depositing at least one second dielectric layer on top of the first dielectric layer and forming the second recess based on the topography of the first recess comprises:
depositing a first second dielectric layer on the top of the first dielectric layer, and forming a third groove based on the appearance of the first groove, wherein the sum of the width of the bottom of the third groove and the thickness of the first second dielectric layer on the top of the first groove is not less than the width of the hole at the top of the third groove;
and depositing and forming a second dielectric layer on the top of the first second dielectric layer, and forming the second groove based on the appearance of the third groove.
According to one embodiment, the first second dielectric layer and the second dielectric layer are made of different compositions.
In accordance with one embodiment of the present invention,
the first dielectric layer comprises an oxide;
the third dielectric layer comprises a nitride.
In accordance with one embodiment of the present invention,
the composition of the first second dielectric layer comprises nitride or carbonitride;
the second dielectric layer comprises an oxide.
In accordance with one embodiment of the present invention,
the width of the bottom of the first groove is larger than the line width of the metal line;
and/or the presence of a gas in the gas,
the width of the metal column is smaller than that of the bottom of the first groove;
and/or the presence of a gas in the gas,
the width of the metal column is larger than that of the bottom of the second groove.
A second aspect of an embodiment of the present invention provides a semiconductor connection structure, including:
a first dielectric layer located on the substrate;
at least one second dielectric layer located above the first dielectric layer;
the third dielectric layer is positioned below the first dielectric layer;
the metal wire is positioned below the third dielectric layer;
the metal column sequentially penetrates through the at least one second dielectric layer, the first dielectric layer and the third dielectric layer from top to bottom to be in contact with the metal line;
and the depth of the metal column in contact with the at least one second dielectric layer is greater than the thickness of the at least one second dielectric layer in the region outside the position of the metal column.
According to one embodiment, the width of the bottom of the metal pillar is not greater than the line width of the metal line.
In accordance with one embodiment of the present invention,
the width of the bottom of the first groove is larger than the line width of the metal line;
and/or the presence of a gas in the gas,
the width of the metal column is smaller than that of the bottom of the first groove;
and/or the presence of a gas in the gas,
the width of the metal column is larger than that of the bottom of the second groove.
According to the semiconductor connecting structure and the manufacturing method thereof provided by the invention, the first groove is formed in the first medium layer, the at least one second medium layer is deposited in the first groove, the second groove is formed based on the first groove, and then the at least one second medium layer, the first medium layer and the third medium layer which are positioned below the second groove are etched to form the hole exposing the metal wire, so that the opening size of the interface between the second medium layer and the first medium layer on the side wall of the hole is reduced, the influence on the appearance of the side wall of the hole due to the excessive etching of the first medium layer during the etching of the hole is favorably reduced, the etching uniformity at the interface is improved, the side wall of the hole is smooth, the filling quality of the hole is improved, and the product quality is improved. Meanwhile, the manufacturing method of the semiconductor connection structure provided by the embodiment can enable the at least one second dielectric layer to be used as a hard mask layer for etching the hole, and an additional hard mask layer is not required to be introduced during etching the hole, so that the process cost is reduced, and the preparation efficiency is improved.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor connection structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram after a second dielectric layer is formed according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart illustrating a method for fabricating a semiconductor interconnect structure according to another embodiment of the present invention;
FIG. 4 is a schematic view of a semiconductor interconnect structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a process for fabricating a dual damascene via connection structure;
FIG. 6 is a schematic view of a semiconductor substrate with a dual damascene via connection structure;
FIG. 7 is a schematic diagram of a dual damascene via connection structure after a first via is formed;
FIG. 8 is a schematic diagram of a dual damascene via connection structure after a second via is formed;
FIG. 9 is a schematic diagram of a dual damascene via connection structure after metal filling;
FIG. 10 is a schematic structural diagram of a dual damascene via connection structure;
FIG. 11 is a schematic view illustrating a process for fabricating a semiconductor interconnect structure according to an embodiment of the present invention;
FIG. 12 is a schematic view of a semiconductor substrate structure according to an embodiment of the present invention;
fig. 13 is a schematic structural view of a semiconductor connection structure after a first groove is formed in the semiconductor connection structure according to an embodiment of the present invention;
fig. 14 is a schematic structural view illustrating a semiconductor connection structure after a second groove is formed therein according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram illustrating a semiconductor connection structure after holes are formed therein according to an embodiment of the present invention;
fig. 16 is a schematic structural view of a semiconductor connection structure after metal filling according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of a semiconductor connection structure according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention will be further elaborated with reference to the drawings and the embodiments. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Unless specifically stated or otherwise indicated, the terms "first," "second," "third," and the like in the present disclosure are used for distinguishing between various components, elements, steps, and the like, and are not used to indicate a logical relationship or a sequential relationship between various components, elements, steps, and the like.
Herein, the term "a over/under B" is meant to include the case where A, B are both in contact with each other, one over/under the other, or the case where A, B is also interposed between the two with other components, one over/under the other without contact.
As shown in fig. 1, an embodiment of the invention provides a method for manufacturing a semiconductor connection structure, including:
step S10: forming a first groove in the first dielectric layer at a position corresponding to the metal wire; wherein the depth of the first groove is not more than the thickness of the first dielectric layer;
step S20: depositing at least one second dielectric layer on the top of the first dielectric layer, and forming second grooves based on the appearance of the first grooves;
step S30: and etching the at least one second dielectric layer, the first dielectric layer and the third dielectric layer below the second groove to form a hole exposing the metal wire, wherein the metal wire is positioned below the third dielectric layer.
The first dielectric layer and the second dielectric layer may be layers formed of different compositions (or dielectrics). The at least one second dielectric layer may include: one or more dielectric layers, in this embodiment "second" of the "second dielectric layers" are not specified, but merely describe the dielectric layer that is located over the first dielectric layer. For example, the number of the second dielectric layers can be 1, 2 or 3.
As shown in fig. 2, at least one second dielectric layer 34 is located above the first dielectric layer 13, the third dielectric layer 12 is located below the first dielectric layer 13, and the metal line 10 is further located below the third dielectric layer 12, so that the following steps are performed from top to bottom: at least one second dielectric layer, a first dielectric layer, a third dielectric layer and a metal line.
In some embodiments, the metal line 10 is disposed in a fourth dielectric layer 11, and the fourth dielectric layer 11 may wrap the metal line 10 to protect the metal line 10.
In some embodiments, the semiconductor connection structure may be used for bonding of two wafers. For example, the semiconductor connection structure is fabricated on a first wafer, the semiconductor connection structure is also fabricated on a second wafer, then the hole on the first wafer is aligned with the hole on the second wafer, the at least one second dielectric layer on the first wafer is aligned with the at least one second dielectric layer on the second wafer, so that the side of the first wafer having the semiconductor connection structure is bonded with the side of the second wafer having the semiconductor connection structure, and the metal wire on the first wafer is connected with the second metal wire, thereby realizing the bonding of the first wafer and the second wafer.
In some embodiments, the semiconductor connection structure may also be used for connection of lower level metal lines to upper level metal lines in a wafer. For example, the semiconductor connection structure is prepared, the semiconductor connection structure is connected with the lower metal line, and then an upper metal line is deposited above the semiconductor connection structure, so that the lower metal line is connected with the upper metal line.
In an embodiment of the present invention, the step S10 may include:
forming a mask layer on the top of the first dielectric layer, coating photoresist on the top of the mask layer, and carrying out patterning processing on the photoresist and the mask layer through a photoetching process to transfer the pattern on the mask plate to the mask layer;
and etching the first dielectric layer by taking the mask layer subjected to the patterning treatment as a mask to form a first groove.
In the embodiment of the present invention, a manner of forming the first groove or the hole may include dry etching or wet etching.
In some embodiments, the manner of forming the first groove may further include: the first part of the first dielectric layer is formed by first deposition, then the mask is covered, the second part of the first dielectric layer is formed by second deposition after the groove position is covered by the mask, and the first groove can be formed; in short, the first groove may be formed in various ways without being limited to any one of the above.
In the embodiment of the present invention, a method for forming the at least one second dielectric layer may include a chemical vapor deposition method, a physical vapor deposition method, and the like.
In an embodiment of the present invention, the material of the metal line may include conductive metal such as copper, aluminum, tungsten, and the like.
In this embodiment, the step S30 may include:
coating photoresist on the top of the at least one second dielectric layer, carrying out imaging processing on the photoresist through a developing technology, and transferring the pattern on the mask onto the photoresist;
and etching the at least one second dielectric layer, the first dielectric layer and the third dielectric layer which are positioned below the second groove by taking the patterned photoresist as a mask so as to form a hole for exposing the metal wire.
As shown in fig. 3, in some inventive embodiments, the method comprises:
step S40: depositing metal in the hole to form a metal pillar that contacts the metal line through the at least one second dielectric layer, the first dielectric layer, and the third dielectric layer;
step S50: and carrying out planarization treatment, wherein after planarization, the upper surface of the metal column is flush with the top of the at least one second dielectric layer.
In the embodiment of the present invention, the material of the metal pillar may include conductive metal such as copper, aluminum, tungsten, and the like. The material of the metal pillar may be the same as or different from that of the metal line.
In an embodiment of the present invention, the planarization process may include a chemical mechanical planarization process. For example, when the metal to be filled into the hole is copper, the copper is oxidized to generate copper oxide and copper hydroxide during planarization, and then the copper oxide is mechanically ground off by particles in a grinder; after the layer of oxide is abraded away, the chemical components in the abrasive continue to oxidize the re-exposed copper surface, and then the regenerated oxide is mechanically abraded away again; the process is repeated until the top of the at least one second dielectric layer is exposed.
In some embodiments of the invention, the step S20 may include:
depositing a first second dielectric layer on the top of the first dielectric layer, and forming a third groove based on the appearance of the first groove, wherein the sum of the width of the bottom of the third groove and the thickness of the first second dielectric layer on the top of the first groove is not less than the width of the hole at the position of the top of the third groove;
and depositing and forming a second dielectric layer on the top of the first second dielectric layer, and forming the second groove based on the appearance of the third groove. In some embodiments, the first second dielectric layer and the second dielectric layer are formed with different compositions. For example, the first second dielectric layer may be made of nitride, carbonitride, or the like; the second dielectric layer can be made of oxide.
In an embodiment of the invention, the first second dielectric layer may include silicon nitride or silicon carbonitride, the hardness of which is greater than that of the second dielectric layer, and the first second dielectric layer may be used as a stop layer for planarization processing.
In an embodiment of the present invention, the second dielectric layer may include silicon oxide, and is used to protect an upper surface of the first second dielectric layer when metal is deposited into the hole, so as to prevent components of the first second dielectric layer from entering the metal pillar and damaging a conductive property of the metal pillar.
In some embodiments, the composition of the first dielectric layer may include an oxide, such as silicon oxide;
the composition of the third dielectric layer may include a nitride, such as silicon nitride.
In some embodiments of the present invention, it is preferred that,
the width of the bottom of the first groove is larger than the line width of the metal line;
and/or the presence of a gas in the gas,
the width of the metal column is smaller than that of the bottom of the first groove;
and/or the presence of a gas in the gas,
the width of the metal column is larger than that of the bottom of the second groove.
In this embodiment, the width of the first groove in the preset direction is greater than the width of the metal line in the preset direction, and the preset direction may be a direction parallel to the spreading direction of the first dielectric layer, the second dielectric layer and/or the third dielectric layer.
The width of the metal column in the preset direction is smaller than that of the first groove in the preset direction.
The width of the metal column in the preset direction is larger than that of the second groove in the preset direction.
As shown in fig. 4, an embodiment of the present invention provides a semiconductor connection structure, including:
a first dielectric layer 13 on the substrate 1;
at least one second dielectric layer 34 located over the first dielectric layer 13;
a third dielectric layer 12 located below the first dielectric layer 13;
the metal wire 10 is positioned below the third dielectric layer 12;
the metal column 40 sequentially penetrates through the at least one second dielectric layer 34, the first dielectric layer 13 and the third dielectric layer 12 from top to bottom to be in contact with the metal wire 10;
the depth of the metal pillar 40 contacting the at least one second dielectric layer 34 is greater than the thickness of the at least one second dielectric layer 34 in the region outside the position of the metal pillar 40.
In an embodiment of the present invention, the substrate may include a monocrystalline silicon wafer, a polycrystalline silicon wafer, a wafer having other dielectric layers, metal regions, or circuit structures, and the like, and is used for bearing the first dielectric layer, the at least one second dielectric layer, the third dielectric layer, the metal line, and the connection structure.
In some inventive embodiments, the width of the bottom of the metal pillar is not greater than the line width of the metal line.
In some embodiments of the present invention, it is preferred that,
the width of the bottom of the first groove is larger than the line width of the metal line;
and/or the presence of a gas in the gas,
the width of the metal column is smaller than that of the bottom of the first groove;
and/or the presence of a gas in the gas,
the width of the metal column is larger than that of the bottom of the second groove.
Several specific examples are provided below in connection with any of the above-described embodiments of the invention:
example 1:
the fabrication of a dual damascene (VIA) VIA connection structure is performed by two-step photolithography (Litho-etch) and one-step filling, and a method for fabricating a dual damascene VIA connection structure is described below with reference to fig. 5 to 10, where the method includes:
step S100: providing a semiconductor substrate, wherein the semiconductor substrate sequentially comprises a dielectric layer containing a metal wire, an etching stop layer, a first dielectric layer, an etching barrier layer and a protective layer from bottom to top; for example, as shown in fig. 6, a semiconductor substrate 2 is provided, where the semiconductor substrate 2 sequentially includes, from bottom to top, a dielectric layer 11 including a metal line 10, an etch stop layer 12, a first dielectric layer 13, an etch stop layer 14, and a protective layer 15;
step S110: etching the protective layer, the etching barrier layer and the first dielectric layer at positions corresponding to the metal line, and consuming part of the etching stop layer to form a first hole, wherein the bottom of the first hole is positioned in the etching stop layer, and the width of the bottom of the first hole is smaller than the line width of the metal line; for example, at a position corresponding to the metal line 10, etching the protection layer 15, the etch stop layer 14, the first dielectric layer 13, and consuming a part of the etch stop layer 12 to form a first hole 20, where the bottom of the first hole 20 is located in the etch stop layer 12, and a width of the bottom of the first hole 20 is smaller than a line width of the metal line 10;
step S120: etching the protective layer and the etching barrier layer at the position of the first hole, consuming part of the first dielectric layer to form a second hole, and etching the etching stop layer to expose the metal wire so that the first hole is connected with the metal wire; wherein the bottom of the second hole is located in the first dielectric layer, the width of the top of the second hole is greater than the width of the top of the first hole, and the width of the bottom of the second hole is greater than the width of the first hole at the position of the bottom of the second hole; for example, as shown in fig. 7 and 8, at the position of the first hole 20, the protective layer 15 and the etching barrier layer 14 are etched, and a portion of the first dielectric layer 13 is consumed, so as to form a second hole 21, and the etching stop layer 12 is etched to expose the metal line 10, so that the first hole 20 is connected to the metal line 10;
step S130: depositing a copper seed layer into the first and second holes; performing copper filling on the surface of the copper seed layer through electrochemical deposition (ECP); for example, as shown in fig. 9, a copper seed layer is deposited into the first and second holes 20 and 21; carrying out copper filling on the surface of the copper seed layer through an electrochemical deposition process;
step S140: carrying out planarization treatment, and removing the extra copper and the protective layer on the surface of the semiconductor substrate to form a metal connecting column; for example, as shown in fig. 10, a planarization process removes the extra copper and the protective layer 15 from the surface of the semiconductor substrate 2 to form metal connection studs 30.
In the step S110, since the thickness of the first dielectric layer is relatively large, the depth of the etched first hole is relatively deep, and a hard mask (hard mask) is required to realize alignment of etching and control of the etching depth when the first through hole is etched, so as to ensure uniformity of the etching depth of the first through hole.
The second through hole is formed by the method, and the first dielectric layer on the exposed side wall of the first through hole has higher etching speed than the barrier layer because the hardness of the first dielectric layer is less than that of the etching barrier layer; and the opening size of the second hole is larger at the interface of the first dielectric layer and the etching barrier layer, so that a step-shaped appearance is easily formed at the interface on the side wall of the second hole, a subsequent copper seed layer is discontinuous, copper filling is poor, and the product yield is reduced. Avoiding such a step-like topography in the second hole is a major challenge for the etching process.
In addition, because the opening size that first hole is located the second hole bottom position is less, consequently the ratio of the degree of depth that first hole is located below the second hole bottom and opening size is great, has increased the degree of difficulty to the even continuous copper seed layer of deposit in the first hole, has further reduced copper seed layer quality, influences the quality of the copper of filling, reduces the electrical property of metal connecting post, the quality of harm product.
Accordingly, embodiments of the present invention provide a method for fabricating a semiconductor connection structure. A method for fabricating a semiconductor connection structure according to an embodiment of the present invention is described in detail with reference to fig. 11 to 17, which includes:
step S1: providing a semiconductor substrate, wherein the semiconductor substrate sequentially comprises a dielectric layer containing a metal wire and an etching stop layer from bottom to top, depositing a first dielectric layer on the semiconductor substrate, and forming a first groove in the first dielectric layer at a position corresponding to the metal wire, wherein the depth of the first groove is smaller than the thickness of the first dielectric layer, and the width of the bottom of the first groove is larger than the width of the metal wire; for example, as shown in fig. 12 and 13, a semiconductor substrate 1 is provided, where the semiconductor substrate 1 sequentially includes, from bottom to top, a dielectric layer 11 including a metal line 10 and an etch stop layer 12, a first dielectric layer 13 is deposited on the semiconductor substrate 1, and a first groove 22 is formed in the first dielectric layer 13 at a position corresponding to the metal line 10, where a depth of the first groove 22 is smaller than a thickness of the first dielectric layer 13, and a width of a bottom of the first groove 22 is greater than a width of the metal line 10;
step S2: depositing an etching barrier layer on the top of the first dielectric layer, and forming a third groove based on the appearance of the first groove; depositing a protective layer on the top of the etching barrier layer, and forming a second groove based on the appearance of the third groove; for example, as shown in fig. 14, an etching barrier layer 14 is deposited on top of the first dielectric layer 13, and a third groove is formed above the position of the first groove 22; depositing a protective layer 15 on the top of the etching barrier layer 14, and forming a second groove 23 based on the third groove;
step S3: etching the protective layer, the etching barrier layer, the first dielectric layer and the etching stop layer at the bottom of the second groove to form a hole exposing the metal wire, wherein the metal wire is positioned below the etching stop layer, and the sum of the width of the bottom of the third groove and the thickness of the etching barrier layer is not less than the width of the hole at the top of the third groove; for example, as shown in fig. 15, the protection layer 15, the etch stop layer 14, the first dielectric layer 13 and the etch stop layer 12 at the bottom of the second groove 23 are etched to form a hole 24 exposing the metal line 10, wherein the metal line 10 is located below the etch stop layer 12, and the sum of the width of the bottom of the third groove and the thickness of the etch stop layer 14 is not less than the width of the hole 24 at the top of the third groove;
step S4: depositing a copper barrier layer within the hole by a Physical Vapor Deposition (PVD) process, depositing a copper seed layer over the copper barrier layer by a physical vapor deposition process; carrying out copper filling on the surface of the copper seed layer through an electrochemical deposition process; for example, as shown in fig. 16, a copper barrier layer is deposited within the via 24 by a physical vapor deposition process, and a copper seed layer is deposited on the copper barrier layer by a physical vapor deposition process; carrying out copper filling on the surface of the copper seed layer through an electrochemical deposition process;
step S5: removing the extra copper on the surface of the protective layer and the protective layer through Chemical Mechanical Planarization (CMP) to form a metal column, wherein the upper surface of the metal column is flush with the top of the etching barrier layer after the chemical mechanical planarization; for example, as shown in fig. 17, the extra copper on the surface of the protection layer 15 and the protection layer 15 are removed by a chemical mechanical planarization process to form a metal pillar 40, wherein the upper surface of the metal pillar 40 is flush with the top of the etch stop layer 14 after the chemical mechanical planarization.
By the method, when the hole is etched, an additional hard mask is not required to be introduced, so that the cost can be effectively reduced, the process time can be shortened, the difficulty of the etching process can be reduced, and the process window of the etching process can be enlarged; the depth-to-width ratio of the holes is small, the side wall appearance is smooth, a copper seed layer is favorably and continuously and uniformly deposited in the holes, the filling quality of the metal columns is improved, and the quality of products is further improved; the depth of the metal column in contact with the etching barrier layer is larger than the thickness of the etching barrier layer in the region outside the metal column, so that the diffusion of copper in the metal column is prevented, and the reliability of the product is improved.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method for fabricating a semiconductor interconnect structure, comprising:
forming a first groove in the first dielectric layer at a position corresponding to the metal wire; wherein the depth of the first groove is not more than the thickness of the first dielectric layer;
depositing at least one second dielectric layer on the top of the first dielectric layer, and forming second grooves based on the appearance of the first grooves;
and etching the at least one second dielectric layer, the first dielectric layer and the third dielectric layer below the second groove to form a hole exposing the metal wire, wherein the metal wire is positioned below the third dielectric layer, the top opening of the hole is flush with the top of the at least one reserved second dielectric layer, and the side wall of the hole is continuous and smooth.
2. The method of claim 1, comprising:
depositing metal in the hole to form a metal pillar that contacts the metal line through the at least one second dielectric layer, the first dielectric layer, and the third dielectric layer;
and carrying out planarization treatment, wherein after planarization, the upper surface of the metal column is flush with the top of the at least one second dielectric layer.
3. The method of claim 1 or 2, wherein depositing at least one second dielectric layer on top of the first dielectric layer and forming the second recess based on the topography of the first recess comprises:
depositing a first second dielectric layer on the top of the first dielectric layer, and forming a third groove based on the appearance of the first groove, wherein the sum of the width of the bottom of the third groove and the thickness of the first second dielectric layer on the top of the first groove is not less than the width of the hole at the position of the top of the third groove;
and depositing and forming a second dielectric layer on the top of the first second dielectric layer, and forming the second groove based on the appearance of the third groove.
4. The method of claim 3,
the first second dielectric layer and the second dielectric layer are made of different compositions.
5. The method of claim 1,
the first dielectric layer comprises an oxide;
the third dielectric layer comprises a nitride.
6. The method of claim 4,
the composition of the first second dielectric layer comprises nitride or carbonitride;
the second dielectric layer comprises an oxide.
7. The method of claim 1,
the width of the bottom of the first groove is larger than the line width of the metal line;
and/or the presence of a gas in the gas,
the width of the metal column is smaller than that of the bottom of the first groove;
and/or the presence of a gas in the gas,
the width of the metal column is larger than that of the bottom of the second groove;
wherein the metal pillar is formed by depositing a metal in the hole.
8. A semiconductor connection structure, comprising:
a first dielectric layer located on the substrate;
at least one second dielectric layer located above the first dielectric layer;
the third dielectric layer is positioned below the first dielectric layer;
the metal wire is positioned below the third dielectric layer;
the metal column sequentially penetrates through the at least one second dielectric layer, the first dielectric layer and the third dielectric layer from top to bottom to be in contact with the metal line;
wherein the content of the first and second substances,
a first groove is formed in the first dielectric layer at a position corresponding to the metal wire; the depth of the first groove is not more than the thickness of the first medium layer;
a second groove is formed in the at least one second dielectric layer based on the appearance of the first groove; the metal column is formed by etching the at least one second dielectric layer, the first dielectric layer and the third dielectric layer which are positioned below the second groove to form a hole for exposing the metal wire, and the hole is filled; the top opening of the hole is flush with the top of the at least one second medium layer, and the side wall of the hole is continuous and smooth;
the depth of the metal column contacting with the at least one second dielectric layer is larger than the thickness of the at least one second dielectric layer in the region outside the metal column.
9. The structure of claim 8,
the width of the bottom of the metal column is not larger than the line width of the metal line.
10. The structure of claim 8,
the width of the bottom of the first groove is larger than the line width of the metal line;
and/or the presence of a gas in the gas,
the width of the metal column is smaller than that of the bottom of the first groove;
and/or the presence of a gas in the gas,
the width of the metal column is larger than that of the bottom of the second groove.
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| CN201910007779.2A CN109887880B (en) | 2019-01-04 | 2019-01-04 | Semiconductor connection structure and manufacturing method thereof |
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| CN201910007779.2A CN109887880B (en) | 2019-01-04 | 2019-01-04 | Semiconductor connection structure and manufacturing method thereof |
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