KR20040043383A - Method for forming Cu wiring of semiconductor device - Google Patents
Method for forming Cu wiring of semiconductor device Download PDFInfo
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- KR20040043383A KR20040043383A KR1020020071626A KR20020071626A KR20040043383A KR 20040043383 A KR20040043383 A KR 20040043383A KR 1020020071626 A KR1020020071626 A KR 1020020071626A KR 20020071626 A KR20020071626 A KR 20020071626A KR 20040043383 A KR20040043383 A KR 20040043383A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 소자의 구리 배선 형성방법에 관한 것으로, 보다 상세하게는, 구리 배선 형성시 발생하는 디싱(Dishing)을 감소시킬 수 있는 반도체 소자의 구리 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly, to a method for forming a copper wiring of a semiconductor device capable of reducing dishing generated during copper wiring formation.
주지된 바와 같이, 금속배선의 재료로서는 전기전도도가 우수하고 가공성이 좋은 알루미늄(Al)이 주로 이용되어 왔다. 그런데, 알루미늄(Al) 배선은 전자 이동 (Electromigration) 및 스트레스 이동(Stress Migration) 등과 같은 배선 신뢰성측면에서 한계가 있어서, 새로운 배선 재료를 요구하게 되었고, 그 하나의 예로서 구리(Cu) 배선의 형성이 진행되고 있다.As is well known, aluminum (Al) having excellent electrical conductivity and good workability has been mainly used as a material for metal wiring. However, aluminum (Al) wiring has limitations in terms of wiring reliability, such as electromigration and stress migration, and thus requires a new wiring material, and as an example, the formation of copper (Cu) wiring This is going on.
현재 진행중인 구리 배선은 순수한 구리만으로 형성되고 있으며, 통상은 전기도금(eletroplating) 방식을 이용해서 배선 형성에 필요한 구리막을 증착하고 있다.Current copper wiring is formed of pure copper only, and is usually deposited by the electroplating (eletroplating) method for depositing a copper film.
이러한 순수 구리 배선은 기존의 알루미늄 또는 그 합금 배선에 비하여 더 우수한 배선 신뢰성을 갖는다.Such pure copper wiring has better wiring reliability than conventional aluminum or alloy wiring thereof.
한편, 상기 알루미늄 배선은 알루미늄막의 증착 및 이에 대한 식각을 통해 용이하게 형성할 수 있는 반면, 상기 구리 배선은 구리막의 식각이 용이치 않은 것과 관련하여 알루미늄 배선과 동일한 방법으로는 그 형성이 어렵다. 특히, 반도체 소자의 고집적화 추세에서, 식각 데미지 및 후속 열공정에 의한 데미지 등을 고려할 때, 기존의 방식으로 구리 배선을 형성한다는 것은 실질적으로 곤란하다.On the other hand, the aluminum wiring can be easily formed through the deposition and etching of the aluminum film, while the copper wiring is difficult to form in the same way as the aluminum wiring with respect to the etching of the copper film is not easy. In particular, in the trend of high integration of semiconductor devices, it is practically difficult to form copper wiring in a conventional manner in consideration of etching damage, damage by subsequent thermal processes, and the like.
따라서, 상기 현재의 구리 배선은 배선 영역을 한정하는 비아홀 및 트렌치를 형성한 후에 구리막을 증착하고, 그리고나서, CMP(Chemical Mechanical Polishing)를 수행하는 듀얼-다마신(dual-damascene) 공정으로 형성하고 있다.Therefore, the current copper wiring is formed by a dual-damascene process in which a copper film is deposited after the formation of via holes and trenches defining wiring regions, followed by chemical mechanical polishing (CMP). have.
아울러, 상기 구리 배선을 포함한 통상의 금속 배선은 실질적인 배선 재료의 하부에 배선 재료의 접착력를 증대시키면서 기판 실리콘과의 반응을 방지하기 위해 베리어막(barrier layer)을 배치시키고 있으며, 이러한 베리어막으로서는 통상 Ti/TiN 적층막이 이용되고 있다.In addition, in the conventional metal wiring including the copper wiring, a barrier layer is disposed to prevent the reaction with the substrate silicon while increasing the adhesive force of the wiring material under the substantially wiring material. A / TiN laminated film is used.
한편, 상기 구리막을 CMP하는 공정은, 일반적으로, 2단계로 나누어져 수행되며, 여기서, 1차 CMP 공정은 구리막에 대한 식각 속도가 빠른 슬러리, 예컨데, H2O2를 사용하여 Ti/TiN의 베리어막이 노출되도록 수행하고, 상기 2차 CMP 공정은 상기 트렌치 및 비아홀내의 구리막과 함께 노출된 베리어막을 연마하는 것이다.On the other hand, the process of CMP the copper film is generally carried out in two steps, where the first CMP process is a slurry having a high etching rate for the copper film, for example, using Ti / TiN using H 2 O 2 The barrier film is exposed so as to be exposed, and the secondary CMP process is to polish the exposed barrier film together with the copper film in the trench and via hole.
그러나, 상기와 같은 1차 CMP 공정은 베리어막 보다 구리막의 연마 속도가 빠르기 때문에 상기 베리어막이 노출되는 시점에서 비아홀 및 트렌치 내의 구리막에 디싱(Dishing)이 발생되는 문제점이 있다.However, since the polishing rate of the copper film is faster than that of the barrier film, the first CMP process may cause dishing in the copper film in the via hole and the trench when the barrier film is exposed.
또한, 2차 CMP 공정을 진행하는 경우에는 상기 디싱 현상에 의하여 CMP 공정 특성이 열화되어 소자의 수율 및 신뢰성이 감소된다.In addition, when the second CMP process is performed, the CMP process characteristics are deteriorated by the dishing phenomenon, thereby reducing the yield and reliability of the device.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 구리막을 CMP 할때 발생되는 디싱을 감소시킬 수 있는 반도체 소자의 구리 배선 형성방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a copper wiring of a semiconductor device capable of reducing dishing generated when CMP of a copper film.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a method of forming a copper wiring of a semiconductor device according to an embodiment of the present invention.
-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing
1 : 반도체 기판 3 : 산화막1 semiconductor substrate 3 oxide film
5 : 비아홀 7 : 트렌치5: via hole 7: trench
9 : Ti/TiN의 베리어막 11 : 구리막9: Barrier film of Ti / TiN 11: Copper film
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 구리 배선 형성방법은 반도체 기판 상에 비아홀 및 트렌치를 구비한 산화막을 형성하는 단계; 상기 비아홀 및 트렌치 표면과 산화막 상에 Ti/TiN의 베리어막을 증착하는 단계; 상기 비아홀 및 트렌치가 매립되도록 상기 Ti/TiN의 베리어막 상에 구리막을 증착하는 단계; 상기 Ti/TiN의 베리어막 보다 구리막의 연마 속도가 빠른 산화제를 슬러리에 첨가하여 상기 구리막을 Ti/TiN의 베리어막이 노출되지 않는 소정의 높이까지1차로 CMP하는 단계; 상기 Ti/TiN의 베리어막 보다 구리막간의 연마 속도가 빠른 산화제를 슬러리에 첨가하여 상기 Ti/TiN의 베리어막이 노출되도록 상기 구리막을 2차로 CMP하는 단계; 상기 구리막 보다 Ti/TiN의 베리어막의 연마 속도가 빠른 슬러리를 사용하여 상기 산화막 상의 Ti/TiN의 베리어막을 3차로 CMP하는 단계를 포함한다.Copper wiring forming method of a semiconductor device of the present invention for achieving the above object comprises the steps of forming an oxide film having a via hole and a trench on a semiconductor substrate; Depositing a barrier film of Ti / TiN on the via hole and the trench surface and the oxide film; Depositing a copper film on the barrier film of Ti / TiN to fill the via hole and the trench; Adding an oxidizing agent having a faster polishing rate of the copper film than the barrier film of Ti / TiN to the slurry to primarily CMP the copper film to a predetermined height such that the barrier film of Ti / TiN is not exposed; CMP of the copper film secondly such that the barrier film of Ti / TiN is exposed by adding an oxidizing agent having a faster polishing rate between copper films than the Ti / TiN barrier film to the slurry; CMP of the barrier film of Ti / TiN on the oxide film in a third step using a slurry having a faster polishing rate of the barrier film of Ti / TiN than the copper film.
여기서, 상기 1차 CMP는 상기 Ti/TiN의 베리어막 상의 구리막이 500∼3000Å의 두께가 잔류되는 시점까지 수행한다.Here, the primary CMP is performed until the copper film on the barrier film of Ti / TiN remains at a thickness of 500 to 3000 GPa.
그리고, 상기 2차 CMP의 슬러리에 첨가되는 산화제는 1차 CMP의 슬러리에 첨가되는 산화제와 비교하여 15∼85%의 중량비를 갖는다.The oxidant added to the slurry of the secondary CMP has a weight ratio of 15 to 85% compared to the oxidant added to the slurry of the primary CMP.
또한, 상기 2차 CMP는 슬러리를 50∼1000㎖/분 으로 플러우(flow)시키면서, 다운 압력(Down force)을 1∼10 PSI, 그리고, 플레이튼(Platen) 회전속도를 50∼ 800 RPM으로 하는 조건으로 수행한다.In addition, the secondary CMP flows the slurry at 50 to 1000 ml / min, down pressure is 1 to 10 PSI, and platen rotation speed is 50 to 800 RPM. It is performed under the condition that
본 발명에 따르면, Ti/TiN의 베리어막이 노출되기 전 상기 베리어막과 구리막간의 연마 속도가 동일하도록 상기 구리막을 CMP하여 상기 베리어막의 표면을 노출시키므로 구리 배선에 발생하는 디싱 현상을 방지할 수 있다.According to the present invention, since the copper film is exposed to the surface of the barrier film by CMP so that the polishing rate between the barrier film and the copper film is the same before the barrier film of Ti / TiN is exposed, dishing phenomenon occurring in the copper wiring can be prevented. .
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a copper wiring in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(1) 상에 산화막(3)을 증착한다. 그런다음, 상기 산화막(3)에 배선 영역을 한정하는 비아홀(5) 및 트렌치(7)를 형성한 후, 상기 비아홀(5) 및 트렌치(7)의 표면과 산화막(3) 상에 Ti/TiN의 베리어막(9)을 증착한다. 그런다음, 상기 트렌치(7) 및 비아홀(5)이 매립되도록 상기 베리어막(9) 상에 구리막(11)을 증착한다.Referring to FIG. 1A, an oxide film 3 is deposited on a semiconductor substrate 1. Then, via holes 5 and trenches 7 defining wiring regions in the oxide film 3 are formed, and then Ti / TiN is formed on the surfaces of the via holes 5 and trenches 7 and the oxide film 3. The barrier film 9 is deposited. Then, a copper film 11 is deposited on the barrier film 9 to fill the trench 7 and the via hole 5.
그 다음, 상기 구리막(11)의 표면을 1차로 CMP한다. 이때, 1차 CMP로 베리어막(9) 상의 구리막(11)의 잔류 두께가 500∼3000Å이 되는 시점을 연마 타겟으로 수행한다.Next, the surface of the copper film 11 is primarily CMP. At this time, the polishing target is performed at the time when the residual thickness of the copper film 11 on the barrier film 9 becomes 500 to 3000 Pa by primary CMP.
따라서, 후속의 2차 CMP는 EPD(End point detect) 시스템을 사용하여 EPD 시점, 바람직하게는, 베리어막(9) 상의 구리막(11)이 500∼3000Å의 두께로 잔류되는 시점부터 진행한다.Therefore, the subsequent secondary CMP proceeds from the EPD time point, preferably, the time point at which the copper film 11 on the barrier film 9 remains at a thickness of 500 to 3000 kPa using an EPD (End point detect) system.
상기 1차 CMP는 상기 베리어막(9) 보다 구리막(11)의 연마 속도를 높이기 위하여 산화제, 예컨데, H2O2가 첨가된 슬러리를 사용하여 수행한다.The primary CMP is performed using a slurry to which an oxidizing agent, for example, H 2 O 2 is added, in order to increase the polishing rate of the copper film 11 rather than the barrier film 9.
한편, 상기 구리막(11)의 연마 속도는 슬러리에 첨가되는 산화제의 농도비에 의하여 제어된다. 즉, 상기 구리막(11)의 연마 속도는 슬러리에 첨가되는 산화제의 농도가 높아질수록 증가되나, 상기 산화제의 농도가 일정량 이상이 되면 상기 구리막(11)의 연마 속도는 더 이상 증가되지 않는 특성을 가진다.On the other hand, the polishing rate of the copper film 11 is controlled by the concentration ratio of the oxidant added to the slurry. That is, the polishing rate of the copper film 11 increases as the concentration of the oxidant added to the slurry increases, but when the concentration of the oxidant becomes more than a predetermined amount, the polishing rate of the copper film 11 does not increase any more. Has
도 1b를 참조하면, 상기 산화막(3) 상의 베리어막(9)이 노출되도록 상기 구리막(11)을 2차 CMP한다.Referring to FIG. 1B, the copper film 11 is secondary CMP such that the barrier film 9 on the oxide film 3 is exposed.
여기서, 상기 2차 CMP는 슬러리를 50∼1000㎖/분 으로 플러우(flow)시키면서, 다운 압력(Down force)을 1∼10 PSI, 그리고, 플레이튼(Platen) 회전속도를 50∼800 RPM으로 하는 조건으로 수행한다.In this case, the secondary CMP flows the slurry at 50 to 1000 ml / min, down pressure is 1 to 10 PSI, and platen rotation speed is 50 to 800 RPM. It is performed under the condition that
한편, 전술한 바와 같이, 1차 CMP에서 슬러리에 첨가된 산화제의 중량비는 베리어막보다 산화막의 연마속도를 높여준다.On the other hand, as described above, the weight ratio of the oxidant added to the slurry in the primary CMP increases the polishing rate of the oxide film than the barrier film.
여기서, 상기 구리막(11)을 연마하여 베리어막(9)을 노출시키는 2차 CMP에서 사용되는 산화제를 상기 1차 CMP에 사용되는 산화제와 동일한 중량비로 조정하면, 상기 구리막(11)과 베리어막(9)간의 연마속도 차이로 인하여 상기 구리막(11) 표면에 디싱이 발생한다.Here, when the oxidant used in the secondary CMP for polishing the copper film 11 to expose the barrier film 9 is adjusted to the same weight ratio as the oxidant used for the primary CMP, the copper film 11 and the barrier Dicing occurs on the surface of the copper film 11 due to the difference in polishing rates between the films 9.
따라서, 상기 2차 CMP에서 첨가되는 산화제는 1차 CMP의 슬러리에 첨가된 산화제의 15∼85％의 중량비로 조정하여 구리막(11)과 베리어막(9)간의 연마 선택비를 종래의 그것과 비교하여 20∼80％로 감소시킨다.Therefore, the oxidizing agent added in the secondary CMP is adjusted to a weight ratio of 15 to 85% of the oxidizing agent added to the slurry of the primary CMP to adjust the polishing selectivity between the copper film 11 and the barrier film 9 with that of the conventional one. Compared to 20 to 80%.
이때, 상기 구리막(11)을 베리어막(9)이 노출되도록 2차 CMP 할때 상기 구리막(11)과 베리어막(9)간의 연마 속도의 차이로 인하여 발생되는 디싱을 현저하게 감소시킬 수 있다.In this case, when the second CMP is exposed to the barrier layer 9, the dishing caused by the difference in polishing speed between the copper layer 11 and the barrier layer 9 may be significantly reduced. have.
도 1c를 참조하면, 상기 베리어막(9)과 비아홀(5) 및 트렌치(7) 내의 구리막 (11)을 3차 CMP 한다. 이때, 상기 3차 CMP는 상기 구리막(11) 보다 베리어막(9)의 연마 속도가 빠른 슬러리를 사용하여 수행한다.Referring to FIG. 1C, the barrier film 9, the via hole 5, and the copper film 11 in the trench 7 are subjected to third CMP. In this case, the tertiary CMP is performed using a slurry having a faster polishing rate of the barrier film 9 than the copper film 11.
여기서, 상기 비아홀(5) 및 트렌치(7) 내의 구리막(11)은 2차 CMP 공정에서 상기 구리막(11)과 베리어막(9)간의 연마 속도 차이로 인한 디싱을 현저하게 감소시켰으므로 3차 CMP 공정에서도 안정된 CMP 공정 특성을 얻을 수 있다.Here, the copper film 11 in the via hole 5 and the trench 7 significantly reduces dishing due to the difference in polishing rate between the copper film 11 and the barrier film 9 in the second CMP process. Stable CMP process characteristics can be obtained even in the next CMP process.
이상에서와 같이, 본 발명은 구리막을 CMP하는 공정을 3단계로 나누어 수행하되, 각각 베리어막과 구리막간의 연마 속도를 다르게 하여 수행하므로, 구리 배선에 발생하는 디싱을 종래의 그것과 비교하여 현저하게 감소시킬 수 있으며, 그래서, 소자의 수율 및 신뢰성을 향상시킬 수 있다.As described above, the present invention is carried out by dividing the process of CMP the copper film in three steps, respectively, by varying the polishing rate between the barrier film and the copper film, so that dishing generated in the copper wiring is remarkably compared to the conventional one. Can be reduced, so that the yield and reliability of the device can be improved.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시 할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
Claims (4)
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| DE102006040585A1 (en) * | 2006-08-30 | 2008-03-20 | Infineon Technologies Ag | A method of filling a trench in a semiconductor product |
| KR20200111334A (en) | 2019-03-19 | 2020-09-29 | 하이엔드테크놀로지(주) | Method for manufacturing semiconductor memory device |
| CN113508458A (en) * | 2019-05-08 | 2021-10-15 | Lsr工程与咨询有限公司 | Method for structuring a substrate |
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| DE102006040585B4 (en) * | 2006-08-30 | 2013-02-07 | Infineon Technologies Ag | A method of filling a trench in a semiconductor product |
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