JPH0329298B2 - - Google Patents
Info
- Publication number
- JPH0329298B2 JPH0329298B2 JP59223351A JP22335184A JPH0329298B2 JP H0329298 B2 JPH0329298 B2 JP H0329298B2 JP 59223351 A JP59223351 A JP 59223351A JP 22335184 A JP22335184 A JP 22335184A JP H0329298 B2 JPH0329298 B2 JP H0329298B2
- Authority
- JP
- Japan
- Prior art keywords
- heat
- insulating film
- resistant resin
- heat treatment
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010438 heat treatment Methods 0.000 claims description 23
- 229920006015 heat resistant resin Polymers 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000002904 solvent Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 20
- 229920005989 resin Polymers 0.000 description 14
- 239000011347 resin Substances 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000005587 bubbling Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- NQBXSWAWVZHKBZ-UHFFFAOYSA-N 2-butoxyethyl acetate Chemical compound CCCCOCCOC(C)=O NQBXSWAWVZHKBZ-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000005375 organosiloxane group Chemical group 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000013557 residual solvent Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
〔産業上の利用分野〕
本発明は、半導体装置の多層配線における層間
絶縁膜の形成方法に関するものである。
配線間の層間絶縁膜は、多層配線による高集積
化を要する現在、配線不要を防止する為に極めて
重要な役割を担つている。
〔従来の技術〕
多層配線工程においては、上層配線のステツプ
カバレツジを良好に保つため層間絶縁膜の表面を
平坦化する技術が種々提案されている。ここで
は、耐熱性樹脂を使用して層間絶縁膜を平坦に形
成する方法を第７図を参照して説明する。
シリコン等の半導体基板１表面に二酸化シリコ
ン（SiO2）膜２を形成し、アルミニウムシリコ
ン合金を被着し、パターニングして下層配線層３
とする。次いでCVD（Chemical Vapour
Deposition）法で全面にリンシリケートガラス
（以下PSGと略示する）層を形成して下層絶縁膜
４とし、全面に耐熱性樹脂層５を塗布し120℃で
30分間、次いで300℃で30分間熱処理をした後全
面から均一深さでエツチングをするコントロール
エツチングを施し、さらに全面に上層絶縁膜６を
形成する。そして上下の絶縁膜４，６を通るスル
ーホールを開孔し、上層配線層７を形成する。
以上は特願昭59−021835によるものである。
〔発明が解決しようとする問題点〕
前述の工程では、300℃で30分間の熱処理を行
つてからコントロールエツチングを施しているが
300℃では、樹脂に対する処理が十分でないため
にコントロールエツチング後の絶縁膜成長時（〜
450℃程度の成長温度）に樹脂が含んでいるメチ
ル基やOH基等が分解してガスが発生する。この
ガスは上層に絶縁膜があるために逃げ場を失い、
樹脂層中にたまり、ついには絶縁膜の破裂に至
り、バブリング現象という不良をおこす。この現
象を防ぐために樹脂が十分に熱処理される温度、
たとえば400℃程度に上げると、樹脂膜の厚い部
分で体積収縮によるクラツクが発生するという問
題が生じてくる。
上記工程におけるバブリング，クラツクの発生
率は高く、70〜80％の製品不良に至ることがあ
る。
本発明は、このような問題点を解決することを
目的とするものである。
〔問題点を解決するための手段〕
本発明では上記問題点を解決するために、表面
に電極配線パターンを有する基板上に、絶縁膜を
被着する工程と、全面に耐熱性樹脂溶液を塗布す
る工程と、該耐熱性樹脂溶液中の溶媒除去のため
の第一の熱処理を行う工程と、該耐熱性樹脂及び
該絶縁膜のエツチング速度をほぼ等しくしてエツ
チングを施し、少なくとも後に前記第一の熱処理
よりも高い温度で行う第二の熱処理においてクラ
ツクが生じない膜厚になるまで該耐熱性樹脂を薄
膜化する工程と、該耐熱性樹脂中の、熱処理によ
り気化する成分を除去するための第二の熱処理を
行う工程とを含むように製造することで達成す
る。
〔作 用〕
上記層間絶縁膜の形成方法において、第１の熱
処理は耐熱性樹脂に含まれる溶媒を除去できる低
温（200℃以下）で行う。実施例ではポリラダー
オルガノシロキサン（以下PLOSと略す）に含ま
れる溶媒，エチレングリコールモノブチルエーテ
ルアセテートを除去できる。
次いで耐熱性樹脂層と該絶縁膜のエツチング速
度を等しくして反応性イオンエツチングで全面を
均一深さにエツチングし該耐熱性樹脂層を薄くす
る（平坦部ではなくなるようにするのがよい。）
この結果、該耐熱性樹脂及び該絶縁膜の表面を
なめらかにすることができる。この後高温（400
℃以上）で第２の熱処理を行うが全面エツチング
により膜厚が薄くなつているため体積収縮の影響
は小さくなりクラツクの発生がおさえられる。し
たがつて、従来例よりも高温の熱処理が可能とな
り樹脂中に含まれるメチル基等はこの高温熱処理
によつて外部へ飛散することができる。
〔実施例〕
第１図〜第６図を参照して説明する。
第１図では、シリコン等の半導体基板１１の表
面上に例えばCVD（Chemical Vapor
Deposition）法でSiO2膜１２を形成後、下層配
線層１３を厚さ1.0μmにアルミニウム（Al）で形
成する。配線材料は金，タングステン等でもよ
い。第２図では、該下層配線層１３および該
SiO2膜１２上にCVD法で厚さ0.7μmにリンシリ
ケートガラス（以下PSGと略す）を形成し、下
層絶縁膜１４とする。絶縁材料はPSGのかわり
にシリコン窒化膜，二酸化シリコン等でもよい。
第３図では、該下層絶縁膜１４上全面に耐熱性
樹脂であるPLOS15（Poly−Ladder−Organo−
Siloxane）をスピンナーで回転塗布し、平坦部
の膜厚ｔが0.5μmになるように積層し、120〜160
℃で30〜60分間第１の熱処理を行い該樹脂に含ま
れるエチレングリコールモノブチルエーテルアセ
テート等の残留溶媒を除去する。この樹脂のかわ
りにポリイミド，耐熱性ホトレジスト等使用して
もよい。
第４図では耐熱性樹脂の全面に四弗化炭素
（CF4）と三弗化メタン（CHF3）の混合ガス中で
反応性イオンエツチング（以下RIEと略す）を施
す。このとき該下層絶縁膜１４と該樹脂層１５の
エツチング速度は等しくなるようにして0.5〜
0.7μm程度コントロールエツチングをする。エツ
チングは樹脂が段差部にのみ残るまで行う。この
とき段差部の樹脂の厚さは0.3〜0.5μmになる。コ
ントロールエツチングの条件は下層絶縁膜と耐熱
性樹脂の材料に応じて選択する。
第５図では、該樹脂層１５がコントロールエツ
チングにより平坦化され凹部のみに残されて埋め
込まれた状態で400〜450℃の第２の熱処理を30〜
60分間施し、組成的に安定にする。次いで上層絶
縁膜１６をCVD法で形成する。
第６図では電極部にフオトリソグラフイ法でス
ルーホールを開孔し、上層配線層１７を形成し、
以下同様に多層配線を行う。
上記方法によれば従来の熱処理で70〜80％の割
合で生じていたクラツク及びバブリング現象によ
る製品不良をなくすことができる。
〔表１〕は、実施例で示した工程において、５
cm2当りのクラツク発生数のPLOSの平坦部での塗
布膜厚ｔ及び60分間の第２の熱処理温度に対する
依存性を調査した結果である。
この表によれば、第２の熱処理温度が400℃の
場合、平坦部の塗布膜厚ｔは0.2μm以下にすれば
クラツクは発生しないことがわかる。300℃以下
の条件では、後のCVD法による絶縁膜の成長工
程で、バブリング現象が発生するために採用でき
ない。
[Industrial Field of Application] The present invention relates to a method for forming an interlayer insulating film in multilayer wiring of a semiconductor device. The interlayer insulating film between wires plays an extremely important role in preventing the need for wires in today's world where high integration is required through multilayer wiring. [Prior Art] In a multilayer wiring process, various techniques have been proposed for flattening the surface of an interlayer insulating film in order to maintain good step coverage of upper layer wiring. Here, a method for forming a flat interlayer insulating film using a heat-resistant resin will be described with reference to FIG. A silicon dioxide (SiO 2 ) film 2 is formed on the surface of a semiconductor substrate 1 made of silicon, etc., and an aluminum silicon alloy is deposited on it and patterned to form a lower wiring layer 3.
shall be. Next, CVD (Chemical Vapor
A phosphosilicate glass (hereinafter abbreviated as PSG) layer is formed on the entire surface using a deposition method to form the lower insulating film 4, and a heat-resistant resin layer 5 is applied on the entire surface at 120℃.
After heat treatment for 30 minutes and then at 300° C. for 30 minutes, control etching is performed to uniformly depth the entire surface, and an upper insulating film 6 is further formed on the entire surface. Then, through holes passing through the upper and lower insulating films 4 and 6 are opened to form an upper wiring layer 7. The above is based on patent application No. 59-021835. [Problem to be solved by the invention] In the above process, control etching is performed after heat treatment at 300°C for 30 minutes.
At 300°C, the resin is not treated sufficiently, so the growth of the insulating film after controlled etching (~
At a growth temperature of approximately 450℃, the methyl groups and OH groups contained in the resin decompose and gas is generated. This gas has no escape because there is an insulating film on the upper layer.
It accumulates in the resin layer, eventually leading to the rupture of the insulating film and causing a defect called bubbling. the temperature at which the resin is sufficiently heat treated to prevent this phenomenon;
For example, if the temperature is raised to about 400°C, a problem arises in that cracks occur in thick parts of the resin film due to volumetric shrinkage. The incidence of bubbling and cracking in the above process is high, and can result in 70 to 80% product defects. The present invention aims to solve these problems. [Means for Solving the Problems] In order to solve the above problems, the present invention includes a process of depositing an insulating film on a substrate having an electrode wiring pattern on the surface, and coating the entire surface with a heat-resistant resin solution. a step of performing a first heat treatment to remove the solvent in the heat-resistant resin solution; and a step of performing etching at approximately the same etching rate for the heat-resistant resin and the insulating film; A step of thinning the heat-resistant resin to a film thickness that does not cause cracks in a second heat treatment performed at a higher temperature than the heat treatment of This is achieved by manufacturing to include a step of performing a second heat treatment. [Function] In the above method for forming an interlayer insulating film, the first heat treatment is performed at a low temperature (200° C. or lower) that can remove the solvent contained in the heat-resistant resin. In the example, the solvent contained in polyladder organosiloxane (hereinafter abbreviated as PLOS), ethylene glycol monobutyl ether acetate, can be removed. Next, the heat-resistant resin layer and the insulating film are etched at the same etching speed, and the entire surface is etched to a uniform depth using reactive ion etching to make the heat-resistant resin layer thin (it is preferable to avoid flat areas). As a result, the surfaces of the heat-resistant resin and the insulating film can be made smooth. After this, high temperature (400
The second heat treatment is carried out at a temperature of 10.degree. C. or above), but since the film thickness is reduced by etching the entire surface, the effect of volumetric shrinkage is reduced and the occurrence of cracks is suppressed. Therefore, heat treatment at a higher temperature than in the conventional example is possible, and methyl groups and the like contained in the resin can be scattered to the outside by this high temperature heat treatment. [Example] An explanation will be given with reference to FIGS. 1 to 6. In FIG. 1, for example, CVD (Chemical Vapor
After forming the SiO 2 film 12 using a deposition method, the lower wiring layer 13 is formed with aluminum (Al) to a thickness of 1.0 μm. The wiring material may be gold, tungsten, etc. In FIG. 2, the lower wiring layer 13 and the
Phosphorsilicate glass (hereinafter abbreviated as PSG) is formed on the SiO 2 film 12 to a thickness of 0.7 μm using the CVD method to form the lower insulating film 14 . The insulating material may be a silicon nitride film, silicon dioxide, etc. instead of PSG. In FIG. 3, a heat-resistant resin PLOS15 (Poly-Ladder-Organo-
Siloxane) was applied using a spinner and laminated so that the film thickness t on the flat part was 0.5 μm.
A first heat treatment is performed at ℃ for 30 to 60 minutes to remove residual solvents such as ethylene glycol monobutyl ether acetate contained in the resin. Polyimide, heat-resistant photoresist, etc. may be used instead of this resin. In FIG. 4, the entire surface of the heat-resistant resin is subjected to reactive ion etching (hereinafter abbreviated as RIE) in a mixed gas of carbon tetrafluoride (CF 4 ) and trifluoromethane (CHF 3 ). At this time, the etching rates of the lower insulating film 14 and the resin layer 15 are set to be equal to 0.5 to 0.5.
Perform control etching of about 0.7μm. Etching is performed until the resin remains only on the stepped portions. At this time, the thickness of the resin at the stepped portion is 0.3 to 0.5 μm. Control etching conditions are selected depending on the materials of the lower insulating film and heat-resistant resin. In FIG. 5, the resin layer 15 is flattened by controlled etching and left only in the recesses, and is then subjected to a second heat treatment at 400 to 450°C for 30 to 30 minutes.
Apply for 60 minutes to ensure compositional stability. Next, an upper insulating film 16 is formed by CVD. In FIG. 6, a through hole is formed in the electrode part using a photolithography method, and an upper wiring layer 17 is formed.
Multilayer wiring is performed in the same manner thereafter. According to the above method, it is possible to eliminate product defects due to cracking and bubbling phenomena, which occur at a rate of 70 to 80% in conventional heat treatments. [Table 1] shows that in the process shown in the example, 5
This is the result of investigating the dependence of the number of cracks generated per cm 2 on the coating film thickness t in the flat area of PLOS and the temperature of the second heat treatment for 60 minutes. According to this table, it can be seen that when the second heat treatment temperature is 400° C., cracks will not occur if the coating film thickness t on the flat portion is 0.2 μm or less. Conditions below 300°C cannot be used because bubbling occurs during the subsequent step of growing an insulating film using the CVD method.
以上説明したように本発明のごとく第１の熱処
理後耐熱性樹脂と絶縁膜のエツチング速度を等し
くしてコントロールエツチングを行えば、樹脂及
び絶縁膜表面を平坦に保ちつつ、樹脂膜厚を薄く
することが可能となるので、従来より高温で第２
の熱処理を行つてもクラツクは発生しない。
また、第２の熱処理が従来よりも高温で行なえ
るので、後工程でCVD法等により絶縁膜を成長
してもバブリング現象が起きることもない。
本工程を採用した結果、クラツク，バブリング
現象の不良を回避できる。
As explained above, if controlled etching is performed by equalizing the etching speed of the heat-resistant resin and the insulating film after the first heat treatment as in the present invention, the resin film thickness can be reduced while keeping the surfaces of the resin and the insulating film flat. This makes it possible to perform the second
Cracks do not occur even after heat treatment. Furthermore, since the second heat treatment can be performed at a higher temperature than conventional methods, bubbling does not occur even when an insulating film is grown by CVD or the like in a subsequent process. As a result of adopting this process, defects such as cracks and bubbling phenomena can be avoided.
第１図〜第６図は本発明の実施例における各工
程の配線部断面図、第７図は従来方法における完
成した配線断面図である。
１１…半導体基板、１２…SiO2膜、１３…下
層配線層、１４…下層絶縁膜、１５…耐熱性樹
脂、１６…上層絶縁膜、１７…上層配線層。
1 to 6 are cross-sectional views of wiring portions in each step in an embodiment of the present invention, and FIG. 7 is a cross-sectional view of completed wiring in a conventional method. DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, 12... SiO2 film, 13... Lower layer wiring layer, 14... Lower layer insulating film, 15... Heat resistant resin, 16... Upper layer insulating film, 17... Upper layer wiring layer.
Claims (1)
絶縁膜を被着する工程と、 全面に耐熱性樹脂溶液を塗布する工程と、 該耐熱性樹脂溶液中の溶媒除去のための第一の
熱処理を行う工程と、 該耐熱性樹脂及び該絶縁膜のエツチング速度を
ほぼ等しくしてエツチングを施し、少なくとも後
に前記第一の熱処理よりも高い温度で行う第二の
熱処理においてクラツクが生じない膜厚になるま
で該耐熱性樹脂を薄膜化する工程と、 該耐熱性樹脂中の、熱処理により気化する成分
を除去するための第二の熱処理を行う工程とを含
むことを特徴とする層間絶縁膜の形成方法。[Claims] 1. On a substrate having an electrode wiring pattern on its surface,
a step of applying an insulating film; a step of applying a heat-resistant resin solution to the entire surface; a step of performing a first heat treatment to remove the solvent in the heat-resistant resin solution; and a step of applying the heat-resistant resin and the insulating film. etching the heat-resistant resin at approximately the same etching rate, and thinning the heat-resistant resin to a film thickness that does not cause cracks at least in a second heat treatment performed later at a higher temperature than the first heat treatment; A method for forming an interlayer insulating film, comprising the step of performing a second heat treatment to remove components vaporized by heat treatment in the heat-resistant resin.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59223351A JPS61116858A (en) | 1984-10-24 | 1984-10-24 | Formation of interlaminar insulating film |
| KR1019850000744A KR900004968B1 (en) | 1984-02-10 | 1985-02-06 | Method for semiconductor device |
| US06/698,901 US4654113A (en) | 1984-02-10 | 1985-02-06 | Process for fabricating a semiconductor device |
| DE8585300829T DE3586109D1 (en) | 1984-02-10 | 1985-02-08 | METHOD FOR PRODUCING A CONNECTION STRUCTURE FROM A SEMICONDUCTOR ARRANGEMENT. |
| EP85300829A EP0154419B1 (en) | 1984-02-10 | 1985-02-08 | Process for producing an interconnection structure of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59223351A JPS61116858A (en) | 1984-10-24 | 1984-10-24 | Formation of interlaminar insulating film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61116858A JPS61116858A (en) | 1986-06-04 |
| JPH0329298B2 true JPH0329298B2 (en) | 1991-04-23 |
Family
ID=16796799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59223351A Granted JPS61116858A (en) | 1984-02-10 | 1984-10-24 | Formation of interlaminar insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61116858A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0669038B2 (en) * | 1984-12-19 | 1994-08-31 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| JPS61196555A (en) * | 1985-02-26 | 1986-08-30 | Nec Corp | Formation for multilayer interconnection |
| FR2588418B1 (en) * | 1985-10-03 | 1988-07-29 | Bull Sa | METHOD FOR FORMING A MULTI-LAYER METAL NETWORK FOR INTERCONNECTING THE COMPONENTS OF A HIGH DENSITY INTEGRATED CIRCUIT AND RESULTING INTEGRATED CIRCUIT |
| JPS62295437A (en) * | 1986-06-14 | 1987-12-22 | Yamaha Corp | Forming method for multilayer interconnection |
| JPH03201438A (en) * | 1989-12-28 | 1991-09-03 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| KR970023723A (en) * | 1995-10-20 | 1997-05-30 | 김주용 | Metal wiring method of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5768050A (en) * | 1980-10-15 | 1982-04-26 | Hitachi Ltd | Multilayer wire structure and manufacture thereof |
-
1984
- 1984-10-24 JP JP59223351A patent/JPS61116858A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5768050A (en) * | 1980-10-15 | 1982-04-26 | Hitachi Ltd | Multilayer wire structure and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61116858A (en) | 1986-06-04 |
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| EXPY | Cancellation because of completion of term |