JPS61154148A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61154148A
JPS61154148A JP27686284A JP27686284A JPS61154148A JP S61154148 A JPS61154148 A JP S61154148A JP 27686284 A JP27686284 A JP 27686284A JP 27686284 A JP27686284 A JP 27686284A JP S61154148 A JPS61154148 A JP S61154148A
Authority
JP
Japan
Prior art keywords
layer
material
lift
formed
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27686284A
Inventor
Toshio Kurahashi
Kazuaki Tsukuda
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27686284A priority Critical patent/JPS61154148A/en
Publication of JPS61154148A publication Critical patent/JPS61154148A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE:To make it possible to form a highly accurate pattern, by coating the pattern formed on a substrate by a lift-off material, performing etching, burying the recess part of the substrate with a heat resisting insulating material, removing the lift-off material, and coating the entire surface of the substrate by a silicone resin and phosphorus silicate glass. CONSTITUTION:A wiring pattern 2 is coated by a lift-off material 3. Thereafter, a silicon dioxide (SiO2) layer 14 is formed by bias sputter etching. A gap be tween the wiring patterns 2 is buried by the SiO2 layer 14, but the upper part is formed in an inverted mountain shape having a 45-degree slant surface owing to the characteristic of the bias sputter etching. A switch 15 for connecting a target 7 and a high frequency power source 9 is provided. With the 45-degree slant surface forming the inverted mountain shape as the maximum value, the etching of the SiO2 layer 14 is made to progress. Therefore, the gap between the wiring patterns 2 is buried by the SiO2 layer 15. The thickness of the layer 15 can be approximated to the thickness of the wiring pattern 2. Then the lift-off material 13 is dissolved and removed by a solvent, and the silicone resin layer 16 is flattened. Then a PSG layer 17 is formed.
JP27686284A 1984-12-27 1984-12-27 Manufacture of semiconductor device Pending JPS61154148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27686284A JPS61154148A (en) 1984-12-27 1984-12-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27686284A JPS61154148A (en) 1984-12-27 1984-12-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61154148A true JPS61154148A (en) 1986-07-12

Family

ID=17575445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27686284A Pending JPS61154148A (en) 1984-12-27 1984-12-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61154148A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162261A (en) * 1990-12-05 1992-11-10 Texas Instruments Incorporated Method of forming a via having sloped sidewalls
JP2008004934A (en) * 2006-06-22 2008-01-10 Macronix Internatl Co Ltd Stacked nonvolatile memory device, and method for fabricating the same
JP2008098602A (en) * 2006-10-13 2008-04-24 Macronix Internatl Co Ltd Laminated thin film transistor type nonvolatile memory device and method of manufacturing thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162261A (en) * 1990-12-05 1992-11-10 Texas Instruments Incorporated Method of forming a via having sloped sidewalls
JP2008004934A (en) * 2006-06-22 2008-01-10 Macronix Internatl Co Ltd Stacked nonvolatile memory device, and method for fabricating the same
JP2008098602A (en) * 2006-10-13 2008-04-24 Macronix Internatl Co Ltd Laminated thin film transistor type nonvolatile memory device and method of manufacturing thereof

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