KR20010003577A - Method of forming an inter-layer insulating film in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming an interlayer insulating film of a semiconductor device is provided to achieve the uniform flat feature of the semiconductor device by adjusting the spin speed of the coating process. CONSTITUTION: A plurality of metal wires(42) having the different aspect ratio are formed on a semiconductor substrate(41). An insulating film(43) is formed along the plurality of metal wires(42). Then, the first spin on glass film(44) is formed on a gap portion by carrying out the first spin on glass coating process with a low spin speed. After that, the second spin on glass film(45) having a flat surface is formed by carrying out the second spin on glass coating process with a high spin speed. In the first spin on glass coating process, the spin on glass chemical is injected for 2 to 4 seconds.

Description

Method of forming an inter-layer insulating film in a semiconductor device

The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and in particular, spin-on-glass (SOG) coating process proceeds in two steps, the spin speed of the first and second coating process (spin speed) is adjusted to the metal The present invention relates to a method for forming an interlayer insulating film of a semiconductor device capable of obtaining uniform and excellent gap filling and planarization characteristics regardless of whether the aspect ratio of the wiring is high or low.

In general, in the manufacturing process of a semiconductor device, the interlayer insulating film is used for the purpose of electrical insulation and planarization between the device and the device or the conductive layer and the conductive layer, and also as a protective film to protect the device from the external environment. do. However, the gap between wirings becomes deeper and deeper due to the decrease in the size of the device due to the higher integration of semiconductor devices. Therefore, the gap required when forming an interlayer insulating film by conventional plasma enhanced chemical vapor deposition (PE-CVD) is required. Since the filling and flattening properties cannot be obtained, an interlayer insulating film structure including an SOG film exhibiting excellent gap filling and flattening properties is used. As the semiconductor devices become more integrated, the gap between patterns becomes narrower, and thus, a double coating method is applied because the gap filling and planarization characteristics cannot be obtained by the one-step coating method in the SOG coating process.

On the other hand, in the SOG coating process, the SOG buried aspect is changed by the spin speed and the aspect ratio, which will be described with reference to FIGS. 1 and 2.

1 is a cross-sectional view for explaining a buried aspect of SOG according to aspect ratio in a state in which spin speed is kept constant.

A plurality of metal wires 12 are formed on the substrate 11 on which various elements for forming a semiconductor element are formed. The plurality of metal wires 12 has a high aspect ratio portion 12a and a low aspect ratio portion 12b. In this state, when the SOG coating process is performed while maintaining a constant spin speed, the gap filling is easily performed by the SOG film 13 in the low aspect ratio portion 12b, but SOG in the high aspect ratio portion 12a. The amount by which the membrane 13 is filled is small.

2 is a cross-sectional view for explaining a buried aspect of SOG according to spin speed in a state having a high aspect ratio.

A plurality of metal wires 22 are formed on the substrate 21 on which various elements for forming a semiconductor element are formed. Many metal wires 22 have only first and second high aspect ratio portions 22a and 22b. In this state, when the SOG coating process is performed at different spin speeds, the gap filling is easily performed by the SOG film 23 in the first high aspect ratio portion 22a to which the low spin speed is applied. In the high aspect ratio portion 22b to which high spin speed is applied, the amount of filling of the SOG film 23 is reduced.

3A and 3B are cross-sectional views of devices for explaining a method of forming an interlayer insulating film of a conventional semiconductor device.

Referring to FIG. 3A, a plurality of metal wires 32 are formed on a substrate 31 on which various elements for forming a semiconductor device are formed. The plurality of metal wires 32 have a high aspect ratio portion 32a and a low aspect ratio portion 32b. An insulating film 33 having excellent insulating properties is formed along the surface portion of the substrate 31 including the plurality of metal wires 32. The first SOG film 34 is formed by the primary SOG coating process for the purpose of filling the plurality of metal wires 32.

Referring to FIG. 3B, a second SOG film 35 is formed on the first SOG film 34 by a second SOG coating process for the purpose of surface planarization.

The SOG film double coating process described above applies the same first and second coating process conditions. That is, the first SOG film 34 serves to fill the gap formed between the metal lines 32, and the second SOG film 35 serves to planarize the surface. The thickness of the SOG film is controlled by the spin speed, and a method using a high spin speed with a spin speed of 3500 to 3700 rpm based on a 2000 kW thickness has been applied to the process.

In the case of the metal wiring 32 formed by the etching process, the width and the height of the metal wiring 32 are the topologies due to the lower layer formed before the metal wiring 32 is formed, and the reasons for the design of the semiconductor device. As a result, it is very uneven throughout the wafer, and the aspect ratio of the metal wiring 32 appears very differently throughout the wafer depending on such nonuniformity.

In the case of the metal wiring 32 in which the portions 32a and 32b having such different aspect ratios exist, when applying the high spin speed (for example, 3500 to 3700 rpm) that is generally applied, it is shown in FIG. 3A. As described above, the gap filling is easily performed by the first SOG film 34 in the low aspect ratio portion 32b, but the amount of filling the first SOG film 34 in the high aspect ratio portion 32a is small. As shown in FIG. 3B, the planarization characteristics required for the second SOG coating process may not be obtained. Therefore, there is a disadvantage in that the planarization characteristic of the SOG film is uneven depending on the aspect ratio of the metal wiring.

Therefore, the present invention proceeds spin-on-glass (SOG) coating process in two stages, uniform and excellent gap filling regardless of the high and low aspect ratio of the metal wiring by adjusting the spin speed of the first and second coating process And a method for forming an interlayer insulating film of a semiconductor device capable of obtaining planarization characteristics.

Method for forming an interlayer insulating film of a semiconductor device of the present invention for achieving the above object comprises the steps of providing a substrate on which a plurality of metal wirings having different aspect ratio; Forming an insulating film along a surface portion of the substrate including the plurality of metal wires; Performing a first SOG coating process at a low spin speed to form a first SOG film in the gap portion; And forming a second SOG film having a flat surface by performing a second SOG coating process at a high spin speed.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view for explaining a buried aspect of SOG according to aspect ratio in a state in which spin speed is kept constant.

2 is a cross-sectional view for explaining a buried aspect of SOG according to spin speed in a state having a high aspect ratio.

3A and 3B are cross-sectional views of a device for explaining a method of forming an interlayer insulating film of a conventional semiconductor device.

4A and 4B are cross-sectional views of devices for explaining a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 21, 31, 41: substrate 12, 22, 32, 42: metal wiring

12a, 32a, 42a: high aspect ratio portion

12b, 32b, 42b: low aspect ratio 13, 23: SOG film

22a and 22b: first and second high aspect ratio portions

33, 43: insulating film 34, 44: first SOG film

35, 45: second SOG film

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Before describing the embodiment of the present invention, once again, the SOG buried aspect is changed by the spin speed and the aspect ratio, so that the gap filling of the SOG film at the low aspect ratio is easy and high when the spin speed is constant. In the aspect ratio portion, the gap filling of the SOG film is poor, and in the high aspect ratio portion where the low spin speed is applied, the gap filling is relatively easy by the SOG film, but the SOG layer is filled in the high aspect ratio portion where the high spin speed is applied. Less amount

4A and 4B are cross-sectional views of devices for describing a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, a plurality of metal wires 42 are formed on a substrate 41 on which various elements for forming a semiconductor device are formed. The plurality of metal wires 42 have a high aspect ratio portion 42a and a low aspect ratio portion 42b. An insulating film 43 having excellent insulating properties is formed along the surface portion of the substrate 41 including the plurality of metal wires 42. The first SOG film 44 is formed by the primary SOG coating process for the purpose of filling the plurality of metal wires 42.

In the above, the SiON film of the plasma enhanced chemical vapor deposition system is mainly used as the insulating film 43. The primary SOG coating process allows for lower spin speeds, e.g., 2500 to 2900 rpm, while dispensing SOG chemicals at flow rates of 1 to 2.5 cc / sec for 2 to 4 seconds. The coating is adjusted to a thickness of 2700 to 3200 mm 3. The first SOG film 44 coated under these conditions achieves good gap filling in both the high aspect ratio portion 42a and the low aspect ratio portion 42b.

Referring to FIG. 4B, a second SOG film 45 is formed on the first SOG film 44 by a second SOG coating process for the purpose of surface planarization.

In the above, the secondary SOG coating process allows for a high spin speed, for example, 3700 while dispensing SOG chemicals at a flow rate of 1 to 2.5 cc / sec for 2 to 4 seconds. It is adjusted to 4400rpm to coat a thickness of 1500 to 2000Å. The second SOG film 44 coated under these conditions achieves good surface planarization in both the high aspect ratio portion 42a and the low aspect ratio portion 42b.

In the above-described embodiment of the present invention, the spin speed is adjusted low during the first SOG coating during the dual coating SOG process to achieve uniform and excellent gap filling regardless of the aspect ratio of the metal wiring, and the spin speed during the second SOG coating. To increase the uniform planarization characteristics. This is based on the principle as described with reference to FIGS. 1 and 2.

As described above, the present invention enables uniform gap filling and surface planarization regardless of aspect ratio, thereby improving reliability of semiconductor devices, thereby improving competitiveness, and applying existing equipment without additional equipment investment. There is an advantage.

Claims (3)

Providing a substrate on which a plurality of metal wires having different aspect ratios are formed; Forming an insulating film along a surface portion of the substrate including the plurality of metal wires; Performing a first SOG coating process at a low spin speed to form a first SOG film in the gap portion; And And forming a second SOG film having a flat surface by performing a secondary SOG coating process at a high spin speed. The method of claim 1, The first SOG coating process is an interlayer of a semiconductor device, characterized in that the coating of the SOG chemicals at a thickness of 2700 to 3200 kPa at a spin speed of 2500 to 2900 rpm with a flow rate of 1 to 2.5 cc / sec for 2 to 4 seconds Method of forming insulating film. The method of claim 1, The second SOG coating process is an interlayer of a semiconductor device, characterized in that the coating of the SOG chemicals at a thickness of 1500 to 2000 kPa at a spin speed of 3700 to 4400 rpm with a flow rate of 1 to 2.5 cc / sec for 2 to 4 seconds Method of forming an insulating film.