KR100197118B1 - Method of forming interconnector in semiconductor device - Google Patents
Method of forming interconnector in semiconductor device Download PDFInfo
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- KR100197118B1 KR100197118B1 KR1019950048302A KR19950048302A KR100197118B1 KR 100197118 B1 KR100197118 B1 KR 100197118B1 KR 1019950048302 A KR1019950048302 A KR 1019950048302A KR 19950048302 A KR19950048302 A KR 19950048302A KR 100197118 B1 KR100197118 B1 KR 100197118B1
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- contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Abstract
본 발명은 콘택홀의 크기가 다른 반도체 소자에서 금속배선막을 형성하는 방법을 제공하기 위한 것이다.The present invention is to provide a method for forming a metal wiring film in a semiconductor device having a different contact hole size.
이와 같은 본 발명의 반도체 소자의 금속배선막 형성방법은 다층금속배선을 갖는 반도체 소자에 있어서, 반도체 기판 위에 형성된 절연막의 소정 부분에 제1 콘택홀(또는 비아홀)을 형성하는 단계; 제1 콘택홀에 제1 금속막을 증착하는 단계; 증착된 제1 금속막을 콘택 부분의 제1 플러그만 남기도록 전면식각하는 단계; 매립된 플러그중 특정 플러그의 바로 옆 부분에 제2 콘택홀(또는 비아홀)을 형성하는 단계; 금속막을 제2 콘택홀을 포함한 전면에 증착하고 제2 플러그만 남기도록 전면식각하는 단게; 결과적인 구조의 전면에 제2 금속막을 형성하는 단계를 포함하는 것을 특징으로 한다.Such a method for forming a metal wiring film of a semiconductor device according to the present invention includes the steps of: forming a first contact hole (or via hole) in a predetermined portion of an insulating film formed on a semiconductor substrate in a semiconductor device having a multilayer metal wiring; Depositing a first metal film in the first contact hole; Etching the deposited first metal film to leave only the first plug of the contact portion; Forming a second contact hole (or via hole) in a portion next to the specific plug among the embedded plugs; Depositing a metal film on the entire surface including the second contact hole and etching the entire surface to leave only the second plug; And forming a second metal film on the entire surface of the resulting structure.
Description
제1도는 본 발명의 실시예에 따른 반도체 소자에 있어서, 금속배선막을 형성하는 방법을 설명하는 공정 단면도.1 is a cross-sectional view illustrating a method of forming a metal wiring film in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 도전층1 silicon substrate 2 conductive layer
3 : 산화막 4, 6` : 텅스텐 플러그3: oxide film 4, 6`: tungsten plug
5 : 감광막 6 : 텅스텐5: photosensitive film 6: tungsten
7 : 제1금속망 8 : 제2금속망7: first metal mesh 8: second metal mesh
9 : 제3금속망9: third metal mesh
본 발명은 반도체 소자의 금속배선망 형성방법에 관한 것으로, 특히 인접하는 큰택홀(또는 비아홀)의 크기가 다른 경우에 있어서, 금속배선막을 형성하는 반도체 소자의 금속배선막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal interconnection network of a semiconductor device, and more particularly to a method for forming a metal interconnection film for a semiconductor device for forming a metal interconnection film when the sizes of adjacent large trench holes (or via holes) are different.
일반적으로 막의 증착에 사용되는 증착공정이라 함은 기상의 소스로부터 특정 원자나 분자를 고상화시켜 필요로 하는 박막을 얻어내는 일종의 물질 합성과정을 통칭한다. 반도체 소자의 제조에는 다결정 실리콘, 산화막, 질화막, 여러 종류의 금속 혹은 실리사이는 박막이 필요하며 이와 같은 박막들은 모두 증착공정에 의해서 형성된다.In general, the deposition process used for the deposition of a film refers to a kind of material synthesis process in which a specific atom or molecule is solidified from a gaseous source to obtain a required thin film. In the manufacture of semiconductor devices, thin films are required between polycrystalline silicon, oxide film, nitride film, and various kinds of metals or silicides, all of which are formed by a deposition process.
증착공정은 박막형성법(Thin Film Procrss)이라고 말할 수 있으며, 이는 크게 물리증착법(Physical Vapor Deposition: PVD)과 화학증착법(Chemical Vapor Deposition)으로 대별된다. 물리증착은 소스부터 임의 다른 성분이 더해지거나 감해지지 않고 상의 변환과정만을 통하여 증착되는 것이다. 반면에 화학증착은 화학반응을 수반하기 때문에 소스와 증착산물간의 물리화학적 구조의 차이가 있다.The deposition process may be referred to as thin film formation, which is roughly classified into physical vapor deposition (PVD) and chemical vapor deposition (Chemical Vapor Deposition). Physical vapor deposition is deposited only through the conversion of the phase without adding or subtracting any other components from the source. On the other hand, because chemical deposition involves chemical reactions, there is a difference in physicochemical structure between the source and the deposition product.
이러한 증착공정을 이용하여 반도체 소자에 사용되는 구성막으로는 크게 절연막과 도전막으로 구성되고, 절연막으로는 SiO2, PSG, BPSG 와 같은 산화막과 Si3N4와 같은 질화막이 있으며, 물리화학증착법중의 일종인 회전도포법(spin coating)의 원리를 이용한 SOG(Spin On Glass)와 PIQ(Polyimide)가 있는데, SOG는 무기계의 실리케이트(Sillicate) SOG와 유기계의 실록산(Siloxine) SOG가 있다. 이러한 SOG는 주로 금속간 유전체(Intermetal Dielectric)용으로 적용된다. 한편, 폴리이미드는 평탄화 능력이 우수한 다층배선 층간 절연막으로서, 두꺼운 막이 가능해서 알파선 저지막으로도 쓰인다.The constituent film used for the semiconductor device using this deposition process is largely composed of an insulating film and a conductive film, and the insulating film includes an oxide film such as SiO 2, PSG, BPSG, and a nitride film such as Si 3 N 4 . SG (Spin On Glass) and PIQ (Polyimide) using the principle of spin coating, which is a kind of SOG, include inorganic silicate SOG and organic siloxane SOG. Such SOG is mainly applied for intermetal dielectrics. On the other hand, polyimide is a multi-layered wiring interlayer insulating film having excellent planarization capability, and can be used as an alpha ray blocking film because a thick film is possible.
반도체 소자의 제조에 있어서, 신호전달 및 전원인가 등을 위해서 형성되는 금속배선막은 집적도의 증가로 인하여 배선자체의 선폭 감소 및 배선간의 간격이 점점 좁아지게 된다. 이러한 배선막을 콘택홀(또는 비아홀, 이하 콘택홀로 표시한 것은 비아홀의 경우도 포함한다)을 포함하는 소정부분에 형성할 때, 콘택홀의 크기가 서로 다르면 금속막의 증착두께를 크기가 큰 콘택홀을 기준으로 하여 결정하게된다. 이로 인하여 글로벌 단차 영역에서는 두꺼운 금속막이 형성되므로, 잔류 텅스텐의 제거가 어려우며, 특히 콘택홀을 매립하는 금속막으로서 텅스텐을 사용하는 경우에는 더욱 어렵다. 또한 텅스텐막이 들뜨게 되는 리프팅 현상의 발생가능성이 높으며, 아울러 두께의 증가로 인하여 표면거칠기가 증가하여 텅스텐의 전면 식각시 식각율의 균일성(uniformity)과 재현성(Repeatibility)이 감소하는 문제점이 존재한다.In the manufacture of semiconductor devices, metal wiring films formed for signal transmission, power supply, and the like become increasingly narrower in line width and wiring spacing due to an increase in the degree of integration. When such a wiring film is formed in a predetermined portion including a contact hole (or a via hole (hereinafter, also referred to as a via hole)), when the contact holes are different in size, the deposition thickness of the metal film is referred to as a large contact hole. Will be decided by. Because of this, since a thick metal film is formed in the global stepped region, it is difficult to remove residual tungsten, especially when tungsten is used as a metal film to fill contact holes. In addition, there is a high possibility of the lifting phenomenon in which the tungsten film is lifted, and the surface roughness increases due to the increase in thickness, thereby reducing the uniformity and reproducibility of the etching rate during the entire surface etching of tungsten.
따라서, 본 발명의 목적은 크기가 다른 금속배선막을 형성할 때, 먼저 작은 크기의 홀을 기준으로 홀을 형성하여 1차로 금속 플러그를 형성하고, 크기가 큰 홀의 경우 기존의 홀에 인접하는 홀을 형성하여 플러그를 형성하므로서 원하는 크기의 콘택을 형성할 수 있는 반도체 소자의 금속배선막 형성방법을 제공하기 위한 것이다.Accordingly, an object of the present invention is to form a metal plug primarily by forming a hole based on a hole of a small size when forming a metal wiring film having a different size, and in the case of a hole having a large size, a hole adjacent to an existing hole is formed. The present invention provides a method for forming a metal wiring film of a semiconductor device that can form a plug by forming a plug.
이와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 금속배선막 형성방법은 다층금속배선을 갖는 반도체 소자에 있어서, 반도체 기판 위에 형성된 절연막의 소정 부분의 제1 콘택홀(또는 비아홀)을 형성하는 단계; 제1 콘택홀에 제1 금속막을 증착하는 단계; 증착된 제1 금속막을 콘택 부분의 제1 플러그만 남기도록 전면식각하는 단계; 매립된 플러그 중 특정 플러그의 바로 옆 부분에 제2 콘택홀(또는 비아홀)을 형성하는 단계; 금속막을 제2 콘택홀을 포함한 전면에 증착하고 제2 플러그만 남기도록 전면 식각하는 단계; 결과적인 구조의 전면에 제2 금속막을 형성하는 단계를 포함하는 단계를 포함하는 것을 특징으로 한다.In the semiconductor device forming method of the semiconductor device of the present invention for achieving the above object, in the semiconductor device having a multi-layered metal wiring, forming a first contact hole (or via hole) of a predetermined portion of the insulating film formed on the semiconductor substrate ; Depositing a first metal film in the first contact hole; Etching the deposited first metal film to leave only the first plug of the contact portion; Forming a second contact hole (or via hole) in a portion of the buried plug immediately next to a specific plug; Depositing a metal layer on the entire surface including the second contact hole and etching the entire surface to leave only the second plug; And forming a second metal film on the entire surface of the resulting structure.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
첨부한 도면은 본 발명의 실시예에 따른 금속배선막 형성방법을 설명하기 위한 공정 흐름도이다.The accompanying drawings are a process flow diagram for explaining a metal wiring film forming method according to an embodiment of the present invention.
먼저, 첨부한 도면의 (a)에 도시한 것처럼, 실리콘 기판(1) 상이나 내부에 이온주입된 실리콘 또는 알루미늄이나 구리 등의 금속물질로 이루어진 도전층(2)을 형성한 다음에 산화막(3)을 그 위에 증착한다. 상기 산화막(3)의 소정 부위에 콘택홀(10)을 형성한다. 상기 콘택홀(또는 비아홀)(10)은 일반적인 포토마스킹 및 식각공정에 의하여 형성된다. 상기 콘택홀이나 비아홀의 형성 후에는 포토마스킹을 위하여 형성한 감광막 패턴을 완전히 제거한다. 여기서, 형성되는 콘택홀의 직경은 최종 콘택홀의 직영이 아니라 최종 콘택홀에서 직경이 작은 콘택홀을 기준으로 한다.First, as shown in (a) of the accompanying drawings, the conductive layer 2 made of silicon or a metal material such as aluminum or copper implanted into or on the silicon substrate 1 is formed, followed by the oxide film 3 Is deposited on it. The contact hole 10 is formed in a predetermined portion of the oxide film 3. The contact hole (or via hole) 10 is formed by a general photomasking and etching process. After the formation of the contact hole or the via hole, the photoresist pattern formed for photomasking is completely removed. Here, the diameter of the contact hole to be formed is based on the contact hole having a small diameter in the final contact hole, not directly running the final contact hole.
콘택홀의 형성 후, 텅스텐을 화학기상증착법으로 산화막(3)의 전면에 증착한다. 상기 콘택홀에 텅스텐을 증착하기 전에 홀의 벽면에 홀의 형태를 유지할 수 있는 정도의 두께만큼 금속막을 스퍼터링 방법으로 형성한다. 이때의 금속막은 티타늄, 티타늄나이트라이드, 탄탈륨, 몰리브듐, 티타늄텅스텐 중의 하나중 택일하여 사용하는 것이 가능하다.After the formation of the contact holes, tungsten is deposited on the entire surface of the oxide film 3 by chemical vapor deposition. Prior to depositing tungsten in the contact hole, a metal film is formed by a sputtering method to a thickness sufficient to maintain the shape of the hole on the wall of the hole. At this time, the metal film can be used in one of titanium, titanium nitride, tantalum, molybdium, and titanium tungsten.
한편, 증착된 텅스텐을 화학적 기계적 연마(Chemical Mechanical Polishing: CMP)법으로 전면식각하여 콘택내부의 플러그(4)만을 남긴다.Meanwhile, the deposited tungsten is etched by chemical mechanical polishing (CMP) to leave only the plug 4 inside the contact.
플러그(4)를 포함한 산화막(3)의 전면에 감광막을 도포하고, 노광과 현상공정을 통하여 (b)와 같은 감광막 패턴을 형성한다. 이때의 감광막 패턴은 최종 콘택홀의 직경이 크지만 제1 콘택홀 형성단계에서 최종 직경보다 적게 형성된 콘택과, 상기 콘택의 옆 부분이 노출되도록 한다.A photosensitive film is coated on the entire surface of the oxide film 3 including the plug 4, and a photosensitive film pattern as shown in (b) is formed through the exposure and development processes. At this time, the photoresist pattern has a large diameter of the final contact hole, but a contact formed less than the final diameter in the first contact hole forming step and a side portion of the contact are exposed.
노출된 산화막을 식각하여 제2의 콘택홀(20)을 형성하고, 감광막 패턴은 완전히 제거한다. 식각된 제2의 콘택홀(20)과 이미 형성된 플러그(4)를 포함한 산화막의 전면에 텅스텐(6)을 화학기상증착법으로 (c)와 같이 증착한다.The exposed oxide film is etched to form the second contact hole 20, and the photoresist pattern is completely removed. Tungsten 6 is deposited on the entire surface of the oxide film including the etched second contact hole 20 and the plug 4 already formed by chemical vapor deposition as shown in (c).
다음으로, (d)와 같이 증착된 텅스텐(6)에서 제2의 콘택홀(20)을 제외한 부분에 형성된 텅스텐막을 전면식각 방법에 의하여 제거한다. 이 때의 전면 식각방법은 전 단계의 경우와 마찬가지로 화학적 기계적 연마법을 이용한다. 상기 전면 식각공정에 의하여 제2의 플러그(6`)가 형성된다.Next, the tungsten film formed in the portion of the tungsten 6 deposited as shown in (d) except for the second contact hole 20 is removed by the front etching method. At this time, the entire surface etching method uses a chemical mechanical polishing method as in the previous step. The second plug 6 ′ is formed by the front etching process.
한편, 상기 제2의 콘택홀(20)을 텅스텐으로 바로 매립하기 전에, 제1의 콘택홀(10)을 매립하는 경우와 마찬가지로, 상기 콘태홀에 텅스텐을 증착하기 전, 홀의 벽면에 홀의 형태를 유지할 수 있는 정도의 두께만큼 금속막을 스퍼터링 방법으로형성한다. 이 때의 금속막은 티타늄, 티타늄나이트라이드, 탄날륨, 몰리브듐, 티타늄텅스텐 중의 하나중 택일하여 사용하는 것이 가능하다.On the other hand, before filling the second contact hole 20 directly with tungsten, as in the case of filling the first contact hole 10, before depositing tungsten in the contact hole, the shape of the hole on the wall surface of the hole The metal film is formed by the sputtering method to a thickness that can be maintained. The metal film at this time can be used by using one of titanium, titanium nitride, tanallium, molybdium, and titanium tungsten.
다음으로, (e)와 같이, 콘택홀에 매림된 플러그(4, 6`)를 전기적으로 연결시키기 위한 금속막을 형성한다. 이때의 금속막은 제1 금속층(7), 제2 금속층(8), 제3 금속층(9)의 3중 구조로 형성이 가능하며, 상기 제2 금속층은 알루미늄이나 구리를 이용할 수 있다. 이때의 상기 제1(7), 제3 금속층(9)은 동일한 물질로 구성하거나 서로 다르게 구성할 수 있는데, 동일할 경우에는 티타늄(Ti), 티타늄나이트라이드(TiN), 탄탈륨(Ta), 티타늄텅스텐(TiW), 실리콘(Si) 중에서 하나를 선택할 수 있으며, 다를 경우에는 두 가지 물질을 선택하여 형성할 수 있다.Next, as shown in (e), a metal film for electrically connecting the plugs 4 and 6 'embedded in the contact holes is formed. In this case, the metal film may be formed in a triple structure of the first metal layer 7, the second metal layer 8, and the third metal layer 9, and the second metal layer may be aluminum or copper. At this time, the first (7), the third metal layer (9) may be composed of the same material or different, if the same, titanium (Ti), titanium nitride (TiN), tantalum (Ta), titanium One of tungsten (TiW) and silicon (Si) may be selected, and if different, two materials may be selected and formed.
이상에서 설명한 바와 같이 본 발명의 금속배선막 형성방법은 콘택홀의 크기가 서로 다른 경우, 먼저 작은 크기의 홀을 기준을 홀을 형성하여 1차로 금속 플러그를 형성하고, 크기가 큰 홀의 경우 이미 형성한 금속 플러그에 인접하는 홀을 형성하여 플러그를 형성하므로서, 직경이 큰 콘택홀을 기준으로 김속을 증착할 때 발생하는 글로블 단차 영역에서의 잔류 금속막 제거가 용이하며, 또한 글러벌 단차영역에서의 잔류 금속막의 두께를 얇게 하므로서 표면 거칠기를 감소시킬 수 있으며, 금속막의 전면식각시 식각율의 균일성을 확보할 수 있다. 아울러, 재현성도 향상시키는 효과를 제공한다.As described above, in the method of forming the metal interconnection film of the present invention, when the contact holes have different sizes, first, the metal plugs are first formed by forming holes based on the small sized holes. By forming a hole by forming a hole adjacent to the metal plug, it is easy to remove the residual metal film in the global step area generated when depositing the steam velocity based on a large diameter contact hole, and also remains in the global step area. By reducing the thickness of the metal film can reduce the surface roughness, it is possible to ensure the uniformity of the etching rate during the entire surface etching of the metal film. In addition, it provides an effect of improving reproducibility.
여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Although specific embodiments of the present invention have been described and illustrated herein, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (12)
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| KR1019950048302A KR100197118B1 (en) | 1995-12-11 | 1995-12-11 | Method of forming interconnector in semiconductor device |
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| KR1019950048302A KR100197118B1 (en) | 1995-12-11 | 1995-12-11 | Method of forming interconnector in semiconductor device |
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| KR100197118B1 true KR100197118B1 (en) | 1999-06-15 |
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| KR100447970B1 (en) * | 2001-12-15 | 2004-09-10 | 주식회사 하이닉스반도체 | Method of making metal wiring in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100447970B1 (en) * | 2001-12-15 | 2004-09-10 | 주식회사 하이닉스반도체 | Method of making metal wiring in semiconductor device |
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