KR0179559B1 - Method of forming anti-corrosion metal interconnector in semiconductor device - Google Patents
Method of forming anti-corrosion metal interconnector in semiconductor device Download PDFInfo
- Publication number
- KR0179559B1 KR0179559B1 KR1019950048289A KR19950048289A KR0179559B1 KR 0179559 B1 KR0179559 B1 KR 0179559B1 KR 1019950048289 A KR1019950048289 A KR 1019950048289A KR 19950048289 A KR19950048289 A KR 19950048289A KR 0179559 B1 KR0179559 B1 KR 0179559B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- copper
- conductive film
- heat treatment
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 금속배선막의 부식을 방지하는 부식방지용 금속배선막의 형성 방법을 제공하기 위한 것이다.The present invention is to provide a method for forming a corrosion preventing metal wiring film to prevent corrosion of the metal wiring film.
이와 같은 본 발명의 부식방지용 금속배선 형성방법은 기판 상부에 형성된 절연막의 소정부분에 형성된 콘택홀(또는 비아홀) 전면에 콘택홀이 매립되지 않을 정도로 얇게 제1도전막을 형성하는 단계; 제1도전막 상에 제2도전막을 콘택홀이 매립되지 않을 정도로 얇게 형성하는 단계; 구리를 제2도전막 상의 전면에 소정 두께로 도포하여 콘택홀을 매립하는 단계; 구리배선 상에 감광막 패턴을 형성하여 제1금속배선패턴 이외의 구리막, 제2금속막, 제1금속막을 순차적으로 제거하는 단계; 노출된 구리 패턴의 측면을 포함한 전면에 알루미늄 박막을 형성하는 단계; 알루미늄 박막이 형성된 결과적인 구조를 열적 산화시키는 단계를 포함하는 것을 특징으로 한다.Such a method for forming a corrosion preventing metal wiring according to the present invention includes the steps of forming a first conductive film so thin that the contact hole is not buried in the entire contact hole (or via hole) formed in a predetermined portion of the insulating film formed on the substrate; Forming a thin second conductive film on the first conductive film such that the contact hole is not embedded; Filling the contact hole by applying copper to the entire surface on the second conductive film; Forming a photoresist pattern on the copper wiring to sequentially remove the copper film, the second metal film, and the first metal film other than the first metal wiring pattern; Forming an aluminum thin film on the front surface including the exposed side of the copper pattern; And thermally oxidizing the resulting structure in which the aluminum thin film is formed.
Description
제1도는 본 발명의 실시예에 따른 반도체 소자에 있어서, 부식방지용 금속배선의 형성방법을 설명하는 공정 단면도.1 is a cross-sectional view illustrating a method of forming a metal wiring for preventing corrosion in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 접합층1 silicon substrate 2 bonding layer
3 : 산화막 4 : 제1금속막3: oxide film 4: first metal film
5 : 제2금속막 6 : 구리 막5: second metal film 6: copper film
7 : CuAl2를 함유한 알루미늄 막 8 : 알루미늄 산화막7: aluminum film containing CuAl 2 8: aluminum oxide film
본 발명은 반도체 소자의 금속배선막 형성방법에 관한 것으로, 특히 콘택홀 및 비아홀에 매립되는 부식방지용 금속배선막의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a metal wiring film of a semiconductor device, and more particularly, to a method of forming a corrosion preventing metal wiring film embedded in contact holes and via holes.
일반적으로 막의 증착에 사용되는 증착공정이라 함은 기상의 소스로부터 특정 원자나 분자를 고상화 시켜 필요로 하는 박막을 얻어 내는 일종의 물질 합성과정을 통칭한다. 반도체 소자의 제조에는 다결정 실리콘, 산화막, 질화막, 여러 종류의 금속 혹은 실리사이드 박막이 필요하며 이와 같은 박막들은 모두 증착공정에 의해서 형성된다.In general, the deposition process used for the deposition of a film refers to a kind of material synthesis process for obtaining a thin film required by solidifying specific atoms or molecules from a gaseous source. The manufacture of a semiconductor device requires a polycrystalline silicon, an oxide film, a nitride film, various metals or silicide thin films, all of which are formed by a deposition process.
증착공정은 박막 형성법(Thin Film Process)이라고 말할 수 있으며, 이는 크게 물리 증착법(Physical Vapor Deposition : PVD)과 화학 증착법(Chemical Vapor Deposition)로 대별된다. 물리 증착은 소스로부터 임의 다른 성분이 더해지거나 감해지지 않고 상의 변환 과정만을 통하여 증착되는 것이다. 반면에 화학증착은 반응을 수반하기 때문에 소스와 증착 산물간에 물리화학적 구조의 차이가 있다.The deposition process may be referred to as a thin film process, which is roughly classified into physical vapor deposition (PVD) and chemical vapor deposition (Chemical Vapor Deposition). Physical deposition is the deposition through phase transformation only, without any other components being added or subtracted from the source. On the other hand, because chemical vaporization involves reaction, there is a difference in physicochemical structure between the source and the deposition product.
이러한 증착공정을 이용하여 반도체 소자에 사용되는 구성막으로는 크게 절연막과 도전막으로 구성되고, 절연막으로는 SiO2, PSG, BPSG와 같은 산화막과 SI3N4와 같은 질화막이 있으며, 물리증착법중의 일종인 회전 도포법(Spin Coating)의 원리를 이용한 SOG(Spin On Glass)와 PIQ(Polymide)가 있는데, SOG는 무기계의 실리케이트(Silicate) SOG와 유기계의 실록산(Siloxane) SOG가 있다. 이러한 SOG는 주로 금속간 유전체(Intermetal Dielectric)용으로 적용된다. 한편, 폴리이미드는 평탄화 능력이 우수한 다층배선 층간절연막으로서, 두꺼운 막이 가능해서 알파선 저지막으로도 쓰인다.The constituent film used for the semiconductor device using such a deposition process is largely composed of an insulating film and a conductive film, and the insulating film includes an oxide film such as SiO 2 , PSG, BPSG, and a nitride film such as SI 3 N 4 . There are spin on glass (SOG) and PIQ (polymide) using the principle of spin coating, which is an inorganic silicate (Silicate) SOG and organic siloxane (Siloxane) SOG. Such SOG is mainly applied for intermetal dielectrics. On the other hand, polyimide is a multi-layered wiring interlayer insulating film having excellent planarization capability, and can be used as an alpha line blocking film because a thick film is possible.
반도체 소자의 제조에 있어서, 신호전달 및 전원인가 등을 위해서 형성되는 금속배선막은 집적도의 증가로 인하여 배선자체의 선폭 감소 및 배선간의 간격이 점점 좁아지게 된다. 이에 따라 콘택홀이나 비아홀의 크기도 점점 작아지게 되는데, 이러한 홀 크기의 감소는 단차비(ASPECT RATIO)를 증가시키게 된다.In the manufacture of semiconductor devices, metal wiring films formed for signal transmission, power supply, and the like become increasingly narrower in line width and wiring spacing due to an increase in the degree of integration. Accordingly, the size of the contact hole or the via hole becomes smaller and smaller, and the decrease in the hole size increases the ASP ratio.
텅스텐 금속을 콘택 및 비아홀에 매립할 때, 스퍼터링 방법으로는 미세콘택에서 충분한 층덮힘을 얻을 수 없기 때문에 단선불량 가능성이 높다. 따라서, 화학기상증착법(Chemical Vapor Deposition : CVD)이 많이 이용된다. 이때, 증착되는 텅스텐의 저항은 알루미늄 합금의 저항값보다 3배 정도 크므로, 콘택 매립후 그 이외의 부분의 텅스텐을 완전히 제거하여야 한다. 그런데, 이러한 부분에서의 텅스텐의 제거는 매우 까다로우며, 글로벌 단차 영역에서의 텅스텐 제거를 위한 과도 식각시 콘택을 매립한 텅스텐(이하 텅스텐 플러그로 표기)도 식각되는 문제점이 존재한다. 이에 대한 대체 방안으로서, 구리를 화학기상증착법으로 형성하는 기술이 있다. 그러나 이러한 방법은 구리 자체의 저항이 알루미늄 합금과 거의 유사하므로, 텅스텐과 같이 식각할 필요는 없으나 구리 자체의 물질 특성상 부식이 빨리 진행되는 문제점이 존재한다.When tungsten metal is embedded in contacts and via holes, there is a high possibility of disconnection because sputtering does not provide sufficient layer covering in the microcontact. Therefore, chemical vapor deposition (CVD) is widely used. At this time, since the resistance of the deposited tungsten is about three times larger than the resistance of the aluminum alloy, tungsten in other portions must be completely removed after the contact is buried. However, the removal of tungsten in such a portion is very difficult, and there is a problem in that tungsten (hereinafter referred to as a tungsten plug) which has buried a contact during the excessive etching for tungsten removal in the global stepped region is also etched. As an alternative, there is a technique of forming copper by chemical vapor deposition. However, since the resistance of copper itself is almost similar to that of aluminum alloy, this method does not need to be etched like tungsten, but there is a problem that corrosion proceeds quickly due to the material properties of copper itself.
따라서, 본 발명의 목적은 금속배선막으로서 구리를 사용하는 경우에 있어서 발생되는 구리 배선의 부식을 방지할 수 있는 금속배선의 형성방법을 제공하기 위한 것이다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring that can prevent corrosion of copper wiring generated when copper is used as the metal wiring film.
이와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 금속배선막 형성방법은 콘택홀(또는 비아홀)을 통하여 구리의 금속배선을 형성하는 반도체 금속배선막 형성방법에 있어서, 반도체 기판 상부에 형성된 절연막의 소정 부분에 형성된 콘택홀(또는 비아홀) 전면에 콘택홀이 매립되지 않을 정도의 소정 두께만큼 제1도전막을 형성하는 단계; 제1도전막 전면에 콘택홀이 매립되지 않을 정도의 소정 두께만큼 제2도전막을 형성하는 단계; 제2도전막 형성후, 계면에서의 점착력을 향상시키기 위하여 소정온도 및 시간동안 열처리하는 제1열처리 단계; 제2도전막 상의 전면에, 콘택홀 상부로부터 소정 높이까지 막이 형성되도록 구리를 증착하는 단계; 증착된 구리배선 상에 감광막 패턴을 형성하여 구리막, 제2금속막, 제1금속막을 선택적 및 순차적으로 제거하는 단계; 노출된 구리 패턴의 측면을 포함한 전면에 알루미늄 박막을 형성하는 단계; 알루미늄 박막과 전 단계에서 형성된 구리막의 계면에서 소정 두께의 알루미늄과 구리 성분으로 구성되는 합금을 형성하기 위하여 소정온도 및 시간동안 열처리하는 제2열처리 단계; 표면 알루미늄막을 열산화시키는 단계를 포함하는 것을 특징으로 한다.The method for forming a metal interconnection film of the semiconductor device of the present invention for achieving the above object is a method of forming a metal interconnection film for forming a metal wiring of copper through a contact hole (or via hole), the insulating film formed on the semiconductor substrate Forming a first conductive film having a predetermined thickness such that the contact hole is not buried in the entire contact hole (or via hole) formed in the predetermined portion; Forming a second conductive film having a predetermined thickness such that contact holes are not buried in the entire surface of the first conductive film; A first heat treatment step of performing heat treatment for a predetermined temperature and time to improve adhesion at the interface after the formation of the second conductive film; Depositing copper on the entire surface of the second conductive film so that the film is formed from a contact hole to a predetermined height; Forming a photoresist pattern on the deposited copper wiring to selectively and sequentially remove the copper film, the second metal film, and the first metal film; Forming an aluminum thin film on the front surface including the exposed side of the copper pattern; A second heat treatment step of performing heat treatment for a predetermined temperature and time to form an alloy composed of aluminum and copper components having a predetermined thickness at an interface between the aluminum thin film and the copper film formed in the previous step; And thermally oxidizing the surface aluminum film.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
첨부한 도면 제1도는 본 발명의 실시예에 따른 금속배선 형성방법을 설명하는 공정흐름도이다.1 is a flowchart illustrating a method for forming metal wirings according to an embodiment of the present invention.
먼저, 첨부한 도면의 (a)에 도시한 것 처럼, 실리콘 기판(1) 상이나 내부에 이온 주입과 열처리 공정을 통하여 접합층(2)을 형성한 다음에 산화막(3)을 그 위에 증착한다. 상기 산화막(3)의 소정 부위에 콘택홀(10)을 형성한다. 상기 콘택홀(또는 비아홀)(10)은 일반적인 포토마스킹 및 식각공정에 의하여 형성한 감광막 패턴을 완전히 제거한다.First, as shown in (a) of the accompanying drawings, the bonding layer 2 is formed on or inside the silicon substrate 1 through ion implantation and heat treatment processes, and then the oxide film 3 is deposited thereon. The contact hole 10 is formed in a predetermined portion of the oxide film 3. The contact hole (or via hole) 10 completely removes the photoresist pattern formed by a general photomasking and etching process.
콘택홀의 형성 후, 콘택홀을 포함한 전면에 콘택홀이 매립되지 않을 정도의 소정 두께만큼 제1도전막(4)을 형성한다. 이때의 제1도전막(4)은 티타늄(Titanium : Ti)을 스퍼터링 방법으로 형성한다.After the formation of the contact hole, the first conductive film 4 is formed to a predetermined thickness such that the contact hole is not embedded in the entire surface including the contact hole. At this time, the first conductive film 4 is formed of titanium (Ti) by the sputtering method.
상기 제1도전막(4) 전면에 콘택홀이 매립되지 않을 정도의 소정 두께만큼 제2도전막(5)을 형성한다. 상기 제2도전막(5)은 티타늄 나이트라이드(TiN)를 스퍼터링 방법 또는 화학기상증착 방법으로 형성하고, 형성된 상기 티타늄 나이트라이드의 두께는 제1도전막(4)인 티타늄의 두께보다 두껍게 증착한다. 또한 상기 제2도전막(5)은 티타늄 텅스텐(TixWy)을 사용하여도 무방하지만 이 경우에는 증착을 위하여 스퍼터링 방법을 사용한다.The second conductive film 5 is formed on the entire surface of the first conductive film 4 by a predetermined thickness such that the contact hole is not buried. The second conductive film 5 is formed of titanium nitride (TiN) by sputtering or chemical vapor deposition, and the thickness of the formed titanium nitride is deposited to be thicker than the thickness of titanium, which is the first conductive film (4). . In addition, the second conductive film 5 may use titanium tungsten (Ti x W y ), but in this case, a sputtering method is used for deposition.
상기 제2도전막(5) 형성후, 계면에서의 점착력을 향상시키기 위하여 450℃ 이상의 온도에서 10분 이상동안 열처리 한다.After the formation of the second conductive film 5, heat treatment is performed for 10 minutes or more at a temperature of 450 ° C. or more to improve the adhesive force at the interface.
상기 제2도전막(5) 상의 전면에, 콘택홀 상부로부터 소정 높이까지 막이 형성되도록 제2도전막인 구리 막(6)을 화학기상증착법으로 증착하는데 이때 구리의 원재료로는 '트리메틸비닐실렌-헥사플루오르아세틸아세토네이트[trimethylvinylsilane-hexafluoroacetylacetonate = tmvs)(hfac)]을 이용할 수 있다.On the entire surface of the second conductive film 5, the copper film 6, which is the second conductive film, is deposited by chemical vapor deposition so that a film is formed from the upper portion of the contact hole to a predetermined height. Hexafluoroacetylacetonate (trimethylvinylsilane-hexafluoroacetylacetonate = tmvs) (hfac) can be used.
증착된 구리배선(6) 상에 제1금속배선막 패턴을 형성하기 위하여 감광막을 도포하고, 노광 및 스트립(strip) 공정을 통하여 마스킹을 위한 감광막 패턴(10)을 형성한다.A photosensitive film is coated on the deposited copper wiring 6 to form a first metal wiring film pattern, and a photosensitive film pattern 10 for masking is formed through an exposure and stripping process.
다음으로, (b)도면에 도시한 바와 같이, 감광막 패턴이 없는 노출된 구리막, 제2금속막, 제1금속막을 순차적으로 제거하여 제1금속배선막 패턴을 형성한다.Next, as shown in (b), the exposed copper film, the second metal film, and the first metal film without the photosensitive film pattern are sequentially removed to form the first metal wiring film pattern.
다음으로 (c)도면에 도시한 바와 같이, 노출된 제1금속배선막 패턴의 측면을 포함한 전면에 제4도전막인 알루미늄 박막을 형성한다. 상기 알루미늄 박막은 화학기상증착법으로 3000Å이하의 두께로 형성한다. 상기 알루미늄 박막의 원재료로는 티바(tiba=trisobutylaluminum)를 이용하는 것도 가능하다. 이후, 현 단계에서 도포된 알루미늄 박막과 전 단계에서 도포된 구리막(6)의 계면에서 CuAl2합금을 형성하기 위하여 350℃ 이상의 온도에서 10분 이상 열처리한다. 상기 열처리 과정으로 알루미늄 박막은 구리막과의 계면에 CuAl2합금막을 함유하는 이중막(7)로 변환된다. 이후, 상기 단계까지의 결과적인 웨이퍼를 350℃ 이상의 온도, 산소(O2)분위기에서 10분 이상 열처리하여 산화시키므로써, 알루미늄 박막의 최외각에 Al2O3박막을 얇게 형성시킨다. 상기 열산화단계에서는 산소와 다른 개스를 1가지 이상 혼합하여 가열하는 것도 가능한데, 이 경우에는 혼합가스 중 산소가스가 10%이상 되도록 한다.Next, as shown in (c), an aluminum thin film, which is a fourth conductive film, is formed on the entire surface including the exposed side of the first metal wiring film pattern. The aluminum thin film is formed to a thickness of less than 3000 kPa by chemical vapor deposition. It is also possible to use tiba (tiba = trisobutylaluminum) as a raw material of the aluminum thin film. Thereafter, heat treatment is performed for 10 minutes or more at a temperature of 350 ° C. or more to form a CuAl 2 alloy at the interface between the aluminum thin film coated in the present step and the copper film 6 applied in the previous step. In the heat treatment process, the aluminum thin film is converted into a double film 7 containing a CuAl 2 alloy film at an interface with the copper film. Subsequently, the resultant wafer up to the step is oxidized by heat treatment at a temperature of 350 ° C. or higher and oxygen (O 2 ) for at least 10 minutes, thereby forming a thin Al 2 O 3 thin film on the outermost portion of the aluminum thin film. In the thermal oxidation step, it is also possible to mix and heat one or more kinds of oxygen and other gases, in which case the oxygen gas in the mixed gas is 10% or more.
이상에서 설명한 바와 같이, 본 발명의 부식방지용 금속배선막 형성방법은 콘택홀에 형성되는 플러그를 제1금속막을 스퍼터링법으로 얇게 형성한 다음에 제2, 제3의 금속막을 도포하여 3층 구조로 형성하므로써 집적도의 증가로 인하여 작아지는 콘택홀을 거의 완전히 매립하는 것이 가능하며, 금속배선막을 구리가 주성분인 다층구조로 형성하므로써, 전자가 알루미늄 배선을 통해 이동할 때, 전자의 운동량이 알루미늄 이온에 전달되므로써 전자의 흐름방향으로 알루미늄의 질량흐름이 생기는 EM(ElectromigraAs described above, in the method for forming a corrosion preventing metal wiring film of the present invention, the plug formed in the contact hole is thinly formed by sputtering the first metal film, and then the second and third metal films are coated to form a three-layer structure. By forming, it is possible to almost completely fill the contact holes that decrease due to the increase in the degree of integration, and by forming the metal wiring layer in a multilayer structure composed mainly of copper, when the electrons move through the aluminum wiring, the momentum of the electrons is transferred to the aluminum ions. Therefore, the mass flow of aluminum in the direction of electron flow
tion) 현상에 대한 내구성을 향상시킬 수 있고, 구리배선 표면에 부식에 대한 내구성을 갖는 물질을 형성시키므로써, 구리배선을 부식을 방지할 수 있으며, 아울러, 금속배선막의 제조공정이 비교적 간단하다는 장점을 제공한다.tion) It is possible to improve durability against phenomena and to prevent corrosion of copper wiring by forming a material having resistance against corrosion on the surface of copper wiring, and to manufacture a metal wiring film relatively simple. To provide.
여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Although specific embodiments of the present invention have been described and illustrated herein, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048289A KR0179559B1 (en) | 1995-12-11 | 1995-12-11 | Method of forming anti-corrosion metal interconnector in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048289A KR0179559B1 (en) | 1995-12-11 | 1995-12-11 | Method of forming anti-corrosion metal interconnector in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970052928A KR970052928A (en) | 1997-07-29 |
| KR0179559B1 true KR0179559B1 (en) | 1999-04-15 |
Family
ID=19438984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950048289A KR0179559B1 (en) | 1995-12-11 | 1995-12-11 | Method of forming anti-corrosion metal interconnector in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0179559B1 (en) |
-
1995
- 1995-12-11 KR KR1019950048289A patent/KR0179559B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970052928A (en) | 1997-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4425432B2 (en) | Manufacturing method of semiconductor device | |
| JP2814972B2 (en) | Method for manufacturing semiconductor device | |
| JP2002043315A (en) | Semiconductor device and manufacturing method thereof | |
| JP3193335B2 (en) | Method for manufacturing semiconductor device | |
| KR100319588B1 (en) | Method for forming interconnection structure | |
| US6413863B1 (en) | Method to resolve the passivation surface roughness during formation of the AlCu pad for the copper process | |
| JPH09326436A (en) | Formation of wiring | |
| JP2004523891A (en) | Chromium adhesive layer for copper vias in low dielectric constant technology | |
| JP2003045878A (en) | Method for forming wiring of semiconductor element | |
| KR0179559B1 (en) | Method of forming anti-corrosion metal interconnector in semiconductor device | |
| JP2000174019A (en) | Semiconductor device and manufacture thereof | |
| KR100400040B1 (en) | Metal wiring method of semiconductor device | |
| KR100606544B1 (en) | Method for forming the copper wiring of semiconductor device | |
| JP3594888B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100247643B1 (en) | A reaction chamber for forming metal layer and method for forming metal layer in semiconductor device using the same | |
| KR100399066B1 (en) | Method for aluminium-alloy in semiconductor device | |
| US6340638B1 (en) | Method for forming a passivation layer on copper conductive elements | |
| JP2002134610A (en) | Method for manufacturing semiconductor device | |
| JPH08181146A (en) | Manufacture of semiconductor device | |
| KR0156126B1 (en) | Formation method of contact hole in semiconductor device | |
| KR100324020B1 (en) | Metal wiring formation method of semiconductor device | |
| KR100197118B1 (en) | Method of forming interconnector in semiconductor device | |
| KR100197992B1 (en) | Forming method for metal wiring in semiconductor device | |
| JP2000100936A (en) | Manufacture of semiconductor device | |
| KR100252764B1 (en) | Method for fabricating multi-layer metallization in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20051021 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |