JP2000174019A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable further higher integration and higher-speed by using wiring composed of Cu. SOLUTION: This device has an opening 32 formed on an underlying substrate 10, an insulating barrier layer 34 for prevention of Cu diffusion, and an electrically conductive layer 36 comprising a Cu layer formed inside the opening 32, wherein the insulating barrier layer 34 is either of a silicon base insulating layer containing carbon and fluorine, an organic film, or a C-axis-oriented BN(boron nitride) film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using a wiring made of a Cu layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, there has been a remarkable increase in the degree of integration of a semiconductor device. However, as the amount of information processing of electronic devices has increased, further higher integration of a semiconductor device has been required. With the increase in the degree of integration of semiconductor devices, the width of wiring connecting elements inside the semiconductor device has also been reduced.

However, when the width of the wiring is simply reduced,
The resistance value of the wiring increases, which causes an increase in signal delay time. Therefore, it has been proposed to use copper having a lower resistivity than aluminum as a wiring material without using aluminum which has been widely used as a wiring material. Aluminum has a resistivity of 3 to 3.5 μΩ · cm, whereas copper has a resistivity as low as about 1.7 μΩ · cm. Therefore, by forming wiring using copper, the resistance value of the wiring can be significantly increased. It is possible to reduce the size.

[0004] Since copper is a metal which is difficult to vaporize even if it is a fluoride, it is difficult to pattern it by etching. Therefore, CWKaanta et al. Have proposed a method called a damascene method and are being applied to products as a method for solving the workability of Cu wiring. A conventional method for manufacturing a semiconductor device will be described with reference to FIG. FIG. 14 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 14, an element isolation film 112 for defining an element region is formed on a silicon substrate 110, and the element region defined by the element isolation film 112 is
Gate electrode 116 having side wall insulating film 114 formed on side surfaces and source / drain diffusion layers 118a, 118
b is formed. Next, an interlayer insulating film 120 and a stopper film 121 are formed on the entire surface.
Contact hole 12 reaching drain diffusion layer 118b
Form 2

Next, a barrier layer 124 and a conductor plug 126 are formed in the contact hole 122. Next, an interlayer insulating film 130 is formed on the entire surface, and the interlayer insulating film 130 is etched using the stopper film 121 as an etching stopper, whereby the trench 13 for embedding the wiring 136 is formed.
Form 2

Next, a TiN film or a TaN film is formed on the entire surface, and thereafter, a Cu layer is formed on the entire surface. Next, CMP
Until the surface of the interlayer insulating film 130 is exposed,
The film and the TiN film or the TaN film are polished, whereby the barrier layer 134 made of the TiN film or the TaN film and the wiring 136 made of the Cu layer are formed in the groove. Note that the barrier layer 134 is for preventing Cu of the wiring 136 from diffusing into the device.

[0008]

However, when a TiN film is used as the barrier layer 134, it has been difficult to form a TiN film having good adhesion. In the case where the width of the groove is reduced in accordance with high integration of the semiconductor device, C
It is necessary to form the barrier layer thin in order to prevent the cross-sectional area of the wiring composed of the u layer from being reduced.
When a thin barrier layer made of an iN film is formed, Ti
The N film did not sufficiently function as a barrier against Cu, and could not sufficiently prevent the diffusion of Cu into the device.

Further, when a TaN film is used as the barrier layer 134, it is difficult to polish the TaN film by the CMP method, so that a long time is required for the polishing step. In addition, since the TaN film has a high electric resistance, the barrier layer is thick,
If the cross-sectional area of the barrier layer occupies a large proportion of the cross-sectional area of the wiring, the signal propagation delay time has been delayed.

An object of the present invention is to provide a semiconductor device capable of realizing higher integration and higher speed by using a wiring made of a Cu layer, and a method of manufacturing the same.

[0011]

An object of the present invention is to provide a barrier insulating layer formed on a base substrate and having an opening to prevent diffusion of Cu, and a conductive layer comprising a Cu layer formed in the opening. Wherein the barrier insulating layer is a silicon-based insulating layer containing carbon and fluorine, an organic film, or a BN film oriented in the C-axis direction. You. Thus, diffusion of Cu can be prevented, and since a wiring or the like made of a Cu layer is formed in the opening of the barrier insulating layer having a low dielectric constant, a semiconductor device with a high degree of integration and a high operating speed can be realized. Can be provided.

[0012] Further, the object is to provide an insulating layer formed on a base substrate and having an opening, a barrier insulating layer formed on a side surface in the opening to prevent diffusion of Cu, Formed in the formed opening,
A conductive layer made of a Cu layer, wherein the barrier insulating layer comprises:
This is achieved by a semiconductor device characterized by being a silicon-based insulating layer containing carbon and fluorine, an organic film, or a BN film oriented in the C-axis direction. Thereby, diffusion of Cu can be sufficiently prevented even if it is thin, and
Since the barrier insulating layer having a low dielectric constant is formed on the side surface in the opening, a semiconductor device with a high degree of integration and a high operation speed can be provided by using a wiring made of a Cu layer.

[0013] Further, the object is to form a first barrier insulating layer formed on a base substrate, having a first opening, for preventing diffusion of Cu, and formed on the first barrier insulating layer. A second barrier insulating layer having a second opening to prevent diffusion of Cu, and a conductive layer comprising the same Cu layer formed in the first opening and the second opening. Wherein the first barrier insulating layer and / or the second barrier insulating layer is a silicon-based insulating layer containing carbon and fluorine,
This is achieved by a semiconductor device characterized by being either an organic film or a BN film oriented in the C-axis direction. Thus, diffusion of Cu can be prevented, and since a wiring or the like made of a Cu layer is formed in the opening of the barrier insulating layer having a low dielectric constant, a semiconductor device with a high degree of integration and a high operating speed can be realized. Can be provided. In addition, since the same conductive layer made of the same Cu layer is formed in the first opening and the second opening, it can be manufactured by simple steps.

The above object is also achieved by a first insulating layer formed on a base substrate and having a first opening, and a second insulating layer formed on the first insulating layer and having a second opening. An insulating layer, a barrier insulating layer formed on the side surface in the first opening and the side surface in the second opening for preventing diffusion of Cu, and the first insulating film on which the barrier insulating layer is formed. The same Cu formed in the opening and in the second opening
A conductive layer formed of a layer and a lower surface of the second opening in a region excluding a region in which the first opening is formed; the etching characteristic is different from that of the second insulating layer; A barrier insulating layer, wherein the barrier insulating layer includes a silicon-based insulating layer containing carbon and fluorine, an organic film,
Or a BN film oriented in the C-axis direction. Thereby, diffusion of Cu can be sufficiently prevented even if it is thin,
Further, since the barrier insulating layer having a low dielectric constant is formed on the side surface inside the first opening and the side surface inside the second opening,
A semiconductor device with a high degree of integration and a high operation speed can be provided by using a wiring formed of a u-layer. In addition, since the same conductive layer made of the same Cu layer is formed in the first opening and the second opening, it can be manufactured by simple steps.

[0015] Further, the object is to form a barrier insulating layer for preventing diffusion of Cu on a base substrate, a step of forming an opening in the barrier insulating layer, and a step of forming a Cu layer in the opening. And a step of forming a conductive layer. Thereby, diffusion of Cu can be prevented, and since a wiring or the like made of a Cu layer is formed in the opening of the barrier insulating layer having a low dielectric constant, a semiconductor device with a high degree of integration and a high operation speed is manufactured. be able to.

The object of the present invention is to form an insulating layer on a base substrate, to form an opening in the insulating layer, and to form a barrier insulating layer on a side surface in the opening to prevent the diffusion of Cu. And a step of forming a conductive layer made of a Cu layer in the opening in which the barrier insulating layer is formed. Thereby, the diffusion of Cu can be sufficiently prevented even if it is thin, and the barrier insulating layer having a low dielectric constant is formed on the side surface in the opening, so that the integration degree is high by using the wiring made of the Cu layer, A semiconductor device with a high operation speed can be manufactured.

Further, the above object is to form a first barrier insulating layer for preventing diffusion of Cu on a base substrate;
Forming a second barrier insulating layer for preventing diffusion of Cu on the first barrier insulating layer; forming a first opening in the first barrier insulating layer; A semiconductor comprising: a step of forming a second opening in an insulating layer; and a step of forming a conductive layer made of the same Cu layer in the first opening and the second opening. This is achieved by a method of manufacturing a device. As a result, diffusion of Cu can be prevented, and a wiring or the like made of a Cu layer is formed in the opening of the barrier insulating layer having a low dielectric constant.
A semiconductor device with high integration and high operation speed can be manufactured. In addition, since the conductive layers made of the same Cu layer are formed in the first opening and the second opening, the semiconductor device can be manufactured by simple steps.

Further, the above object is to form a first insulating layer on a base substrate, and to form a first insulating layer on the first insulating layer.
Forming a second insulating layer for preventing the diffusion of the second insulating layer, forming a third insulating layer having a different etching characteristic from the second insulating layer on the second insulating layer, Forming a first opening in the insulating layer and the second insulating layer, and forming a second opening in the third insulating layer; and forming a side surface in the first opening and the second Forming a barrier insulating layer for preventing diffusion of Cu on the side surface in the opening of the first opening and the second opening in which the barrier insulating layer is formed; And a step of forming a conductive layer made of the semiconductor device. Thereby, the diffusion of Cu can be sufficiently prevented even if it is thin, and a barrier insulating layer having a low dielectric constant is formed on the side surface in the first opening and the side surface in the second opening. A semiconductor device with a high degree of integration and a high operation speed can be manufactured by using the wiring composed of the above. In addition, since the conductive layers made of the same Cu layer are formed in the first opening and the second opening, the semiconductor device can be manufactured by simple steps.

[0019]

[First Embodiment] The semiconductor device and the method for fabricating the same according to a first embodiment of the present invention will be explained with reference to FIG. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment. 2 to 4 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.

(Semiconductor Device) First, the semiconductor device according to the present embodiment will be explained with reference to FIG. As shown in FIG.
An element isolation film 12 that defines an element region is formed on the silicon substrate 10. In the element region defined by the element isolation film 12, a gate electrode 16 having a sidewall insulating film 14 formed on a side surface and a source / drain diffusion layer 18
a and 18b are formed.

Silicon substrate 1 on which transistors are formed
, An interlayer insulating film 2 made of a silicon oxide film
0 is formed on the interlayer insulating film 20.
A stopper film 21 made of a 1 μm SiN film is formed. A contact hole 22 reaching the source / drain diffusion layer 18b of the transistor is formed in the interlayer insulating film 20 and the stopper film 21. Contact hole 2
2, a barrier layer 24 made of a TiN film is formed, and a conductor plug 26 made of a tungsten layer is formed in the contact hole 22 where the barrier layer 24 is formed.

Further, a 0.6 μm-thick hydrogen silsesquioxane film (hereinafter referred to as HS) is formed on the entire surface.
(Referred to as a Q film). A groove 32 reaching the conductor plug 26 and the stopper film 21 is formed in the interlayer insulating film 30. A barrier insulating layer 34 made of a BN (Boron Nitride) film having a thickness of 30 nm is formed on a side surface in the groove 32. The main feature of the semiconductor device according to the present embodiment is that a barrier insulating layer made of a BN film, which is an insulating film, is used instead of the barrier layer which has been a conductive film in the past. Since the BN layer can sufficiently prevent the diffusion of Cu even with an extremely thin film thickness, for example, about 30 nm, even if the width of the groove is narrowed due to the high integration of the semiconductor device, a sufficient wiring width can be obtained. The width can be secured. Further, since the BN film has a low dielectric constant, it is possible to suppress the signal propagation speed from being reduced in the wiring. The BN film used as the barrier insulating layer 34 is formed so as to be oriented in the C axis. Since the BN film is oriented along the C axis, the dielectric constant can be kept low.

An interconnect 36 made of Cu is formed in the groove 32 in which the barrier insulating layer 34 is formed. A barrier insulating layer 34 for preventing the diffusion of Cu is formed on the side surface in the groove 32. The SiN film used as the stopper film 21 has a function for preventing the diffusion of Cu. Is prevented from diffusing into the device.

As described above, according to the present embodiment, the BN film that can sufficiently prevent the diffusion of Cu is used as the barrier insulating layer even when formed thinly. Since the dielectric constant is low, a semiconductor device with high integration and high operation speed can be provided. (Electrical Characteristics) Next, the electrical characteristics of the semiconductor device according to the present embodiment will be explained.

The evaluation of the electrical characteristics of the semiconductor device according to the present embodiment was performed by subjecting the above-described semiconductor device to a heat treatment at 400 ° C. and measuring the change in the leak current before and after the heat treatment. As a result, the semiconductor device according to the present embodiment showed no particular change in the leak current, and exhibited good electrical characteristics.

(The Method for Fabricating the Semiconductor Device) Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. First, as shown in FIG.
An element isolation film 12 for defining an element region is formed on the surface of the silicon substrate 10 by a (LOCal Oxidation of Silicon) method.

Next, a transistor having a gate electrode 16 having a sidewall insulating film 14 formed on a side surface and source / drain diffusion layers 18a and 18b is formed in the element region. Next, plasma CVD (plasma-enh
An interlayer insulating film 20 made of a silicon oxide film having a film thickness of 1.5 μm is formed by an advanced chemical vapor deposition method. The deposition conditions are, for example, a substrate temperature of 350 ° C.
The pressure in the film forming chamber is 3.0 Torr and the refractive index is 1.49 ±
0.02, RF power 300W, electrode spacing 400m
il, SiH ₄ gas flow rate is 40 sccm, N ₂ O gas flow rate is 400 sccm, N ₂ gas flow rate is 2,000 sccc
m, the growth rate can be 560 nm ± 50 nm. One mil is 1/1000 inch.

Next, the silicon oxide film 2 is formed by the CMP method.
0 is flattened (see FIG. 2B). Next, a 0.1 μm-thick SiN film was formed on the entire surface by plasma CVD.
A stopper film 21 made of a film is formed. The deposition conditions are, for example, a substrate temperature of 400 ° C. and a pressure in the deposition chamber of 4.85.
Torr, refractive index 1.92 ± 0.05, RF power 375 W, electrode spacing 600 mils, SiH ₄ gas flow rate 100 sccm, NH ₃ gas flow rate 75 scc
m, the flow rate of N ₂ gas is 1600 sccm, and the growth rate is 5
00 nm ± 50 nm.

Next, a contact hole 22 reaching the source / drain diffusion layer is formed (see FIG. 2C). Next, a TiN film and a tungsten film are sequentially formed on the entire surface by the CVD method. Next, polishing is performed by a CMP method until the surface of the interlayer insulating film 20 is exposed, thereby forming a barrier layer 24 made of a TiN film and a conductor plug 26 made of a tungsten film in the contact hole 22 (FIG. 3). (A)).

Next, an interlayer insulating film 30 made of a hydrogen silsesquioxane film having a thickness of 0.6 μm is formed on the entire surface (see FIG. 3B). The interlayer insulating film 30 can be formed by forming a film by a spin coating method and then performing a heat treatment. Spin coating conditions are, for example, 30
00 rpm for 30 seconds. The heat treatment conditions are, for example, 40 atmospheres or less in an O ₂ concentration of 50 ppm or less.
0 ° C. for 30 minutes.

Next, the interlayer insulating film 30 is patterned by using the stopper film 21 as an etching stopper to form a groove 32 for embedding the wiring 36 (see FIG. 3C).
Next, a film thickness of 30 nm is formed on the entire surface by a plasma CVD method.
Is formed (see FIG. 4A). The film forming conditions include, for example, a flow ratio of BCl ₃ gas to NH ₃ gas of 1:
20, the substrate temperature was 450 ° C., and the pressure in the deposition chamber was normal pressure (7
60 Torr) and the refractive index can be 1.78. Note that the BN film is preferably formed so as to be C-axis oriented. By forming the BN film so as to be oriented along the C axis, the dielectric constant can be reduced.

Next, the BN film 33 in a region excluding the side surface in the groove 32 is etched by anisotropic etching. Thus, the barrier insulating layer 34 made of the BN film 33 is formed on the side surface in the groove 32 (see FIG. 4B).
Next, a seed layer made of a Cu layer having a thickness of 50 nm is formed on the entire surface by a sputtering method, and thereafter, a Cu layer having a thickness of 1 μm is formed by a plating method.

Next, polishing is performed by a CMP method until the surface of the interlayer insulating film 30 is exposed.
The wiring 36 made of the u layer is formed (see FIG. 4C).
Thus, the semiconductor device according to the present embodiment can be manufactured. After that, a semiconductor device having a multilayer wiring can be manufactured by further forming an interlayer insulating film, a wiring, and the like in the same steps as described above.

[Second Embodiment] The semiconductor device and the method for fabricating the same according to a second embodiment of the present invention will be explained with reference to FIGS. FIG. 5 is a sectional view of the semiconductor device according to the present embodiment. FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment. The same components as those of the semiconductor device according to the first embodiment and the method for fabricating the same shown in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

As shown in FIG. 5, a semiconductor device according to the first embodiment shown in FIG. 1 is different from the semiconductor device according to the first embodiment shown in FIG. Is the same as What is a Si-based CF film?
It is a silicon-based film containing carbon, fluorine, and oxygen, and a formation method thereof will be described later.

Barrier insulating layer 34 made of a Si-based CF film
“a” can sufficiently prevent the diffusion of Cu in the wiring into the device even with an extremely thin film thickness, for example, about 10 nm. Thereby, even when the width of the groove is reduced due to the high integration of the semiconductor device, it is possible to secure a sufficient width of the wiring 36. Further, since the Si-based CF film has a low dielectric constant, it is possible to suppress a reduction in signal propagation speed in the wiring 36.

As described above, according to the present embodiment, since the Si-based CF film is used as the barrier insulating layer 34a, the barrier insulating layer 34a which can sufficiently prevent the diffusion of Cu even if it is thin. The barrier insulating layer 34a can be formed with high adhesion.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, the method of manufacturing the semiconductor device according to the present embodiment is the same as the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 2A to 3C up to the step of forming the groove 32. Description is omitted because there is. Next, a 10 μm-thick Si-based CF film 33a is formed on the entire surface by a plasma CVD method. The Si-based CF film can be formed as follows.

As a film forming apparatus, a parallel plate type plasma C
The VD method can be used. The deposition conditions depend on the source
Using methyltriethoxysilane as a fluorine source
C_FourF₈Use gas. Methyltriethoxysilane is a liquid
Therefore, adjustment is performed using a liquid mass flow. In addition,
The flow rate of methyltriethoxysilane is the TEOS equivalent flow rate
And adjust it to be, for example, 20-40 sccm
Can be. Also, C _FourF₈The gas flow rate is, for example, 0 to 167 s
ccm. Also, for example, the applied power is
200W, pressure in the film forming chamber is 1.0 Torr, substrate temperature
Should be 240 ° C and the vaporizer temperature should be 80 ° C
it can.

It should be noted that methyltriethoxysilane and C_FourF₈
The flow ratio to gas is not limited to the above, but
Properly set to obtain the desired Si-based CF film
Can be. Methyltriethoxysilane and C_FourF₈With gas
Changing the flow rate ratio to form a Si-based CF film
The film structure and the relative permittivity will be described with reference to Table 1. Table 1
C _FourF₈Change the flow ratio between gas and methyltriethoxysilane
The figure shows the film structure and relative dielectric constant when
You.

[0041]

[Table 1] As shown in Table 1, methyltriethoxysilane and C ₄ F ₈
By appropriately setting the flow ratio with the gas, the Si-based CF film 33a having a desired film structure and a desired relative dielectric constant can be formed. Next, by anisotropic etching,
The Si-based CF film 33a in the region excluding the side surface in the groove 32 is etched. As a result, the barrier insulating layer 34a made of the Si-based CF film 33a is formed on the side surface in the groove 32 (see FIG. 6B).

Next, a film thickness of 50 is formed on the entire surface by sputtering.
A seed layer made of a Cu layer having a thickness of 1 nm is formed, and thereafter, a Cu layer having a thickness of 1 μm is formed by a plating method. Next, CM
By the P method, Cu is used until the surface of the interlayer insulating film 30 is exposed.
The layer is polished, thereby forming a wiring 36 made of a Cu layer in the groove 32 (see FIG. 6C).

Thus, the semiconductor device according to the present embodiment can be manufactured. Next, the electrical characteristics of the semiconductor device according to the present embodiment will be explained. The evaluation of the electrical characteristics of the semiconductor device according to the present embodiment was performed by performing a heat treatment at 400 ° C. on the semiconductor device and measuring a change in leakage current before and after the heat treatment.

As a result, the semiconductor device according to the present embodiment showed no particular change in the leak current, and exhibited good electrical characteristics. [Third Embodiment] The semiconductor device and the method for fabricating the same according to a third embodiment of the present invention will be explained with reference to FIGS.
FIG. 7 is a sectional view of the semiconductor device according to the present embodiment. FIG. 8 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment. The same components as those of the semiconductor device according to the first embodiment and the method for fabricating the same shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

(Semiconductor Device) The semiconductor device according to this embodiment is the same as the semiconductor device according to the first embodiment.
The semiconductor device according to the first embodiment is the same as the semiconductor device according to the first embodiment, except that the barrier interlayer insulating film 38 serving both as the barrier insulating layer 34a and the barrier insulating layer 34a is formed thick. That is, in this embodiment, instead of the interlayer insulating film 30 and the barrier insulating layer 34, a barrier interlayer insulating film 38 made of a Si-based CF film having a thickness of 1 μm is formed.

According to the present embodiment, it is not necessary to form a barrier insulating layer separately from the interlayer insulating film, so that a semiconductor device having a simple configuration can be provided. (The Method for Fabricating the Semiconductor Device) Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIG.

The steps up to the step of forming the barrier layer 24 and the conductor plug 26 in the contact hole 22 are the same as those in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 2A to 3A. Description is omitted. Next, a 1 μm-thick Si-based C
A barrier interlayer insulating film 38 made of an F film is formed. In addition,
The barrier interlayer insulating film 38 made of a Si-based CF film is made of a third material.
The semiconductor device can be formed in the same manner as in the method for manufacturing the semiconductor device according to the embodiment.

Next, the interlayer insulating film 30 is patterned using the stopper film 21 as an etching stopper to form a groove 32 for burying the wiring 36 (see FIG. 8B).
Next, a seed layer made of a Cu layer having a thickness of 50 nm is formed on the entire surface by a sputtering method, and thereafter, a Cu layer having a thickness of 1 μm is formed by a plating method. Next, by the CMP method,
Polishing the Cu layer until the surface of the interlayer insulating film 30 is exposed,
Thus, a wiring 36 made of a Cu layer is formed in the groove 32 (see FIG. 8C).

Thus, the semiconductor device according to the present embodiment can be manufactured. (Electrical Characteristics) Next, the electrical characteristics of the semiconductor device according to the present embodiment will be explained. The electrical characteristics of the semiconductor device according to the present embodiment were evaluated by measuring the leak current and the like after the heat treatment at 400 ° C., as in the semiconductor device according to the first embodiment.

As a result, the semiconductor device according to the present embodiment showed no particular change in the leak current and the like, and exhibited good electrical characteristics. [Fourth Embodiment] The semiconductor device and the method for fabricating the same according to a fourth embodiment of the present invention will be explained with reference to FIGS. FIG. 9 is a sectional view of the semiconductor device according to the present embodiment. 10 to 13 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. 1 to 8
The same reference numerals are given to the same components as those of the semiconductor device according to the first embodiment and the method of manufacturing the same, and the description thereof will be omitted or simplified.

(Semiconductor Device) The semiconductor device according to the present embodiment is characterized mainly in that it has a so-called dual damascene structure in which the conductor plug and the wiring are formed of the same conductive layer. As shown in FIG. 9, on a silicon substrate 10,
An interlayer insulating film 40 is formed, and a stopper film 42 is formed on the interlayer insulating film 40. On the stopper film 42, an interlayer insulating film 44 is formed.

A groove 46 is formed in the interlayer insulating film 44 using the stopper film 42 as an etching stopper.
A barrier insulating layer 48 made of a BN film is formed on the side surface inside 6. A wiring 50 made of a Cu layer is formed in the groove 46 in which the barrier insulating layer 48 is formed. Wiring 5
0 is formed on the entire surface of the interlayer insulating film 44 on which the
A stopper film 52 made of a 0 nm SiN film is formed, and a 300 nm-thick HSQ film is formed on the stopper film 52.
An interlayer insulating film 54 made of a film is formed.

On the interlayer insulating film 54, a 50 nm thick S
A stopper film 56 made of an iN film is formed, and an interlayer insulating film 58 made of a 550 nm-thickness FSG film is formed on the stopper film 56. Further, the interlayer insulating film 5
8, a silicon oxide film 60 having a thickness of 50 nm,
A stopper film 62 made of a 0 nm SiN film is sequentially formed.

The stopper film 56 and the interlayer insulating film 54 include
A contact hole 64 reaching the wiring 50 from the surface of the stopper film 56 is formed. The stopper film 62, the silicon oxide film 60, and the interlayer insulating film 58 have a stopper film 6
A groove 66 for burying a wiring reaching the surface of the stopper film 56 from the surface 2 is formed. A barrier insulating layer 68 made of a BN film is formed on the side surface in the groove 66 and the side surface in the contact hole 64.
A wiring 70 and a conductor plug 72 made of the same Cu layer are integrally formed in the groove 66 and the contact hole 64 in which are formed.

According to the present embodiment, the barrier insulating layer made of the same insulating layer is formed in the contact hole and the groove, and the conductor plug and the wiring made of the same conductive film are formed. A semiconductor device can be manufactured by a simpler process than when these are formed. (The Method for Fabricating the Semiconductor Device) Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, transistors and the like (not shown) are formed on the silicon substrate 10 in the same manner as in the first embodiment. Next, an interlayer insulating film 40 made of a silicon oxide film is formed on the entire surface by a plasma CVD method. Next, a stopper film 42 made of a 50 nm-thickness SiN film is formed on the entire surface by a plasma CVD method. Next, an interlayer insulating film 44 made of a silicon oxide film is formed on the entire surface by a plasma CVD method.

Next, the interlayer insulating film 44 is patterned using the stopper film 42 as an etching stopper, thereby forming a groove 46 for embedding the wiring 50. Next, a BN film having a thickness of 30 nm is formed by a plasma CVD method. Next, the BN film in the region excluding the side surface in the groove 46 is etched by anisotropic etching. Thereby, the groove 4
A barrier insulating layer 48 made of a BN film is formed on the side surface inside 6.

Next, a film thickness of 50 is formed on the entire surface by sputtering.
A seed layer made of a Cu layer having a thickness of 1.5 nm is formed, and thereafter, a Cu layer having a thickness of 1.5 μm is formed by a plating method. next,
Polishing is performed by a CMP method until the surface of the interlayer insulating film 44 is exposed, whereby the groove 46 in which the barrier layer 48 is formed is formed.
A wiring 50 made of a Cu layer is formed therein (FIG. 10A).
reference).

Next, the entire surface is formed by a plasma CVD method.
A stopper film 52 made of a 50 nm-thick SiN film is formed. Next, the entire surface is spin-coated to a thickness of 30 μm.
An interlayer insulating film 54 made of a 0 nm HSQ film is formed.
Next, a film thickness of 50 nm is formed on the entire surface by a plasma CVD method.
The stopper film 56 made of the SiN film is formed.

Next, the entire surface is formed by a plasma CVD method.
An interlayer insulating film 58 of a 550 nm-thickness FSG film (Fluoro Silicon Glass), which is a silicon oxide film into which fluorine has been introduced, is formed. Next, a 50 nm-thickness silicon oxide film 60 is formed on the entire surface by a plasma CVD method.

Next, the whole surface is formed by the plasma CVD method.
A stopper film 62 made of a 50 nm-thick SiN film is formed (see FIG. 10B). Next, a photoresist film is formed on the entire surface, and an opening (not shown) in the shape of the contact hole 64 is formed in the photoresist film using a photolithography technique. Thereby, the contact hole 6
As a result, a photoresist mask having an opening of the shape 4 is formed.

Next, using the photoresist mask as a mask, the stopper film 62 and the silicon oxide film 60 are etched. Next, the interlayer insulating film 58 is etched using the stopper film 56 as an etching stopper. Next, the exposed stopper film 56 is etched. Next, the stopper film 52
Is used as an etching stopper to etch the interlayer insulating film 54. Next, the exposed stopper film 52 is etched. Thus, the contact hole 64 reaching the wiring 50
Is formed (see FIG. 11A).

Next, the photoresist mask is removed.
Next, a photoresist film is formed on the entire surface, and an opening (not shown) in the shape of the groove 66 is formed in the photoresist film using a photolithography technique. As a result, a photoresist mask having an opening in the shape of the groove 66 is formed. Next, the stopper film 62 and the silicon oxide film 60 are sequentially etched using the photoresist mask as a mask. Next, the interlayer insulating film 58 is etched using the stopper film 56 as an etching stopper. Thus, a groove 66 for embedding the wiring 70 is formed (see FIG. 11B).

Next, a film thickness of 30
A BN film 67 of nm is formed (see FIG. 12A). Next, the BN film 67 in a region excluding the side surface of the contact hole 64 and the side surface of the groove 66 is etched by anisotropic etching. As a result, the barrier insulating layer 68 is formed on the side surfaces of the groove 66 and the side surfaces of the contact hole 64 (see FIG. 12B).

Next, a film thickness of 5 was formed on the entire surface by sputtering.
A seed layer made of a 0 nm Cu layer is formed, and thereafter, a Cu layer having a thickness of 1.5 μm is formed by plating. Next, the Cu layer is polished by the CMP method until the surface of the stopper film 62 is exposed, whereby the wiring 70 and the conductor plug 72 made of the same Cu layer are formed in the groove 66 and the contact hole 64. (See FIG. 13).

Thus, the semiconductor device according to the present embodiment can be manufactured. (Electrical Characteristics) Next, the electrical characteristics of the semiconductor device according to the present embodiment will be explained. The electrical characteristics of the semiconductor device according to the present embodiment were evaluated by measuring the leak current and the like after the heat treatment at 400 ° C., as in the semiconductor device according to the first embodiment.

As a result, the semiconductor device according to the present embodiment showed no change in the leak current and the like, and exhibited good electrical characteristics. [Modified Embodiments] The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, a Si-based CF film or BN film is used as the barrier insulating layer, but any insulating film may be used as the barrier insulating layer as long as the insulating film has a low dielectric constant that can prevent diffusion of Cu. Can be, for example,
An organic film such as a hydrocarbon-based material or a fluorocarbon-based material that prevents diffusion of Cu can be used. Further, a SiN film can be used as the barrier insulating layer.

In the first embodiment, the interlayer insulating film 30
Although a SiN film was used as a stopper film when etching the substrate, the stopper film is not limited to the SiN film, and any film that functions as a stopper when etching the interlayer insulating film may be used. For example, a BN film or the like may be used.

[0069]

As described above, according to the present invention, the diffusion of Cu can be sufficiently prevented even if it is thin, and the barrier insulating layer having a low dielectric constant is formed on the side surface of the groove. A semiconductor device having a high degree of integration and a high operating speed can be provided by using a wiring made of a Cu layer.

Further, according to the present invention, the diffusion of Cu can be prevented, and since the wiring or the like made of the Cu layer is formed in the opening of the barrier insulating layer having a low dielectric constant, the integration degree is low. A semiconductor device with high operation speed can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 7 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 9 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention;

FIG. 10 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the fourth embodiment of the present invention;

FIG. 11 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the fourth embodiment of the present invention.

FIG. 12 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the fourth embodiment of the present invention.

FIG. 13 is a process sectional view (part 4) illustrating the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Element isolation film 14 ... Side wall insulating film 16 ... Gate electrode 18a, 18b ... Source / drain diffusion layer 20 ... Interlayer insulating film 21 ... Stopper film 22 ... Contact hole 24 ... Barrier layer 26 ... Conductor plug 30 ... interlayer insulating film 32 ... groove 33 ... BN film 33a ... Si based CF film 34 ... barrier insulating layer 34a ... barrier insulating layer 36 ... wiring 38 ... barrier interlayer insulating film 40 ... interlayer insulating film 42 ... barrier insulating layer 44 ... interlayer Insulating film 46 Groove 48 Barrier insulating layer 50 Wiring 52 Stopper film 54 Interlayer insulating film 56 Stopper film 58 Interlayer insulating film 60 Silicon oxide film 62 Stopper film 64 Contact hole 66 Groove 67 BN Film 68 barrier insulating layer 70 wiring 72 conductor plug 110 silicon substrate 112 element isolation film 11 ... Sidewall insulating film 116 ... Gate electrode 118a, 118b ... Source / drain diffusion layer 120 ... Interlayer insulating film 121 ... Stopper film 122 ... Contact hole 124 ... Barrier layer 126 ... Conductor plug 130 ... Interlayer insulating film 132 ... Groove 134 ... Barrier Layer 136: Wiring

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Yoshihiro Nakata 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shiro Yamaguchi 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Fujitsu Limited F-term (reference) 5F033 HH11 JJ11 JJ19 JJ33 KK01 KK11 MM01 MM02 NN06 NN07 PP06 QQ16 QQ25 QQ37 QQ48 RR01 RR04 RR06 RR11 RR12 RR21 SS01 SS02 SS03 SS15 TT02 TT01 TT02 TT01 BD18 BF07 BF24 BF25 BF27 BF30 BH12 BJ02

Claims (8)

[Claims] A first substrate formed on the base substrate and having an opening;
A barrier insulating layer for preventing diffusion of Cu, and a conductive layer formed of a Cu layer formed in the opening, wherein the barrier insulating layer is a silicon-based insulating layer containing carbon and fluorine, an organic film, or A semiconductor device comprising any one of a BN film oriented in a C-axis direction. 2. An insulating layer formed on a base substrate and having an opening, a barrier insulating layer formed on a side surface in the opening to prevent diffusion of Cu, and wherein the barrier insulating layer is formed. A conductive layer made of a Cu layer formed in the opening; and the barrier insulating layer is a silicon-based insulating layer containing carbon and fluorine, an organic film, or a BN film oriented in the C-axis direction. A semiconductor device, characterized in that: A first barrier insulating layer formed on the base substrate and having a first opening to prevent diffusion of Cu; a second barrier insulating layer formed on the first barrier insulating layer; A second barrier insulating layer having an opening and preventing diffusion of Cu; and a conductive layer made of the same Cu layer formed in the first opening and the second opening, The first barrier insulating layer and / or the second barrier insulating layer may be any of a silicon-based insulating layer containing carbon and fluorine, an organic film, or a BN film oriented in the C-axis direction. Characteristic semiconductor device. 4. A first insulating layer formed on a base substrate and having a first opening, and a second insulating layer formed on the first insulating layer and having a second opening. A barrier insulating layer formed on a side surface in the first opening and a side surface in the second opening for preventing diffusion of Cu; and in the first opening on which the barrier insulating layer is formed, and A conductive layer formed of the same Cu layer formed in the second opening; and a second layer formed on a lower surface of the second opening in a region excluding a region in which the first opening is formed. And a third insulating layer for preventing the diffusion of Cu, wherein the barrier insulating layer has a silicon-based insulating layer containing carbon and fluorine, an organic film, or a C-axis direction. A semiconductor device characterized by being one of oriented BN films. 5. A step of forming a barrier insulating layer for preventing diffusion of Cu on a base substrate; a step of forming an opening in the barrier insulating layer; and forming a conductive layer made of a Cu layer in the opening. And a method of manufacturing a semiconductor device. 6. A step of forming an insulating layer on a base substrate, a step of forming an opening in the insulating layer, and a step of forming a barrier insulating layer for preventing diffusion of Cu on a side surface in the opening. And forming a conductive layer made of a Cu layer in the opening where the barrier insulating layer is formed. 7. A step of forming a first barrier insulating layer for preventing diffusion of Cu on a base substrate; and a second barrier insulating layer for preventing diffusion of Cu on the first barrier insulating layer. Forming a first opening in the first barrier insulating layer and forming a second opening in the second barrier insulating layer; and forming the first opening in the first opening and the second opening in the second barrier insulating layer. Forming a conductive layer made of the same Cu layer in the second opening. 8. A step of forming a first insulating layer on a base substrate; a step of forming a second insulating layer for preventing diffusion of Cu on the first insulating layer; Forming a third insulating layer having an etching characteristic different from that of the second insulating layer on the insulating layer, and forming a first opening in the first insulating layer and the second insulating layer. Forming a second opening in the third insulating layer; forming a barrier insulating layer on the side surface in the first opening and the side surface in the second opening to prevent diffusion of Cu; Manufacturing a semiconductor device, comprising: forming a conductive layer made of the same Cu layer in the first opening and the second opening where the barrier insulating layer is formed. Method.