KR960006701B1 - Metal wire forming method of semiconductor device - Google Patents

Abstract

The method of forming a metal line of a semiconductor device includes the steps of forming a transistor and capacitor on a main cell region(30) of a semiconductor substrate(1) and forming an insulating layer(2) thereon, planarizing the substrate by using SOG(6) having etching selectivity to the insulating layer(2), etching back the SOG(6) and interlevel insulating layer(2) and wet-etching the SOG to remove the remaining portion of the SOG(6), simultaneously forming first and second contact holes(4,4') on a peripheral region(20) and main cell region(30), filling the first and second contact holes with selective tungsten, and depositing a metal(7) on the overall surface of the substrate.

Description

Metal wiring formation method of semiconductor device

1 is a process diagram of metallization of a conventional semiconductor device.

2 is a metal wiring forming process diagram of a semiconductor device according to the present invention.

* Explanation of cold protection symbols in the main parts of the drawings

1 semiconductor substrate 2 interlayer insulating film

3: photoresist 4: first contact hole

4 ': second contact hole 5: tungsten

6: SOG 7: Metal

The present invention improves the method of filling contact holes in a peripheral area of a chip and a main cell area of a chip of a semiconductor device, thereby overcoming a topology and thus high ASPECTRATIO. It relates to a method for forming metal wiring of a semiconductor device having a.

In general, ultra high-integrated circuit semiconductor devices require double wiring and more multilayer wiring structures, and should be able to exhibit substantially high reliability and low wiring resistance. It will greatly influence the characteristics.

That is, it is possible to satisfy the effective filling of the contact holes in the peripheral area and the main cell area and the planarization of the grooves generated during the metal wiring, and to overcome the topology of the main cell area and the peripheral area of the semiconductor device and simultaneously between the two areas. It should be able to maintain the uniformity of.

Therefore, in order to open the contact hole of the peripheral region 20 inside the chip, as shown in FIG. 1, an interlayer insulating film 2 is first formed on the semiconductor engine 1 as shown in FIG. As shown in (B), after the photoresist 3 is applied to the entire surface, a first contact hole region is defined through a mask operation, and then the interlayer insulating film 2 is etched using the photoresist 3 as a mask to form a first contact. After the hole 4 is formed, the photoresist 3 is removed.

After the process is completed, the photoresist 3 'is defined in the main cell region 30 by applying the photoresist 3' to the main cell region 30 as shown in (C) and then the photoresist 3 'is defined. When the second contact hole 4 ′ is formed by etching with a mask, the topology of the peripheral area 20 and the main cell area 30 is severely generated.

Thereafter, as shown in (D), a selective tungsten (5) growing only on the semiconductor substrate (1) is deposited for easy contact with the aluminum alloy wiring, so that the first contact hole (4) and the main cell region of the peripheral region (20) are deposited. To fill the second contact hole 4 '.

After the above process, an aluminum alloy is deposited and a separate multilayer interlayer insulating film is formed between the metal layer and the metal layer to planarize the main cell region 30 and the peripheral region 20.

The metal wiring forming method of the conventional semiconductor device as described above not only has to perform double photo masking etching to form contact holes in the peripheral region and the main cell region in the semiconductor device, but also the topology between the peripheral region and the main cell region in the semiconductor device. When the selective tungsten is formed in consideration of the contact hole of the main cell region, it grows excessively than the contact hole height of the peripheral region, as in the dotted line of the contact hole (D) of the peripheral region. In order to planarize the cell regions, a separate multilayer interlayer insulating film needs to be formed, which makes the semiconductor manufacturing process difficult.

In order to solve the problems described above, the present invention is to deposit SOG before forming contact holes in the peripheral region and the main cell region when forming an interlayer insulating layer for planarization due to the severe topology between the peripheral region and the main cell region in the semiconductor device. After adjusting the selectivity between the interlayer insulating film and the SOG, and then performing etch back, the remaining SOG film is subjected to high selectivity wet etching to further ease the topology between the peripheral area and the main cell area. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring in a semiconductor device which can simplify the process by forming a contact hole in the peripheral region and the main cell region at the same time by masking and improve the step coverage. will be.

In the method of forming a metal wiring of the semiconductor device of the present invention, after forming a circuit device such as a transistor and a capacitor in the main cell region 30 on the semiconductor substrate 1, forming an interlayer insulating film 2, the front surface of the Depositing and planarizing the interlayer insulating film 2 and the SOG 6 having a predetermined etching selectivity to a predetermined thickness, and simultaneously etching back the SOG 6 and the interlayer insulating film 2 by a predetermined thickness, and then 6) high selectivity wet etching to remove the remaining SOG (6), applying a photoresist (3) to the front surface and a photo mask operation to define the contact hole region, and exposed to the peripheral region 20 and the main Simultaneously forming first and second contact holes 4 and 4 'in the cell region 30, and growing selective tungsten 7 in the first and second contact holes 4 and 4'. And filling the first and second contact holes 4 and 4 ', and depositing a metal 7 to be used as a wiring on the entire surface. It is broken.

When described with reference to the accompanying drawings as follows.

2 is a process diagram for forming a metal wiring of a semiconductor device according to the present invention, which overcomes the topology by improving the planarization between the peripheral area and the main cell area in the semiconductor device and escapes from the existing double photo masking process, and has a high aspect as a single mask. It is to improve the effective embedding and step coverage of the contact hole having a ratio.

That is, when the transistor and the capacitor are formed in the main cell region 30 on the semiconductor substrate 1 and the interlayer insulating film 2 is deposited, as shown in (a), the severe gap between the peripheral region 20 and the main cell region 30 is shown. The topology is triggered.

At this time, the SOG 6 is deposited to have a thickness of 1,000 to 10,000 Å for planarization before forming the contact hole as shown in (B), and then the selectivity between the interlayer insulating film 2 and the SOG 6 is reduced to 1 as shown in (C). : SOG 6 and interlayer insulating film 2 are simultaneously etched back to a thickness of 1,000 to 5,000 μs so as to minimize the topology between the peripheral area 20 and the main cell area 30 by adjusting to 1 to 1: 1.4. Next, the SOG 6 is removed by high-selective non-wet etching to remove the remaining SOG 6, so that the topology between the peripheral area 20 and the main cell area 30 is not severe even when the contact hole is opened.

After the process is completed, as shown in (D), the photoresist 3 is applied to form contact holes between the peripheral region 20 and the main cell region 30 on the front surface, and then the contact hole region is formed by a pto mask (M) operation. After the definition, the exposure process is performed using the photoresist 3 as a mask to simultaneously form the first and second contact holes 4 and 4 ′ in the peripheral region 20 and the main cell region 30.

Then, as shown in (e), the first and second contact holes 4 and 4 'are buried by growing the selective tungsten 7 or aluminum that grows only on the semiconductor substrate 1. At this time, by growing the selective tungsten (5) or aluminum by the height of the first contact hole (4) of the peripheral region 20 is filled in the contact hole having a high aspect ratio in the main cell region (30).

Since the aluminum alloy 7 to be used as a metal wiring is deposited on the entire surface, excellent step coverage can be obtained in the second contact hole 4 ′ in the main cell region 30.

As described above, according to the present invention, after forming an SOG before forming contact holes in the peripheral region and the main cell region when forming an interlayer insulating layer for planarization due to the severe topology between the peripheral region and the main cell region in the semiconductor device. By adjusting the selectivity between the interlayer insulating film and the SOG and performing etch back, high selectivity wet etching of only the remaining SOG can be performed to further ease the topology between the peripheral area and the main cell area. Not only can contact holes be formed in the main cell area at the same time, but also metal wiring can be improved after selective tungsten growth to improve step coverage.

Claims (6)

In the method of forming a metal wiring of a semiconductor device, after forming circuit elements such as transistors and capacitors in the main cell region 30 on the semiconductor substrate 1, forming an interlayer insulating film (2), and the interlayer on the front surface Depositing and planarizing the insulating film 2 and the SOG 6 having a predetermined etching selectivity to a predetermined thickness, and simultaneously etching back the SOG 6 and the interlayer insulating film 2 by a predetermined thickness, and then SOG 6 ) To remove the residual SOG (6) by high-selectivity wet etching, and to apply the photoresist (3) to the front surface and to apply the photoresist, and to define the contact hole region and to expose the peripheral region 20 and the main cell. Simultaneously forming first and second contact holes 4 and 4 'in the region 30, and growing selective tungsten 7 in the first and second contact holes 4 and 4'. Embedding the first and second contact holes 4 and 4 ', and depositing a metal 7 to be used as the wiring on the entire surface thereof. The metal wiring forming method of the semiconductor device characterized by the above-mentioned. The method of claim 1, wherein the SOG (6) is deposited to a thickness of 1,000 to 10,000 kHz. The method of claim 1, wherein the SOG (6) has an etch back thickness of 1,000 to 5,000 kPa. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the selective etching ratio of the interlayer insulating film (2) and the SOG (6) has a ratio of 1: 1 to l: 1.4. The method of claim 1, wherein the selective tungsten (5) is grown by the thickness of the first contact hole (4) formed in the peripheral region (20). 2. The method for forming metal wiring in a semiconductor device according to claim 1, wherein aluminum is used instead of the selective tungsten (5).