KR100358127B1 - Method for forming contact hole in semiconductor device - Google Patents

Method for forming contact hole in semiconductor device Download PDF

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Publication number
KR100358127B1
KR100358127B1 KR1019950006191A KR19950006191A KR100358127B1 KR 100358127 B1 KR100358127 B1 KR 100358127B1 KR 1019950006191 A KR1019950006191 A KR 1019950006191A KR 19950006191 A KR19950006191 A KR 19950006191A KR 100358127 B1 KR100358127 B1 KR 100358127B1
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South Korea
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insulating layer
layer
forming
contact hole
semiconductor substrate
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KR1019950006191A
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Korean (ko)
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KR960035817A (en
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황준
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

PURPOSE: A method for forming a contact hole in a semiconductor device is provided to be capable of improving the step coverage. CONSTITUTION: A lower layer(22) including a gate electrode and an insulating layer is formed on a semiconductor substrate(21). A planarization layer(23) having a relatively thick thickness is formed on the resultant structure. The planarization layer(23) and the lower layer(22) are selectively etched so as to remain a portion of the lower layer(22). Then, a plug ion-implantation is performed in order to increase etch rate. A contact hole is then formed by blanket-etching of the remaining lower layer(22) together with the over deposited planarization layer.

Description

반도체 소자의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 높은 단차를 갖는 고집적 소자에 적합한 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole suitable for a highly integrated device having a high step.

제 1A 도 내지 제 1C 도는 종래방법에 따른 콘택흘 형성과정을 나타내는 단면도로, 이를 통하여 종래기술을 개략적으로 설명하면 다음과 같다.1A to 1C are cross-sectional views illustrating a contact flow forming process according to a conventional method, which will be described below with reference to the related art.

먼저, 제 1A 도에 도시된 바와 같이 반도체기판(1) 상부에 하지층(2) 형성후 BPSG막(3)을 증착한 다음, 플로우하여 평탄화한다. 상기 하지층(2)은 통상 절연막이다.First, as shown in FIG. 1A, after the base layer 2 is formed on the semiconductor substrate 1, the BPSG film 3 is deposited and then flown and planarized. The base layer 2 is usually an insulating film.

이어서, 제 1B 도에서 상기 BPSG(3)막 및 하지층(2)을 리소그래피 공정으로 선택적으로 제거하여, 콘택 영역의 상기 반도체기판(1)을 노출시킨 후, 노출된 반도체기판 상부로 플러그(plug) 이온주입 공정을 실시한 다음, 고온에서 열처리한다.Subsequently, in FIG. 1B, the BPSG 3 film and the underlying layer 2 are selectively removed by a lithography process to expose the semiconductor substrate 1 in the contact region, and then plug into the exposed semiconductor substrate. ) The ion implantation process is performed, followed by heat treatment at high temperature.

끝으로, 제 1C 도에 도시된 바와 같이 스퍼터링 기법으로 상기 구조 전체 상부에 전도막 예컨대 금속막(4)을 형성한다.Finally, as shown in FIG. 1C, a conductive film such as a metal film 4 is formed over the entire structure by sputtering.

상기 종래방법에 따라 콘택홀을 형성할 경우 고온에 의한 플러그 열처리시 결정결함(crystal defect)을 야기하게 되며, 금속배선 형성후 스텝커버리지(step coverage)특성이 불량해지는 문제점이 따랐다.In the case of forming the contact hole according to the conventional method, crystal defects occur when the plug is heat-treated due to high temperature, and the step coverage characteristic is poor after the metal wiring is formed.

상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 본 발명은 플러그 이온주입 및 열처리에 의한 기판의 결정결함을 방지함과 아울러 높은 단차를 갖는 고집적 소자에서도 콘택홀내에 매립되는 전도막이 양호한 스텝커버리지 특성을 나타내도록 하는데 적합한 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the problems of the prior art as described above prevents the crystal defect of the substrate by plug ion implantation and heat treatment, and also has a good step coverage characteristic of the conductive film embedded in the contact hole even in a highly integrated device having a high step height. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device, which is suitable for the purpose of describing the present invention.

상기 목적을 달성하기 위한 본 발명은, 반도체 소자의 콘택홀 형성방법에 있어서, 반도체기판 상에 제l절연층 형성후 평탄화용 제2절연층을 형성하되, 원하는두께보다 두껍게 제2절연층을 형성하는 제1단계; 콘택마스크를 사용한 리소그래피 공정을 통해 상기 제1 및 제2 절연층을 식각하되, 상기 제1절연층을 상기 반도체기판 상에 일부두께 잔류시키는 제2단계; 플러그 이온주입을 실시하는 제3단계; 및 상기 제2절연층의 과도 증착 두께와 상기 잔류 제1절연막을 블랭킷 식각하여 상기 반도채기판을 노출시키는 제4단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a contact hole in a semiconductor device, wherein after forming a first insulating layer on a semiconductor substrate, a second insulating layer for planarization is formed, and a second insulating layer is formed thicker than a desired thickness. The first step to do; Etching the first and second insulating layers through a lithography process using a contact mask, but leaving the first insulating layer partially on the semiconductor substrate; A third step of performing plug ion implantation; And a fourth step of exposing the semiconductor substrate by blanket etching the overdeposited thickness of the second insulating layer and the remaining first insulating layer.

또한, 본 발명은 반도체 소자의 콘택홀 형성방법에 있어서, 반도체기판에 제1절연층과 평탄화용 제2절연층을 차례로 형성하는 제1단계; 상기 제2절연층 상에 질화층, 액상절연층을 형성하는 제2단계; 콘택마스크를 사용한 리소그래피 공정을 통해 상기 액상절연층, 질화층, 제2 및 제1 절연층을 식각하되, 상기 제l절연층을 상기 반도체기판 상에 일부두께 잔류시키는 제3단계; 플러그 이온주입을 실시하는 제4단계; 및 상기 질화층을 식각정지층으로 이용한 블랭킷 식각으로 상기 액상절연층 및 상기 잔류하는 제1절연층을 식각하는 제5단계를 포함하여 이루어지는 것을 특징으로 한다.In addition, the present invention provides a method for forming a contact hole in a semiconductor device, comprising: a first step of sequentially forming a first insulating layer and a planarizing second insulating layer on a semiconductor substrate; A second step of forming a nitride layer and a liquid insulating layer on the second insulating layer; Etching the liquid insulating layer, the nitride layer, the second and first insulating layers through a lithography process using a contact mask, and leaving the first insulating layer partially on the semiconductor substrate; A fourth step of performing plug ion implantation; And etching the liquid insulating layer and the remaining first insulating layer by blanket etching using the nitride layer as an etch stop layer.

이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 2A 도 내지 제 2D 도는 본 발명의 제1실시예에 따른 콘택홀 형성 후 금속배선 형성과정을 나타내는 단면도로서, 먼저, 제 2A 도에 도시된 바와 같이 반도체기판(21) 상부에 하지층(22) 형성 후 BPSG막(23)을 증착한다. 이때, BPSG막(23)은 평탄화 목적으로 증착되는 종래의 일반적인 두께보다 1.5배 가량 두껍게 과다 증착되도록 한다.2A to 2D are cross-sectional views illustrating a process of forming a metal wiring after forming a contact hole according to a first embodiment of the present invention. First, as shown in FIG. 2A, a base layer 22 is formed on an upper portion of a semiconductor substrate 21. After the formation, the BPSG film 23 is deposited. At this time, the BPSG film 23 is over-deposited about 1.5 times thicker than the conventional general thickness deposited for planarization purposes.

이어서, 제 2B 도에 도시된 바와 같이 상기 BPSG막(23)을 플로우하여 평탄화하되, 단차완화를 위해 플로우가 많이 일어나도록 한 다음. 콘택홀 형성을 위한 식각마스크로 사용될 감광막패턴(50)을 형성한다.Subsequently, as shown in FIG. 2B, the BPSG film 23 is flowed and planarized, and a lot of flow occurs to reduce the step difference. A photoresist pattern 50 to be used as an etching mask for forming a contact hole is formed.

계속해서, 제 2C 도에서와 같이 상기 감광막패턴(25)을 식각마스크로 사용하여 하부의 상기 BPSG막(23), 하지층(22)을 식각하되, 하지층이 일부두께 잔류하도록(A)한 다음, 플러그 이온주입 공정을 실시하여 잔류되는 하지층을 뚫고 반도체기판(21)에 이온이 주입되도록 한다. 이때의 이온주입으로 콘택 영역의 상기 BPSG막(23)과 하지층(22)의 식각률(etch rate)(후속 공정의 습식 식각률)이 증대된다.Subsequently, as shown in FIG. 2C, the lower BPSG film 23 and the underlying layer 22 are etched using the photosensitive film pattern 25 as an etching mask, but the underlying layer remains partially thick (A). Next, a plug ion implantation process is performed to penetrate the remaining underlayer to inject ions into the semiconductor substrate 21. The ion implantation at this time increases the etch rate (wet etch rate in subsequent steps) of the BPSG film 23 and the underlying layer 22 in the contact region.

끝으로, 제 2D도에 도시된 바와 같이 상기 플러그 이온주입 후 열처리 한 다음, 습식식각으로 상기 BPSG(23)막 및 상기 잔류 하지층(A)을 식각하되. 상기 BPSG막(23)은 과다증착된 두께만큼을 전면적으로 제거하고, 콘택영역의 잔류 하지층(A)은 모두 제거함으로써 콘택영역의 상기 반도체기판(21)을 노출시킨 다음, 금속물질을 증착하여 금속배선(24)을 형성한다.Finally, as shown in FIG. 2D, after the plug ion implantation and heat treatment, the BPSG layer 23 and the residual underlying layer A are etched by wet etching. The BPSG film 23 completely removes the overdeposited thickness and removes all the remaining underlayer A of the contact region, thereby exposing the semiconductor substrate 21 in the contact region, and then depositing a metal material. The metal wiring 24 is formed.

제 3A 도 내지 제 3D 도는 본 발명의 제2실시예에 따른 콘택홀 형성과정을 나타내는 단면도로서, 제1실시예와는 달리 BPSG막을 정규두께로 형성하면서 결정결함 및 스텝커버리지를 향상시킬 수 있는 콘택홀 형성 방법을 보여준다.3A to 3D are cross-sectional views illustrating a process of forming a contact hole according to a second embodiment of the present invention. Unlike the first embodiment, a contact that can improve crystal defects and step coverage while forming a BPSG film at a regular thickness is shown in FIG. Demonstrate the hole formation method.

먼저, 제 3A도에 도시된 바와 같이 반도체기판(31) 상부에 하지층(32) 형성후 BPSG막(33)을 증착한 후 플로우한다. 계속해서, 상기 BPSG막(33) 상부에 질화막(36), 액상절연체(liquid phase dielectric, LPD)막(37)을 증착하여 평탄화한다. 이때, 질화막(36)은 액상절연체막의 식각정지층 역할을 하게되며, 후속 공정에서 과도식각에 의한 추가적인 BPSG막의 손실을 방지한다.First, as shown in FIG. 3A, after forming the base layer 32 on the semiconductor substrate 31, the BPSG film 33 is deposited and then flows. Subsequently, a nitride film 36 and a liquid phase dielectric (LPD) film 37 are deposited and planarized on the BPSG film 33. In this case, the nitride film 36 serves as an etch stop layer of the liquid insulator film, and prevents the loss of additional BPSG film due to overetching in a subsequent process.

이어서, 제 3B 도에서 콘택홀 형성을 위한 식각마스크로 사용될 감광막패턴(35)을 형성한다.Subsequently, a photosensitive film pattern 35 to be used as an etching mask for forming a contact hole is formed in FIG. 3B.

계속해서, 제 3C 도에서 상기 감광막패턴(35)을 식각마스크로 하부의 콘택영역의 상기 액상절연체막(37), 질화막(36), BPSG막(33) 및 하지층(32)을 식각하되, 하지층(32)이 일부두께 잔류하도록(B)한 다음, 플러그 이온주입 공정을 실시하여 잔류되는 하지층을 뚫고 반도체기판(31)에 이온이 주입되도록 한다. 이때의 이온주입으로 콘택 영역의 상기 BPSG막(33)과 하지층(32)의 식각률(etch rate)(후속 공정의 습식 식각률)이 증대된다.Subsequently, in FIG. 3C, the liquid insulator film 37, the nitride film 36, the BPSG film 33, and the underlayer 32 of the contact region under the photoresist film pattern 35 are etched. After the underlying layer 32 remains a part of thickness (B), a plug ion implantation process is performed to penetrate the remaining underlying layer and inject ions into the semiconductor substrate 31. The ion implantation at this time increases the etch rate (wet etch rate in a subsequent process) of the BPSG film 33 and the underlying layer 32 in the contact region.

끝으로, 제 3D도에 도시된 바와 같이 상기 플러그 이온주입 후 열처리 한 다음, 상기 질화막(36)을 식각정지층으로 블랭킷 식각하여 상기 액상절연체막(37), 잔류하는 하지층(32)을 제거한다.Finally, as shown in FIG. 3D, after the plug ion implantation and heat treatment, the nitride layer 36 is blanket-etched with an etch stop layer to remove the liquid insulator layer 37 and the underlying layer 32. do.

본 실시예들에서는 BPSG막을 사용하고 있으나 당업자에게 잘 알려진 바와 같이 BPSG막 대신에 BSP, PSG 등 기타 불순물을 포함하는 절연막을 사용할 수 있으며, 하지층은 TEOS막과 같은 절연층을 사용할 수 있다.In the present exemplary embodiment, a BPSG film is used, but as is well known to those skilled in the art, an insulating film containing other impurities such as BSP and PSG may be used instead of the BPSG film, and an insulating layer such as a TEOS film may be used as the underlying layer.

상기와 같이 이루어지는 본 발명은 고집적 소자에 적합한 미세 콘택홀을 형성할 수 있으며, 플러그 이온주입 및 열처리에 의한 기판의 결정결함을 방지함과 아울러 콘택홀 상부의 완만한 식각으로 스텝커버리지 특성이 향상되는 효과를 얻을 수 있다.The present invention made as described above can form a fine contact hole suitable for the highly integrated device, and prevents the defects of the crystallization of the substrate by plug ion implantation and heat treatment, and improves step coverage characteristics by gentle etching on the upper portion of the contact hole. The effect can be obtained.

제 1 도는 종래방법에 따른 콘택홀 형성 후 금속배선 형성과정을 나타내는 단면도.1 is a cross-sectional view showing a metal wiring forming process after forming a contact hole according to the conventional method.

제 2 도는 본 발명의 제1실시예에 따른 콘택홀 형성후 금속배선 형성과정을 나타내는 단면도.2 is a cross-sectional view illustrating a metal wiring formation process after forming a contact hole according to a first embodiment of the present invention.

제 3 도는 본 발명의 제2실시예에 따른 콘택홀 형성과정을 나타내는 단면도.3 is a cross-sectional view illustrating a process of forming a contact hole according to a second embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21, 31 : 반도체기판 22, 32 : 하지층21, 31: semiconductor substrate 22, 32: underlayer

23, 33 : BPSG 막 24, 34 : 금속배선23, 33: BPSG film 24, 34: metal wiring

25, 35 : 감광막패턴 36 : 질화막25, 35 photosensitive film pattern 36: nitride film

37 : 액상절연체막37: liquid insulator film

Claims (6)

반도체 소자의 콘택홀 형성방법에 있어서,In the method of forming a contact hole of a semiconductor device, 반도체기판 상에 제1절연층 형성후 평탄화용 제2절연층을 형성하되, 원하는 두께보다 두껍게 제2절연층을 형성하는 제1단계;A first step of forming a second insulating layer for planarization after forming the first insulating layer on the semiconductor substrate, wherein the second insulating layer is formed thicker than a desired thickness; 콘택마스크를 사용한 리소그래피 공정을 통해 상기 제1 및 제2 절연층을 식각하되, 상기 제l절연층을 상기 반도체기판 상에 일부두께 잔류시키는 제2단계:A second step of etching the first and second insulating layers through a lithography process using a contact mask, and leaving the first insulating layer partially on the semiconductor substrate; 플러그 이온주입을 실시하는 제3단계; 및A third step of performing plug ion implantation; And 상기 제2절연층의 과도 증착 두께와 상기 잔류 제l절연막을 블랭킷 식각하여 상기 반도체기판을 노출시키는 제4단계A fourth step of exposing the semiconductor substrate by blanket etching the excess deposition thickness of the second insulating layer and the remaining first insulating layer; 를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.A contact hole forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제2절연층은 불순물을 함유한 절연층인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And the second insulating layer is an insulating layer containing impurities. 제2항에 있어서,The method of claim 2, 상기 불순물을 함유한 절연층은 BPSG 층인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And the insulating layer containing the impurity is a BPSG layer. 제3항에 있어서,The method of claim 3, 상기 제1단계에서 상기 BPSG층은 예정된 두께의 1.5배 두께로 과다 증착한후, 플로우시킴으로써 형성되는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein the BPSG layer is formed by over-depositing and then depositing 1.5 times the predetermined thickness. 반도체 소자의 콘택홀 형성방법에 있어서,In the method of forming a contact hole of a semiconductor device, 반도체기판에 제1절연층과 평탄화용 제2절연층을 차례로 형성하는 제1단계;A first step of sequentially forming a first insulating layer and a planarizing second insulating layer on the semiconductor substrate; 상기 제2절연층 상에 질화층, 액상절연층을 형성하는 제2단계;A second step of forming a nitride layer and a liquid insulating layer on the second insulating layer; 콘택마스크를 사용한 리소그래피 공정을 통해 상기 액상절연층, 질화층, 제2 및 제1 절연층을 식각하되, 상기 제1절연층을 상기 반도체기판 상에 일부두께 잔류시키는 제3단계;Etching the liquid insulating layer, the nitride layer, the second and first insulating layers through a lithography process using a contact mask, and leaving the first insulating layer partially on the semiconductor substrate; 플러그 이온주입을 실시하는 제4단계; 및A fourth step of performing plug ion implantation; And 상기 질화층을 식각정지층으로 이용한 블랭킷 식각으로 상기 액상절연층 및 상기 잔류하는 제1절연층을 식각하는 제5단계A fifth step of etching the liquid insulating layer and the remaining first insulating layer by a blanket etching using the nitride layer as an etch stop layer 를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.A contact hole forming method of a semiconductor device comprising a. 제5항에 있어서,The method of claim 5, 상기 제2절연층은 BPSG층인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And the second insulating layer is a BPSG layer.
KR1019950006191A 1995-03-23 1995-03-23 Method for forming contact hole in semiconductor device KR100358127B1 (en)

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