JPH1064995A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the multi-layer wiring in which a capacitance between wires is reduced without increasing the number of process stages. SOLUTION: At first after a low dielectric constant film 3 whose dielectric constant is lower than that of an insulation film 2 is formed on the insulation film 2 in a state of covering a conductor layer 1, a groove 4 for forming a wire is formed to the low dielectric constant film 3 in a way that the groove width is made narrower from an upper part of the groove 4 toward the lower part. Then a connection hole 5 in communication with the groove 4 and reaching the conductor layer 1 is formed to the insulation film 2. Succeedingly a wiring material film 6 is formed on the low dielectric constant film 3, the inside of the connection hole 5 and of the groove 4. Then the wiring material film 6 on the low dielectric constant film 3 is removed while leaving the wiring material film 6 in a state of imbeding the inside of the groove 4 so as to obtain an upper layer wire 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a multilayer wiring.

[0002]

2. Description of the Related Art With the high integration of ULSI, the demand for fine processing technology is becoming more and more severe. In particular, in recent device structures in which the adoption of multilayer wiring is unavoidable, the introduction of embedded wiring technology such as a dual damascene (Dual Damascene) method capable of improving the flatness of an insulating film formed on the wiring is required. .

In the conventional embedded wiring technique, for example, when forming an embedded wiring shown in FIG. 8, first, a second insulating film 53 is formed on a first insulating film 52 formed so as to cover a lower wiring 51.
To form The first insulating film 52 is made of, for example, silicon oxide (SiO ₂ ), and the second insulating film 53 is made of, for example, SiO 2.
_It is made of a low dielectric material having a dielectric constant lower than ₂ . Then
The second insulating film 5 is formed by lithography and etching.
A groove 54 is formed in 3. Subsequently, a groove 5 is formed in the first insulating film 52.
4 and a connection hole 55 reaching the lower wiring 51 is formed. Thereafter, a metal material film is formed on the second insulating film 53, and a metal material film is formed inside the groove 54 and inside the connection hole 55. By removing the excess wiring material film on the second insulating film 53 while leaving the wiring material film in a state where the inside of the groove 54 is buried, a buried wiring 56 as an upper layer wiring is formed.

[0004]

However, as the wiring structure becomes more multilayered and the pattern becomes finer, the problem is the increase in wiring capacitance. In a future device, particularly, an increase in capacitance between wirings in the same layer (layer) may cause a delay in the operation speed of the device and increase power consumption. Therefore, as shown in FIG. 8, a method of reducing the capacitance between wirings by using a low dielectric film such as a silicon-based oxide containing fluorine (SiOF) or an organic polymer as an insulating film between wirings has been proposed. .

However, recent studies have confirmed that when a low dielectric film is formed only between wirings, the effect of reducing the capacitance is not so large. Also, the reason is that electric field (line of electric force) leaks from upper and lower portions of the wiring having a substantially rectangular cross-sectional shape, and the leaked electric field is caused by a high dielectric constant SiO ₂ insulating film existing in the upper and lower layers of the wiring. Has been found to cross the This finding is obtained from the result of simulating the state of the electric lines of force between the wires by passing a signal through the wires. Based on the above findings, in order to reduce the capacitance between wirings by using a low dielectric film, it is only necessary to form the low dielectric film so as to cover the entire wiring. It has been found to reach a practical level.

However, in practice, when a low dielectric film is formed above and below a wiring by a conventional embedded wiring technique, a problem occurs in that the number of steps is increased. Therefore, there is a need for establishing a technology capable of reducing the capacitance between wirings without increasing the number of steps.

[0007]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an insulating film covering a conductive layer in a first step; After forming a low dielectric film having a low dielectric constant, a groove for forming a wiring is formed in the low dielectric film so that the groove width becomes narrower from the upper part to the lower part of the groove. Next, in a second step, a connection hole communicating with the groove and reaching the conductive layer is formed in the insulating film. Subsequently, in a third step, a wiring material film is formed on the inside of the connection hole and the inside of the groove together with the low dielectric film, and in a fourth step, the inside of the connection hole and the inside of the groove are buried. Then, the wiring material film on the low dielectric film is removed while leaving the wiring material film.

According to the first aspect of the present invention, since the groove is formed in the low dielectric film so that the groove width decreases from the upper part to the lower part,
A groove having a smaller width at the bottom of the groove formed by the upper surface of the low dielectric film is obtained as compared with the groove formed by the conventional method.
That is, on the lower side of the groove, the groove is formed in a state in which the low-dielectric film enters the inside of the groove more than the side surface of the groove formed by the conventional method. Therefore, by forming a wiring material film inside the trench, a wiring is formed in which a lower part of the wiring is surrounded by a low dielectric film as compared with the related art. Also, after forming the groove, a contact hole communicating with the groove and reaching the conductive layer is formed, and a wiring material film is also formed inside the connection hole, so that a contact portion for electrically connecting the wiring and the conductive layer is also provided. It is formed. Further, since the grooves are formed in the same number of steps as the formation of the grooves in the conventional method, the total number of steps is not increased as compared with the conventional method.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, a low dielectric film having a lower dielectric constant than the insulating film is formed on the insulating film formed so as to cover the conductive layer in the first step. After the formation, a hole reaching the conductive layer is formed in the insulating film and the low dielectric film. Next, in a second step, a groove for forming a wiring is formed in the low dielectric film by reducing the width of the groove from the upper part to the lower part of the groove and opening the hole at the interface between the insulating film and the low dielectric film. It is formed to include a part. And in the third step,
A wiring material film is formed on the low dielectric film as well as inside the connection hole formed by the hole formed in the insulating film and inside the groove. Thereafter, the fourth step described in the first aspect of the present invention is performed.

According to the third aspect of the present invention, since the groove is formed so as to include the opening of the hole at the interface between the insulating film and the low dielectric film, the groove communicating with the connection hole formed by the hole formed in the insulating film is formed. can get. Further, since the grooves are formed in the same number of steps as the grooves in the conventional method, the total number of steps is not increased as compared with the conventional method. Also, in the present invention, since the groove is formed so that the groove width becomes narrower from the upper part to the lower part, as in the first aspect of the present invention, the lower part of the wiring is surrounded by a low dielectric film as compared with the prior art. Wiring is formed.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, a low dielectric film having a lower dielectric constant than the insulating film is formed on the insulating film formed so as to cover the conductive layer in the first step. After the formation, when forming a groove for forming a wiring in the low dielectric film, the groove is formed while leaving the low dielectric film at the bottom of the groove.
Then, the second, third, and fourth steps described in the first aspect of the present invention are performed.

According to the fifth aspect of the present invention, after forming the groove so as to leave the low dielectric film at the bottom of the groove, the wiring material film is formed inside the groove. A wiring whose part and bottom are surrounded by the low dielectric film is formed.
Further, since the grooves are formed in the same number of steps as the grooves in the conventional method, the total number of steps is not increased as compared with the conventional method.

[0013] In a method of manufacturing a semiconductor device according to a sixth aspect of the present invention, a low dielectric film having a lower dielectric constant than the insulating film is formed on the insulating film formed so as to cover the conductive layer in the first step. After the formation, a hole reaching the conductive layer is formed in the insulating film and the low dielectric film. Next, in the second step, when forming a groove for forming a wiring in the low dielectric film, the low dielectric film is left at the bottom of the groove, and the opening of the hole at the interface between the insulating film and the low dielectric film is formed. A groove is formed to include the portion. Then, the third step and the fourth step described in the third aspect of the invention are performed.

According to the sixth aspect of the present invention, when forming the groove, the groove is formed so as to include the opening of the hole at the interface between the insulating film and the low dielectric film. A groove communicating with the hole is obtained. Further, since the grooves are formed in the same number of steps as the grooves in the conventional method, the total number of steps is not increased as compared with the conventional method. Also in this invention, since the groove is formed so as to leave the low dielectric film at the bottom of the groove, similar to the invention of claim 5, except for the portion where the connection hole is formed,
A wiring is formed in which both sides and the bottom are surrounded by the low dielectric film.

[0015]

Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a first embodiment, which is one embodiment of the first and second aspects of the present invention, in the order of steps, and particularly shows a step of forming a multilayer wiring which is a feature of these aspects of the present invention.

In this method, first, a first step shown in FIGS. 1A and 1B is performed. That is, as shown in FIG. 1A, a low dielectric film 3 having a lower dielectric constant than the insulating film 2 is formed on the insulating film 2 formed so as to cover the conductive layer 1.
The conductive layer 1 is composed of a lower wiring formed of a metal material such as aluminum (Al). The insulating film 2
For example, it is made of a normal insulating material such as SiO ₂ . The low dielectric film 3 is formed, for example, by SiO ₂ (dielectric constant ε = 4.
0) and a method such as a coating method or a chemical vapor deposition method (hereinafter, referred to as a CVD method).

For example, as the low dielectric film 3 having a dielectric constant lower than 4.0, SiOF (ε = 3.7 to 3.2), organic SOG (Spin on glass) (ε = 3.5 to 3) A film made of a polyimide-based polymer (ε = 3.5-3) having a structure represented by the formula [1] in FIG. 2 or a polyimide-based polymer (ε = about 2.7) further doped with fluorine, etc. Is mentioned. Further, a polytetrafluoroethylene-based polymer [for example, amorphous Teflon (trade name)] having the structure represented by the formula [2] in FIG. Fluorinated polymer [eg Cytop (trade name)] (ε = 2.
1), benzocyclobutene (BCB) (ε = about 2.6) having a structure represented by the formula [4] in FIG. 3, and the formula [5] in FIG.
A film made of a fluorinated polyallyl ether-based polymer (ε = 2.6) having the structure shown in (1), a polyparaxylylene to which fluorine is added (ε = about 2.4), or the like is used as the low dielectric film 3.
Can also be used. Note that the low dielectric film 3 is not limited to these examples, and any material may be used as long as it has a lower dielectric constant than the insulating film 2.

An example of a condition for forming a low dielectric film 3 made of a fluorinated polyallyl ether-based polymer represented by the formula [5] in FIG. 3 on an insulating film 2 made of, for example, SiO ₂ will be described below. Show. This is because the insulating film 2 is formed using a spin coater.
Apply a fluorinated polyallyl ether-based polymer on top,
This is the condition for forming the low dielectric film 3 after drying and annealing. Rotation speed of spin coater: 3000 rpm Drying condition: 200 ° C., 1 minute Annealing condition: 400 ° C., 1 minute

After forming the low dielectric film 3, a resist pattern is formed on the low dielectric film 3 by lithography (not shown). Then, by etching using the resist pattern as a mask, as shown in FIG. 1B, a groove 4 for forming a wiring is formed in the low dielectric film 3. At this time, the groove 4 is formed such that the groove width becomes narrower from the upper part to the lower part of the groove 4 and the bottom of the groove 4 is formed by the upper surface of the low dielectric film 3. Further, the side surface 4a of the groove 4 is formed in a curved surface or a planar shape. FIG. 1B shows a case where the groove 4 is formed in a substantially semicircular cross section as an example when the side surface 4a of the groove 4 is formed in a curved surface. Groove 4
As an example when the side surface 4a is formed in a planar shape, there is a case where the groove 4 is formed in a so-called reverse tapered shape as shown in FIG.

For forming such a groove 4, for example, 10P
Under a relatively high pressure equal to or higher than a, a dry etching method using plasma that generates a deposition product, an isotropic dry etching method using radicals, or the like can be used. The former dry etching method performs plasma etching under a relatively high pressure, thereby restricting the incidence of ions near the corners of the groove 4 and generating a depositable product during the etching, so that the This is a method of processing the groove 4 so that the groove width decreases toward the lower part. Examples of the plasma that generates a deposition product include CF-based plasma generated by using a fluorocarbon (CF _x ) -based etching gas. When using a CF _x -based etching gas is, C
The shape of the groove 4 can be controlled to some extent by the composition ratio of F and F.

The latter method using isotropic dry etching mainly involves a radical reaction with the low dielectric film 3 or the etching mask, so that the groove width decreases from the upper part to the lower part. This is a method of processing No. 4. For example, when the low dielectric film 3 is made of a polymer containing carbon, oxygen that burns and reacts with carbon is introduced into the etching atmosphere to increase the isotropic etching component composed of oxygen radicals, thereby forming the groove 4 as described above. It is processed into various shapes.

An example of conditions for forming the groove 4 to have a substantially semicircular cross section by a method of performing plasma etching under a relatively high pressure will be described below. This is a condition when a magnetron type reactive ion etching (RIE) device is used. Etching gas and flow rate: C ₄ F ₈ / Ar / O ₂ = 5
0 sccm / 100 sccm / 20 sccm [sccm
Is the volume flow rate (cm ³ / min) in the standard state.] Atmospheric pressure: 50 Pa RF power: 1.2 kW Substrate temperature: 30 ° C. After the groove 4 is formed, the mask made of the resist pattern is removed.

Next, a resist pattern is formed on the low dielectric film 3 by lithography (not shown). Then, as shown in FIG. 1C, the connection holes 5 are formed in the insulating film 2 by etching using the resist pattern as a mask.
To form At this time, the connection hole 5 is formed so as to communicate with the groove 4 and reach the conductive layer 1 (second step). After that, the resist pattern is removed.

Subsequently, as shown in FIG.
The wiring material film 6 is formed on the low dielectric film 3 by the VD method, and the wiring material film 6 is formed inside the connection hole 5 and inside the groove 4 (third step). Here, for example, a wiring material film 6 made of Al is formed so as to bury the inside of the connection hole 5 and the groove 4. Wiring material film 6 inside connection hole 5
Is formed, a contact portion 7 for electrically connecting the upper wiring 7 and the conductive layer 1 is formed. The material for forming the wiring material film 6 is not limited to Al, and any material can be used as long as it is a conductive material. As an example, a metal material such as Cu and metal silicide can be given.

Then, as shown in FIG. 1E, the low dielectric film 3 is left while the wiring material film 6 is left in a state where the inside of the groove 4 is buried.
The upper surplus wiring material film 6 is removed (fourth step). As a result, an upper wiring 8 in which the wiring material film 6 is embedded in the trench 4 is formed in the low dielectric film 3. As a method of removing the wiring material film 6, for example, a chemical mechanical polishing (CMP) method, an etch back, or the like can be used. Here, the wiring material film 6 made of Al is removed by the CMP method. Through the above steps, a multilayer wiring in which the upper wiring 8 is a buried wiring and the upper wiring 8 and the conductive layer 1 are electrically connected via the contact portions 7 is formed.

In the method of the first embodiment described above, the groove 4 for the upper wiring 8 is formed so that the groove width becomes narrower from the upper part to the lower part. The groove 4 having a small width at the bottom of the groove 4 can be obtained. In other words, the groove 4 can be formed in a state where the low dielectric film 3 enters the inside of the groove 4 below the groove 4 than the side surface of the groove having a substantially U-shaped cross section formed by the conventional method. As a result, by forming the wiring material film 6 inside the groove 4,
Since the upper wiring 8 surrounded by the low dielectric film 3 can be formed also on the lower side, compared with the conventional case, the leakage of electric lines of force from the lower part of the upper wiring 8 when a signal flows through the upper wiring 8 is suppressed. Thus, it is possible to prevent the leaked electric lines of force from crossing the insulating film 2 existing below the upper wiring 8. Therefore, it is possible to obtain a multilayer wiring in which the capacitance between the upper wiring 8 and the conductive layer 1 is reduced.

Further, by forming the side surface 4a of the groove 4 into a curved surface, the upper wiring 8 having no corners at the bottom can be formed.
It is possible to prevent the lines of electric force from the upper wiring 8 from being concentrated on the lower part. Then, it is possible to prevent a decrease in the electrical reliability of the upper wiring 8 due to the concentration of the electric flux lines. Further, in this method, the groove 4 is formed in the same number of steps as the formation of the groove in the conventional method.
Multilayer wiring can be formed without increasing the total number of steps. Further, since the groove 4 can be easily processed by the conventional technique, and a normal multi-layer wiring processing process can be adopted for steps other than the processing of the groove 4, the above-described method can be easily realized. The effect is also obtained. Therefore, by using the method for manufacturing a semiconductor device according to the first embodiment, it is possible to manufacture a semiconductor device that has high integration, operates at high speed, and has good device characteristics such as low power consumption.

Next, a second embodiment, which is one embodiment of the third and fourth aspects of the present invention, will be described with reference to FIG. FIG. 5 is a diagram showing a step of forming a multilayer wiring, which is a feature of the present invention. In FIG. 5,
The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. In the second embodiment, first, FIG.
The first step shown in (a) and (b) is performed. The step illustrated in FIG. 5A is similar to the step described with reference to FIG. 1A of the first embodiment. That is, a low dielectric film 3 having a lower dielectric constant than the insulating film 2 is formed on the insulating film 2 formed so as to cover the conductive layer 1.

Next, a resist pattern is formed on the low dielectric film 3 by lithography (not shown). Then, by etching using the resist pattern as a mask, holes 11 reaching the conductive layer 1 are formed in the low dielectric film 3 and the insulating film 2 as shown in FIG. Then, the mask made of the resist pattern is removed. Subsequently, as shown in FIG. 5C, a groove 4 for forming a wiring is formed in the low dielectric film 3 (second step). At this time, the opening (not shown) of the hole 11 at the interface between the insulating film 2 and the low dielectric film 3
Is formed to include a hole 11 formed in the insulating film 2 and a connection hole 5 communicating with the groove 4 is obtained. Further, the groove 4 is processed so that the groove width becomes narrower from the upper part to the lower part of the groove 4. At this time, the side surface 4a of the groove 4 is formed in a curved surface or a planar shape. In FIG. 5C, the side surface 4 of the groove 4 is shown.
As an example when a is formed in a curved shape, a case where the groove 4 is formed in a substantially semicircular cross section is shown.

As described above, the groove 4 is formed by a dry etching method using a plasma that generates a deposition product under a relatively high pressure, an isotropic method using a radical, or the like. A typical dry etching method can be used. After processing the groove 4 by etching, the mask made of the resist pattern is removed. Thereafter, as shown in FIGS. 5D and 5E, the third step and the fourth step described in the first embodiment are sequentially performed to form the contact portions 7 in the insulating film 2 and to form the grooves. An upper wiring 8 in which a wiring material film 6 is buried inside 4 is formed on the low dielectric film 3.

Through the above steps, a multilayer wiring in which the upper wiring 8 is a buried wiring and the upper wiring 8 and the conductive layer 1 are electrically connected through the contact portion 7 is formed. In the method of the second embodiment, the groove 4 is formed so as to include the opening of the hole 11 at the interface between the insulating film 2 and the low dielectric film 3. Therefore, according to this method, the groove 4 communicating with the connection hole 5 including the hole 11 formed in the insulating film 2 is also provided.
Can be formed. Also in this method, the multi-layer wiring can be formed in the same number of steps as the conventional method, and a normal multi-layer wiring processing process can be adopted in the steps other than the processing of the groove 4, so that it can be easily realized. Such an effect can be obtained.

Also, as in the first embodiment, the groove 4 for the upper wiring 8 is formed so that the width of the groove becomes narrower from the upper part to the lower part. Thus, it is possible to obtain a multilayer wiring in which the capacitance between the upper wiring 8 and the conductive layer 1 is reduced. Also, the side surface 4 of the groove 4
By forming a into a curved shape, it is possible to prevent a decrease in the electrical reliability of the upper wiring 8 due to the concentration of the electric flux lines. Therefore, even with the method of manufacturing a semiconductor device according to the second embodiment, it is possible to manufacture a semiconductor device that is highly integrated and has good device characteristics such as device operation speed and power consumption.

Next, a third embodiment, which is one embodiment of the invention of claim 5, will be described with reference to FIG. FIG. 6 is a diagram showing a step of forming a multilayer wiring, which is a feature of the present invention. In this figure, the same components as those of the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted. In the third embodiment, first, FIG.
The first step shown in (b) is performed. FIG. 6A is a process similar to the process described with reference to FIG. 1A of the first embodiment, and the insulating film 2 is formed on the insulating film 2 formed so as to cover the conductive layer 1. Also, the low dielectric film 3 having a low dielectric constant is formed.

Next, a resist pattern is formed on the low dielectric film 3 by lithography (not shown). Then, as shown in FIG. 6B, a groove 21 for forming a wiring having a substantially U-shaped cross section is formed in the low dielectric film 3 by etching using this resist pattern as a mask. On this occasion,
The groove 21 is formed such that the low dielectric film 3 is left at the bottom of the groove 21. For the formation of such a groove 21, ordinary anisotropic etching, for example, a dry etching method using plasma can be used. When etching,
For example, by controlling the etching time, the groove 21 is formed at a predetermined depth, and the low dielectric film 3 is formed on the bottom of the groove 21.
To leave. The etching time can be calculated from the etching rate obtained in advance and the obtained etching rate.

An example of the etching conditions is shown below. Etching gas and flow rate: C ₄ F ₈ / CO / Ar = 2
0 sccm / 180 sccm / 10 sccm Atmospheric pressure: 1.0 Pa RF power: 1.2 kW Substrate temperature: 30 ° C. In this etching, for example, when the depth of the groove 21 becomes about 90% of the thickness of the low dielectric film 3 To stop processing. In the formation of the groove 21, it is important that the depth of the groove 21 is accurately and uniformly formed. This is because the variation in the depth of the groove 21 may appear as it is as a change in the resistance of an upper wiring 22 described later formed using the groove 21. After forming the groove 21 in this manner, the mask made of the resist pattern is removed.

Next, a resist pattern is formed on the low dielectric film 3 by lithography (not shown). Then, as shown in FIG. 6C, the connection holes 5 are formed in the insulating film 2 by etching using the resist pattern as a mask.
To form At this time, the connection hole 5 is formed so as to communicate with the groove 21 and reach the conductive layer 1 (second step). After that, the resist pattern is removed. Then, the same processing as the third step and the fourth step described in the first embodiment is performed. That is, as shown in FIG.
The wiring material film 6 is formed on the low dielectric film 3 by the method, and the wiring material film 6 is formed inside the connection hole 5 and inside the groove 21 (third step). The contact portion 7 is formed by forming the wiring material film 6 inside the connection hole 5.

Then, as shown in FIG.
The excess wiring material film 6 on the low dielectric film 3 is removed by the MP method while leaving the wiring material film 6 so as to fill the trench 21 (fourth step). As a result, an upper wiring 22 in which the wiring material film 6 is embedded in the groove 21 is formed in the low dielectric film 3. Through the above steps, a multilayer wiring in which the upper wiring 22 is a buried wiring and the upper wiring 22 and the conductive layer 1 are electrically connected via the contact portion 7 is formed.

In the method of the third embodiment, the grooves 21
A groove 21 for the upper wiring 22 is formed so as to leave the low dielectric film 3 at the bottom of the substrate. For this reason, except for the connection part with the contact part 7, the upper layer wiring 22 whose both sides and the bottom are surrounded by the low dielectric film 3 can be formed. Therefore, when a signal flows through the upper wiring 22, the lines of electric force from the bottom of the upper wiring 22 are separated from the insulating film 2 existing under the upper wiring 22.
Since leakage and crossing can be further suppressed, it is possible to obtain a multilayer wiring in which the capacitance between the upper wiring 22 and the conductive layer 1 is further reduced.

Also in this method, a multilayer wiring can be formed without increasing the number of steps as compared with the conventional method. Further, the groove 21 can be easily processed by a conventional technique, and a normal multi-layer wiring processing process can be employed for steps other than the processing of the groove 21. Therefore, the above-described method can be easily realized. There is also an effect that there is. Therefore, by using the method for manufacturing a semiconductor device according to the third embodiment, it is possible to manufacture a highly integrated semiconductor device that operates at higher speed and has better device characteristics such as lower power consumption.

Next, a fourth embodiment, which is one embodiment of the invention of claim 6, will be described with reference to FIG. FIG.
FIG. 2 is a view showing a step of forming a multilayer wiring, which is a feature of the present invention. Also, in FIG. 7, the first to third embodiments are described.
The same components as those of the embodiment are denoted by the same reference numerals, and description thereof is omitted. In the fourth embodiment, first, FIG.
As shown in (a) and (b), by performing the first step described in the second embodiment, a low dielectric having a lower dielectric constant than the insulating film 2 is formed on the insulating film 2 covering the conductive layer 1. The film 3 is formed, and a hole 11 reaching the conductive layer 1 is formed in the low dielectric film 3 and the insulating film 2.

Next, a resist pattern is formed on the low dielectric film 3 by lithography (not shown). Then, as shown in FIG. 7C, a groove 21 for forming a wiring having a substantially U-shaped cross section is formed in the low dielectric film 3 by etching using this resist pattern as a mask. On this occasion,
A groove 21 is formed so as to include an opening (not shown) of the hole 11 at an interface between the insulating film 2 and the low dielectric film 3, and a connection hole formed of the hole 11 of the insulating film 2 and communicating with the groove 21. Get 5. Further, the groove 21 is formed so as to leave the low dielectric film 3 at the bottom of the groove 21 (second step).

For the formation of such a groove 21, for example, a dry etching method using plasma can be used as described in the third embodiment. At the time of etching, the groove 21 is formed at a predetermined depth by controlling the etching time, for example, so that the low dielectric film 3 is left at the bottom of the groove 21. As described above, the groove 2
In the formation of No. 1, it is important to form the depth of the groove 21 accurately and uniformly. After forming the groove 21 in this manner, the mask made of the resist pattern is removed.

Thereafter, as shown in FIGS. 7D and 7E, the third step and the fourth step described in the third embodiment are sequentially performed to form the contact portions 7 on the insulating film 2. At the same time, an upper wiring 22 in which the wiring material film 6 is embedded in the groove 21 is formed in the low dielectric film 3. By the above steps, the upper wiring 22 is a buried wiring and the upper wiring 2
A multilayer wiring in which the conductive layer 2 and the conductive layer 1 are electrically connected via the contact portion 7 is formed.

In the method according to the fourth embodiment, the groove 21 is formed so as to include the opening of the hole 11 at the interface between the insulating film 2 and the low dielectric film 3.
A groove 21 communicating with the connection hole 5 composed of the hole 11 formed in the insulating film 2 can be obtained. Also in this method, the multi-layer wiring can be formed in the same number of steps as the conventional method, and a normal multi-layer wiring processing process can be adopted in the steps other than the processing of the groove 21, so that it can be easily realized. Such an effect can be obtained. Further, similarly to the third embodiment, a groove 21 for the upper layer wiring 22 is formed at the bottom thereof with the low dielectric film 3.
Are formed so that the leakage of electric lines of force from the bottom of the upper layer wiring 22 can be further suppressed, and the upper layer wiring 22 and the conductive layer 1 are formed.
And a multilayer wiring with a further reduced capacitance between them. Therefore, even with the method of manufacturing a semiconductor device according to the fourth embodiment, a highly integrated semiconductor device with better device characteristics can be manufactured.

In the third and fourth embodiments, the case where the groove is formed in a substantially U-shaped cross section has been described. However, the groove may be formed with the low dielectric film left at the bottom. Needless to say, the invention is not limited to this example. In the first to fourth embodiments, the case where the conductive layer is a wiring has been described. However, the conductive layer may be, for example, a diffusion layer formed on a substrate. Further, the present invention is not limited to the first to fourth embodiments, and the shape, processing conditions, and the like can be appropriately changed without departing from the gist of the present invention.

[0046]

As described above, according to the method of manufacturing a semiconductor device according to the first aspect of the present invention, a groove is formed so that a groove width is reduced from an upper part to a lower part, and a wiring material is formed inside the groove. Since the wiring is obtained by forming the film, when a signal flows through the wiring, it is possible to significantly suppress leakage of electric lines of force from below the wiring to the insulating film below the wiring. Thus, a multilayer wiring with reduced capacitance between the wiring and the conductive layer can be obtained. Further, since the groove can be formed in the same number of steps as the formation of the groove in the conventional method, a multilayer wiring can be formed without increasing the number of steps as compared with the conventional method.

According to the second aspect of the present invention, since the groove is formed so as to include the opening of the hole at the interface between the insulating film and the low dielectric film, the groove communicates with the connection hole formed by the hole formed in the insulating film. Groove can be obtained. Further, by forming the groove in the same manner as in the first aspect of the present invention, it is possible to form a wiring in which leakage of electric lines of force from the lower part is significantly suppressed, and the number of components is the same as that of the conventional method. Since this groove can be formed, it is possible to obtain a multilayer wiring in which the capacitance between the wiring and the conductive layer is reduced without increasing the number of steps as in the first aspect.

According to the fifth aspect of the present invention, a groove is formed so as to leave a low dielectric film at the bottom of the groove, and a wiring material film is formed inside the groove to obtain a wiring. When flowing, it is possible to significantly suppress leakage of electric lines of force from below the wiring to the insulating film. Thus, a multilayer wiring with reduced capacitance between the wiring and the conductive layer can be obtained. Further, since the groove can be formed in the same number of steps as the formation of the groove in the conventional method, a multilayer wiring can be formed without increasing the number of steps as compared with the conventional method.

According to the sixth aspect of the present invention, since the groove is formed so as to include the opening of the hole at the interface between the insulating film and the low dielectric film, the groove communicating with the connection hole formed of the hole in the insulating film is formed. Can be obtained. By forming the groove in the same manner as in the fifth aspect of the present invention, the leakage of electric lines of force from the lower part can be formed significantly, and the groove can be formed by the same number of steps as in the conventional method. Since it can be formed, a multilayer wiring having a reduced capacitance between the wiring and the conductive layer can be obtained without increasing the total number of steps, as in the fifth aspect. Therefore, according to the first, third, fifth and sixth aspects of the present invention, a semiconductor device having high device characteristics such as high integration, high-speed operation and low power consumption can be manufactured. It can be manufactured without increasing the number.

[Brief description of the drawings]

FIGS. 1A to 1E are diagrams illustrating a first embodiment of the present invention in the order of steps, and are diagrams illustrating one embodiment of the first and second aspects of the present invention.

FIG. 2 is a diagram (part 1) illustrating an example of a material used for forming a low dielectric film.

FIG. 3 is a diagram (part 2) illustrating an example of a material used for forming a low dielectric film.

FIG. 4 is a diagram showing another example of forming a groove side surface.

FIGS. 5A to 5E are views for explaining a second embodiment of the present invention in the order of steps, and are views showing one embodiment of the third and fourth aspects of the present invention.

6 (a) to 6 (e) are views for explaining a third embodiment of the present invention in the order of steps, and are views showing one embodiment of the invention of claim 5; FIG.

FIGS. 7A to 7E are views for explaining a fourth embodiment of the present invention in the order of steps, and are views showing one embodiment of the invention of claim 6;

FIG. 8 is a diagram illustrating an example of a conventional method in the order of steps.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 conductive layer 2 insulating film 3 low dielectric film 4
21 groove 4a side surface 5 connection hole 6 wiring material film 8,
22 Upper layer wiring 11 holes

Claims (6)

[Claims] An insulating film formed so as to cover the conductive layer, a low dielectric film having a lower dielectric constant than the insulating film is formed, and a wiring forming groove is formed in the low dielectric film. A first step of forming a groove width narrower from an upper part to a lower part of the groove; a second step of forming a connection hole communicating with the groove and reaching the conductive layer in the insulating film; A third step of forming a wiring material film inside the connection hole and inside the groove together with the body film, and leaving the wiring material film in a state where the inside of the connection hole and the inside of the groove are buried. A fourth step of removing the wiring material film on the low dielectric film. 2. When forming a groove in the first step,
2. The method according to claim 1, wherein a side surface of the groove is formed into a curved surface or a planar shape. 3. A low dielectric film having a lower dielectric constant than the insulating film is formed on the insulating film formed so as to cover the conductive layer, and then the conductive film is formed on the insulating film and the low dielectric film. A first step of forming a hole reaching a layer, a groove for forming a wiring in the low dielectric film, a groove width is reduced from an upper part to a lower part of the groove, and the insulating film and the low dielectric film are formed. A second step of forming an opening of the hole at the interface with the substrate, wiring on the low dielectric film, inside the connection hole formed of the hole formed in the insulating film, and inside the groove. A third step of forming a material film; and a fourth step of removing the wiring material film on the low dielectric film while leaving the wiring material film in a state of filling the inside of the connection hole and the inside of the groove. A method for manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 3, wherein in forming the groove in the second step, a side surface of the groove is formed in a curved surface or a planar shape. 5. A low dielectric film having a lower dielectric constant than the insulating film is formed on the insulating film formed so as to cover the conductive layer, and a trench for forming a wiring is formed in the low dielectric film. A first step of forming the groove while leaving the low dielectric film at the bottom of the groove; and a second step of forming a connection hole in the insulating film that communicates with the groove and reaches the conductive layer. A third step of forming a wiring material film on the low dielectric film, inside the connection hole and inside the groove; and forming the wiring material film so as to bury the inside of the connection hole and the inside of the groove. Removing the wiring material film on the low-dielectric film while leaving the semiconductor device. 6. After forming a low dielectric film having a lower dielectric constant than the insulating film on the insulating film formed so as to cover the conductive layer, the conductive film is formed on the insulating film and the low dielectric film. A first step of forming a hole reaching a layer; and, when forming a groove for forming a wiring in the low dielectric film, leaving the low dielectric film at the bottom of the groove, and forming the insulating film and the low dielectric substance. A second step of forming the groove so as to include an opening of the hole at an interface with a film; and, on the low dielectric film, inside of a connection hole formed of a hole formed in the insulating film, and A third step of forming a wiring material film therein and a step of removing the wiring material film on the low dielectric film while leaving the wiring material film in a state of filling the inside of the connection hole and the inside of the groove; A method for manufacturing a semiconductor device, comprising four steps.