KR100234372B1 - Method of manufacturing insulator of semiconductor device - Google Patents

Method of manufacturing insulator of semiconductor device Download PDF

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KR100234372B1
KR100234372B1 KR1019970006810A KR19970006810A KR100234372B1 KR 100234372 B1 KR100234372 B1 KR 100234372B1 KR 1019970006810 A KR1019970006810 A KR 1019970006810A KR 19970006810 A KR19970006810 A KR 19970006810A KR 100234372 B1 KR100234372 B1 KR 100234372B1
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insulating film
film
hdp
forming
chemical mechanical
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KR19980069650A (en
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김창규
홍석지
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윤종용
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

HDP(High Density Plasma)를 이용한 절연막과 이보다 연마율이 낮은 박막을 형성한 뒤 선택적 화학기계적 연마를 수행하여 반도체 장치 절연막의 글로벌 평탄화를 달성하는 방법. 본 발명의 방법은 HDP(Density Plasma)를 이용한 절연막 형성단계와, 상기 HDP막에 비해 연마율이 낮은 박막을 형성하는 단계와, 화학기계적 연마법을 이용하여 절연막을 평탄화시키는 단계를 포함한다. 본 발명에서 적용된 HDP CVD막은 증착공정과 식각 공정이 동시에 진행되기 때문에 패턴 상단 측면에서 박막 증착속도가 매우 낮아진다. 따라서 셀과 같이 크기가 작은 패턴의 상부에 낮은 절연막이 증착되고, 큰 패턴의 상부와 필드 영역에서는 두꺼운 절연막이 증착된다. HDP CVD막을 증착한 후 연마율이 보다 낮은 박막을 증착하고 선택적 화학기계적 연마를 진행하면 평탄도가 크게 향상되어진다.A method of achieving global planarization of a semiconductor device insulating film by forming an insulating film using a high density plasma (HDP) and a thin film having a lower polishing rate and then performing selective chemical mechanical polishing. The method includes forming an insulating film using Density Plasma (HDP), forming a thin film having a lower polishing rate than the HDP film, and planarizing the insulating film using a chemical mechanical polishing method. In the HDP CVD film applied in the present invention, since the deposition process and the etching process are performed at the same time, the deposition rate of the thin film is very low at the upper side of the pattern. Therefore, a low insulating film is deposited on top of a small pattern like a cell, and a thick insulating film is deposited on top of a large pattern and a field region. After depositing the HDP CVD film and depositing a thinner film having a lower polishing rate and performing selective chemical mechanical polishing, the flatness is greatly improved.

Description

반도체 장치의 절연막 평탄화 방법Insulating Planarization Method of Semiconductor Device

본 발명은 반도체 장치의 제조방법에 관한 것으로, 상세하게는 반도체 장치의 절연막 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of planarizing an insulating film of a semiconductor device.

반도체 장치가 고집적화됨에 따라 사진 공정에서의 공정 마아진을 확보하고 배선 길이를 최소화하기 위해 저유전막 평탄화 기술이 요구된다. 하부막을 평탄화하기 위한 방법으로 BPSG(borophosphosilicate glass) 리플로우, SOG(spin on glass) 또는 포토레지스트의 에치백, 화학기계적 연마(CMP:chemical mechanical polishing) 등을 사용할 수 있다. CMP 공정은 리플로우 공정이나 에치백 공정으로는 달성할 수 없는 넓은 영역에서의 글로벌 평탄화 및 저온 평탄화를 달성할 수 있어 차세대 평탄화 기술로 부상하고 있다.As semiconductor devices become highly integrated, low dielectric film planarization techniques are required to secure process margins in the photolithography process and to minimize wiring lengths. As a method for planarizing the lower layer, borophosphosilicate glass (BPSG) reflow, spin on glass (SOG) or etch back of photoresist, chemical mechanical polishing (CMP), or the like may be used. The CMP process is emerging as the next generation planarization technology because it can achieve global planarization and low temperature planarization in a wide area that cannot be achieved by the reflow process or the etch back process.

그러나 CMP 공정은 단차와 레이아웃에 따라 평탄도 특성에 영향을 받는 문제가 있다. 구체적으로 넓은 영역이 과도식각되어 움푹하게 파이는 디슁현상이 야기되어 글로벌 평탄화를 달성하는데 한계가 있다.However, the CMP process has a problem that the flatness characteristics are affected by the step and the layout. In particular, a large area is over-etched, causing a deep digging phenomenon, which limits the global planarization.

본 발명은 글로벌 평탄화를 달성할 수 있는 절연막 평탄화 방법을 제공하는 것을 기술적 과제로 한다.An object of the present invention is to provide an insulating film planarization method capable of achieving global planarization.

도 1 내지 도 5는 본 발명에 따른 반도체 장치의 절연막 평탄화 방법을 설명하기 위한 단면도들이다.1 to 5 are cross-sectional views illustrating an insulating film planarization method of a semiconductor device according to the present invention.

본 발명은 HDP(High Density Plasma)를 이용한 층간절연막 형성단계와, 상기 HDP막에 비해 연마율이 낮은 박막을 형성하는 단계와, CMP 공정을 이용하여 절연막을 평탄화시키는 단계를 포함하는 것을 특징으로 한다.The present invention includes forming an interlayer insulating film using HDP (High Density Plasma), forming a thin film having a lower polishing rate than the HDP film, and planarizing the insulating film using a CMP process. .

HDP CVD막은 그 형성시에 증착과 식각공정이 동시에 진행되기 때문에 어스펙트 비가 높은 단차 부분에서 갭(gap)이 효과적으로 채워지는 특징을 가지고 있다. 상기 HDP CVD막을 증착한 후 BN(boron nitride)막과 같이 연마율이 낮은 막을 증착하고 선택적 CMP 공정을 진행함으로써 절연막의 평탄화를 달성할 수 있다.The HDP CVD film has a feature that a gap is effectively filled in a step portion having a high aspect ratio because the deposition and etching processes are performed simultaneously. After the deposition of the HDP CVD film, a film having a low polishing rate such as a boron nitride (BN) film may be deposited and a planarization of the insulating film may be achieved by performing a selective CMP process.

본 발명에서 적용된 HDP CVD막에서는 증착공정과 식각 공정이 동시에 진행되기 때문에 패턴 상단 측면에서 박막 증착속도가 매우 낮아진다. 따라서 셀과 같이 크기가 작은 패턴의 상부에 낮은 절연막이 증착되고, 큰 패턴의 상부와 필드 영역에서는 두꺼운 절연막이 증착된다. HDP CVD막 증착 후 CMP 공정을 진행하면 디슁현상이 발생하나, 본 발명의 방법에 따라 HDP CVD막을 증착한 후 연마율이 보다 낮은 막을 증착하고 선택적 CMP 공정을 진행하면 평탄도가 크게 향상되어진다.In the HDP CVD film applied in the present invention, since the deposition process and the etching process are performed at the same time, the deposition rate of the thin film is very low at the upper side of the pattern. Therefore, a low insulating film is deposited on top of a small pattern like a cell, and a thick insulating film is deposited on top of a large pattern and a field region. Dip phenomenon occurs when the CMP process is performed after the deposition of the HDP CVD film. However, according to the method of the present invention, when the HDP CVD film is deposited, a film having a lower polishing rate is deposited and the CMP process is performed to improve the flatness significantly.

이하 도면을 참조하여 본 발명을 보다 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1을 참조하면, 제1 절연막(10) 상에 제1 도전선(11)을 형성하고 이 제1 도전선(11) 상에 제2 절연막(12)으로 HDP CVD막을 증착한다. HDP CVD막으로는 유전율이 낮은 SiOF막이 바람직하다. 상기 제1 절연막(10)으로는 산화막을 사용하는 것이 바람직하다.Referring to FIG. 1, a first conductive line 11 is formed on a first insulating film 10, and an HDP CVD film is deposited on the first conductive line 11 with a second insulating film 12. As the HDP CVD film, a SiOF film having a low dielectric constant is preferable. It is preferable to use an oxide film as the first insulating film 10.

도 2를 참조하면, 상기 제2 절연막(12)인 HDP CVD막 상에 연마율(polishing rate)이 보다 낮고 저유전율을 가진 제3 절연막(13)을 형성한다. 상기 제3 절연막(13)으로 BN(boron nitride)막, CN(carbon nitride)막, SOG막, 또는 저유전 폴리머막을 사용하는 것이 바람직하다. 상기 제3 절연막(13)은 플라즈마 장치 또는 고밀도 플라즈마 장치를 이용하여 형성할 수 있다. 상기 제3 절연막(13)의 연마율은 상기 제2 절연막인 HDP CVD막(12)에 비해 1/50에 불과하여 무시할 수 있을 정도로 작다.Referring to FIG. 2, a third insulating film 13 having a lower polishing rate and a lower dielectric constant is formed on the HDP CVD film, which is the second insulating film 12. It is preferable to use a boron nitride (BN) film, a carbon nitride (CN) film, an SOG film, or a low dielectric polymer film as the third insulating film 13. The third insulating layer 13 may be formed using a plasma apparatus or a high density plasma apparatus. The polishing rate of the third insulating film 13 is negligible since it is only 1/50 of the HDP CVD film 12 which is the second insulating film.

도 3을 참조하면, 상기 제3 절연막(13)과 제2 절연막(12)을 CMP 공정으로 연마하여 글로벌 평탄화를 달성한다. 이때 제3 절연막(13')의 연마율이 제2 절연막(12)의 연마율에 비해 무시할 수 있을 정도로 작기 때문에 선택적 연마(selective polishing)를 이용하여 글로벌 평탄도를 용이하게 얻을 수 있다.Referring to FIG. 3, the third insulating layer 13 and the second insulating layer 12 are polished by a CMP process to achieve global planarization. In this case, since the polishing rate of the third insulating layer 13 ′ is negligibly small compared to the polishing rate of the second insulating layer 12, global flatness can be easily obtained by using selective polishing.

도 4를 참조하면, 상기 연마 공정을 수행한 후 제4 절연막(14)을 형성하는 공정을 더 수행할 수 있다. 상기 제4 절연막(14)은 p-TEOS 산화막, BN, CN, SiOF, 및 p-SiH4산화막으로 이루어진 군에서 선택된 적어도 하나로 이루어지는 것이 바람직하다.Referring to FIG. 4, a process of forming the fourth insulating layer 14 may be further performed after the polishing process. The fourth insulating layer 14 is preferably made of at least one selected from the group consisting of a p-TEOS oxide film, BN, CN, SiOF, and p-SiH 4 oxide film.

도 5를 참조하면, 비아 콘택을 형성한 후 텅스텐 플러그(15)와 제2 도전선(16)을 형성한다. 상기 공정을 반복하여 다층 배선을 형성할 수 있다.Referring to FIG. 5, after forming the via contact, a tungsten plug 15 and a second conductive line 16 are formed. The above process can be repeated to form a multilayer wiring.

본 발명에 의하면, HDP CVD막을 증착한 후 HDP CVD막에 비해 연마율이 낮은 막을 증착하고 CMP 공정을 진행하기 때문에 디슁현상 등이 발생하지 않고 글로벌 평턴화가 용이하게 달성되어지는 효과가 있다.According to the present invention, since the deposition rate of the film having a lower polishing rate than the HDP CVD film and the CMP process are performed after the deposition of the HDP CVD film, global flattening can be easily achieved without the occurrence of the phenomenon of dipping.

이상, 본 발명을 도면을 참조하여 설명하였으나 이는 설명의 편의를 위한 것이지 본 발명의 범위를 이에 한정시키는 것은 아니다. 당업계에서 평균적인 지식을 가진 자에 있어 본 발명은 많은 변형이 가능한 것이다. 예컨대, 본 발명에 적용될 수 있는 층간절연막은 IMD(intermetallic dielectric)막 뿐만 아니라 ILD(interlayer dielectric)막도 포함하는 것이다.As mentioned above, although this invention was demonstrated with reference to drawings, this is for convenience of description and does not limit the scope of the present invention to this. For those of ordinary skill in the art, the present invention is capable of many variations. For example, the interlayer insulating film applicable to the present invention includes not only an intermetallic dielectric (IMD) film but also an interlayer dielectric (ILD) film.

Claims (5)

제1 절연막 상에 도전선을 형성하는 단계;Forming a conductive line on the first insulating film; 상기 도전선 상에 제2 절연막으로 HDP CVD막을 형성하는 단계;Forming an HDP CVD film on the conductive line with a second insulating film; 상기 제2 절연막 상에 상기 제2 절연막보다 연마율이 낮은 제3 절연막을 형성하는 단계; 및Forming a third insulating film on the second insulating film, the third insulating film having a lower polishing rate than the second insulating film; And 상기 제3 절연막과 제2 절연막을 화학기계적 연마법으로 연마하되, 상기 제3절연막과 제2절연막 간의 연마율의 차이를 이용하여 선택적 연마가 되어지도록 하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 절연막 평탄화 방법.Polishing the third insulating film and the second insulating film by chemical mechanical polishing, and performing selective polishing by using a difference in polishing rate between the third insulating film and the second insulating film. Insulation planarization method. 제1항에 있어서, 상기 제2 절연막이 SiOF로 이루어진 것을 특징으로 하는 반도체 장치의 절연막 평탄화 방법.The method of claim 1, wherein the second insulating film is made of SiOF. 제1항에 있어서, 상기 제3 절연막이 BN, CN, SOG, 및 저유전 폴리머로 이루어진 군에서 선택된 어느 하나의 저유전막으로 이루어진 것을 특징으로 하는 반도체 장치의 절연막 평탄화 방법.The method of claim 1, wherein the third insulating film is made of any one of a low dielectric film selected from the group consisting of BN, CN, SOG, and a low dielectric polymer. 제1항에 있어서, 상기 제1 절연막이 산화막으로 이루어진 것을 특징으로 하는 반도체 장치의 절연막 평탄화 방법.The method of claim 1, wherein the first insulating film is formed of an oxide film. 제1항에 있어서, 상기 화학기계적 연마 단계 후에, p-TEOS 산화막, BN, CN, SiOF, 및 p-SiH4산화막으로 이루어진 군에서 선택된 적어도 하나의 절연막을 증착하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 절연막 평탄화 방법.The method of claim 1, further comprising, after the chemical mechanical polishing step, depositing at least one insulating film selected from the group consisting of a p-TEOS oxide film, BN, CN, SiOF, and p-SiH 4 oxide film. An insulating film planarization method of a semiconductor device.
KR1019970006810A 1997-02-28 1997-02-28 Method of manufacturing insulator of semiconductor device KR100234372B1 (en)

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