KR20020051350A - Conductive lines and interconnections in semiconductor devices and forming method thereof - Google Patents

Abstract

PURPOSE: An interconnection and an interconnection connecting portion are provided to reduce a resistance of an interconnection and a capacitance variety between the interconnection and an insulating layer and to prevent an electromigration by forming a swollen portion on the interconnection. CONSTITUTION: An interconnection and an interconnection connecting portion comprises insulating layers made of a first, a second and a third insulating layers(21,22,23) formed on a semiconductor substrate(20), a hole formed in the first and second insulating layers(21,22) to expose the semiconductor substrate(20), a trench having a defined interconnection pattern formed in the insulating layer(23), a barrier(240) formed to contact with the exposed semiconductor substrate(20) on the inner surfaces of the hole and trench, a first conductive layer(250) completely filled into the hole and trench, and a second conductive layer(26) made of a copper layer formed on only the first conductive layer(250) so as to form a swollen portion.

Description

Wiring and wiring connecting portion of semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring and wiring connection portions of semiconductor devices and a method of manufacturing the same. In particular, a via hole, which is a connection portion of an upper wiring to be connected to a lower conductive layer, and a trench in which an upper wiring is to be formed are formed in an insulating layer, and then a barrier layer and copper, etc. A conductive layer of the via hole and the trench, and then the first CMP using the barrier layer on the insulating layer as the polishing stop layer was applied to the conductive layer, and then the exposed barrier layer and part of the insulating layer were removed by buffing CMP. After flattening the surface and depositing the conductive layer on the entire surface again by PVD, and again conducting a second CMP on the conductive layer, the upper surface of the remaining conductive layer is convex and the conductive layer is reinforced with the form of the partially protruded portion over the insulating layer. It prevents the change of wiring resistance and electron transfer phenomenon, reduces the change of parasitic capacitance, ensures the uniform thickness of insulation layer and reduces defects. One relates to the structure of wiring and the wiring connection part and a manufacturing method of a semiconductor device and drinking.

The wiring connection part and wiring for the electrical connection between the elements of the semiconductor device and the formation technology thereof are formed by forming a plug in a contact hole or a via hole of an interlayer insulating layer, and then patterning the wiring on the plug. Deeper, low step coverage, short circuit between wirings, and thus yield of product is poor.

In order to improve this, a dual damascene structure has been proposed as a method of forming a contact plug and a wiring at the same time. However, such a structure and its manufacturing method are excellent in mitigating a step difference from the surroundings. Further improvements in step coverage and reduced resistance at the wiring connections are needed.

In addition, in the conventional art of forming copper metal wiring and wiring connection portions, a copper layer is formed as a conductive layer in a hole or a trench by electroplating, and then a CMP is applied to the copper layer to expose the surface of the insulating layer. The wiring connecting portion and the wiring are formed at the same time.

However, the chemical mechanical polishing (CMP) for the copper layer has a large difference in the polishing ratio between the copper / barrier layer and the insulating layer, so that the upper surface of the copper layer remaining in the trenches forming the respective wirings is centered by dishing. The sharpening of the stiffening resulted in a concave profile (see FIG. 1C), while the erosion of the region having a large pattern density was intensified due to the partial difference in the pattern density as a whole, and the overall cross-sectional profile was also concave (FIG. 1D). Reference).

Therefore, in the related art, the resistance change due to the loss of the metal wiring and the thickness of the insulating layer are lowered, thereby increasing the parasitic capacitance between the wirings.

1A to 1D are process cross-sectional views showing a wiring of a semiconductor device and a method of forming a connection portion thereof according to the prior art.

Referring to FIG. 1A, a first insulating layer 11 is deposited on a semiconductor substrate 10 made of silicon or the like by an oxide film or the like by chemical vapor deposition (hereinafter, referred to as CVD).

Next, in order to use the etch stop layer on the first insulating layer 11, the second insulating layer 12 is thinly formed of an insulating material having a large etching selectivity with the first insulating layer. In this case, the second insulating layer 12 may be formed by depositing a nitride film by CVD.

Then, the third insulating layer 13 is deposited on the second interlayer insulating layer by using an interlayer dielectric layer 13 with an oxide film or the like. In this case, the third insulating layer 13 may be formed by combining tetra ethyl ortho silicate (TEOS) and spin on glass (SOG), and a main component thereof is SiO ₂ .

In the above description, the substrate 10 may be a semiconductor substrate having an impurity diffusion region (not shown) or a lower wiring.

In addition, contact holes H1 to via holes H1 and upper wirings which expose conductive regions of the substrate by patterning predetermined portions of the third, second and first insulating layers 13, 12, and 11 by photolithography. The pattern forms a recessed trench T1. That is, in a subsequent process, a plug for connecting conductive regions such as upper and lower wirings is formed in the via hole H1, and upper wirings are simultaneously formed in the trench.

At this time, the contact hole and the trench are patterned at the same time, the method can be carried out as follows.

First, the first hole defining the via hole forming portion is formed by removing the third and second insulating layers 13 and 12 to a predetermined depth.

In addition, an etching mask in which the upper wiring trench pattern is defined is formed on the third insulating layer 13 on the portion including the first hole, and then the third insulating layer 13 is removed by dry etching using the etching mask. To form a trench. Therefore, during the trench formation etching, the first insulating layer 11 under the first hole is simultaneously etched to simultaneously form the via hole H1 having the upper portion extended with the trench T1.

Referring to FIG. 1B, the barrier layer 14 is contacted with a physical vapor deposition (PVD) or ionized metal plasma (IMP) to contact the substrate 10 exposed through trenches and via holes on the remaining third insulating layer 13. Form by law. At this time, the barrier layer 14 is formed by depositing Ti, TiN, Ta, TaN and the like.

Then, the conductive layer 15 is formed on the barrier layer 14 to form the upper wiring. In this case, when the conductive layer is formed using Cu, a copper seed layer (not shown) for forming a copper bulk layer on the surface of the barrier layer 14 is also deposited by PVD method. After the formation, the copper bulk layer 15 is formed to a thickness sufficiently filling the contact holes and the trenches by elecroplating using the copper seed layer. Thus, via holes were filled with a copper layer to simultaneously form interconnects and upper wiring forming layers.

Referring to FIG. 1C, a planarization process is performed on the formed copper bulk layer to expose the surface of the remaining third insulating layer 13 to form an upper interconnection electrically connected to the exposed conductive region of the substrate without a separate patterning process. At this time, the planarization process is performed by chemical mechanical polishing (CVD). At this time, a dishing phenomenon occurs in which the upper portion of the remaining conductive layer 150 is concave due to a difference in the polishing ratio between the copper and the oxide film, and the maximum thickness of the center of the center portion reaches 'D1'.

Meanwhile, referring to FIG. 1D, in the region where the pattern density of the upper wiring 150 is high, erosion of the third insulating layer 13 and the conductive layer 150 is simultaneously performed to concave the overall cross-sectional profile. Form, eroded up to 'E' in the center.

Therefore, the wiring connecting portion and the wiring forming method of the semiconductor device according to the prior art are parasitic between wirings due to the increase in resistance according to the dipping of the copper layer, which is the metal wiring, and the thickness of the third insulating layer, which is the inter metal dielectric layer. There is a problem that capacitance increases.

Accordingly, an object of the present invention is to form a via hole, which is a connection portion of an upper wiring to be connected to a lower conductive layer, and a trench to form an upper wiring in a cutout layer, and then form a conductive layer such as a barrier layer and copper on the inner surface of the hollow hole and the trench. After forming the first CMP using the barrier layer on the insulating layer as the polishing stop layer in the conductive layer, the exposed barrier layer and part of the insulating layer are removed by buffing CMP to planarize the upper surface, and then the entire conductive layer is again covered by PVD. Deposited on the conductive layer and subjected to the second CMP again to form a wiring having a convex upper surface of the remaining conductive layer and a reinforced conductive layer partially protruding over the insulating layer to change the wiring resistance and the electron transfer phenomenon. Damascene structure wiring and wiring connections of semiconductor devices to prevent parasitic capacitance change, to ensure uniform insulation thickness, and to reduce defects To provide a crude method.

Wiring and wiring connection portion of the semiconductor device according to the present invention for achieving the above object, an insulating layer formed on the semiconductor substrate, a portion of the lower portion of the insulating layer is removed extending from the hole and the hole to expose a predetermined portion of the substrate A portion of the insulating layer is removed to form a trench having a predetermined wiring pattern, a barrier layer formed on an inner surface of the hole and the trench in contact with the exposed substrate, and a contact with the barrier layer in contact with the barrier layer. And a second conductive layer formed only on the upper surface of the first conductive layer so as to partially protrude from the surface of the insulating layer.

Preferably, the first conductive layer is a copper layer formed by a plating method and the second conductive layer is formed of a copper layer formed by physical vapor deposition (PVD), and the upper profile of the second conductive layer is flat or convex. Has

According to an aspect of the present invention, there is provided a method of manufacturing a wiring and wiring connection part of a semiconductor device, the method including forming a wiring insulating layer on a semiconductor substrate, and partially removing a lower portion of the insulating layer to expose a predetermined portion of the substrate. Forming a trench having a predetermined wiring pattern by partially removing a hole and an upper portion of the insulating layer, and forming a barrier layer on an inner surface of the hole and the trench in contact with the exposed substrate; And forming a first conductive layer on the insulating layer in contact with the barrier layer and completely filling the holes and trenches, and first chemical mechanical polishing using the barrier layer on the insulating layer as an abrasive stop layer. Conducting a first conductive layer to leave the first conductive layer only inside the holes and trenches; the exposed barrier layer and the Performing a buffing chemical mechanical polishing on top of the substrate to remove a portion of the insulating layer and remove a portion of the upper surface of the first conductive layer; Forming a second conductive layer by physical vapor deposition; and performing a second chemical mechanical polishing on the second conductive layer to expose the upper surface of the insulating layer, and depositing the second conductive layer only on the upper surface of the first conductive layer. It comprises a step of remaining.

Preferably, the first conductive layer is formed of copper formed by the plating method, the second conductive layer is formed of copper formed by the physical vapor deposition, the second conductive layer is formed within 1000 kPa, the buffing chemical mechanical polishing The thickness of the insulating layer removed by the maximum is 500 kPa or less, and the first chemical mechanical polishing and the buffing chemical mechanical polishing are performed in the same equipment.

1A to 1D are cross-sectional views illustrating a method of manufacturing wirings and wiring connectors of a semiconductor device according to the related art.

2A through 2F are cross-sectional views illustrating a method of manufacturing wirings and wiring connectors of a semiconductor device according to the present invention.

Figure 3 is a cross-sectional view of the wiring and wiring connection of the semiconductor device manufactured according to the present invention

The present invention forms a trench in which an via hole or a contact hole and a wiring pattern are engraved in an insulating layer for fabricating a wiring and a wiring connection part having a damascene structure, and then forms a barrier layer so as to sufficiently fill the holes and trenches with a metal such as copper. A first conductive layer interposed therebetween is formed on the insulating layer, and the first conductive layer using the barrier layer on the insulating layer as the polishing stop layer is applied to the first conductive layer to remain only in the holes and trenches, and then the buffer layer and the insulating layer are again formed. By buffing CMP to remove the surface of the insulating layer by a predetermined thickness, and then exposing the second conductive layer to the remaining first conductive layer surface and the insulating layer by physical vapor deposition (PVD). After that, the second conductive layer is subjected to the second CMP to expose the surface of the insulating layer, thereby completing the wiring having the convex shape of the upper surface. The thickness of the metal wiring insulation layer is formed in consideration of the thickness removed by the buffing CMP.

Therefore, unlike the prior art, in the present invention, since the upper surface of the wiring of the damascene structure is manufactured in a convex form, the resistance of the wiring is reduced, and at the same time, electromigration is prevented, and copper is reinforced, so that the metal wiring and the insulating layer are interposed. It is possible to reduce the capacitance change of and to uniformly control the thickness of the entire insulating layer by additional polishing of the insulating layer by buffing CMP, thereby contributing to the planarization and reducing various defects.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are process cross-sectional views illustrating a method for manufacturing wirings and wiring connectors of a semiconductor device according to the present invention.

Referring to FIG. 2A, the first insulating layer 21 is deposited on the semiconductor substrate 20 made of silicon by an oxide film or the like by chemical vapor deposition (hereinafter, referred to as CVD).

Next, in order to use the etch stop layer on the first insulating layer 21, the second insulating layer 22 is formed thin with an insulating material having a large etching selectivity with the first insulating layer. In this case, the second insulating layer 22 may be formed by depositing a nitride film by CVD.

The third insulating layer 23 is deposited on the second insulating layer 22 by an inter-metal dielectric 23 using an oxide film or the like. In this case, the third insulating layer 23 may be formed by combining tetra ethyl ortho silicate (TEOS) and spin on glass (SOG), and the main component thereof is SiO ₂ , and the formation thickness is an amount removed by buffing CMP. In consideration of this, it is formed to ensure a stable third insulating layer (23).

In the above description, the substrate 20 may be a semiconductor substrate having an impurity diffusion region (not shown) or a lower wiring.

In addition, contact portions H2 to via holes H2 and upper wirings which expose the conductive region of the substrate by patterning predetermined portions of the third, second and first insulating layers 23, 22, and 21 by a photolithography method. The pattern forms a recessed trench T2. That is, in a subsequent process, a plug for connecting conductive regions such as upper wiring and lower wiring is formed in the via hole H2, and upper wiring is simultaneously formed in the trench T2.

In this case, when the contact hole and the trench are patterned at the same time, the method may be performed as follows.

First, the first hole defining the via hole forming portion is formed by removing the third and second insulating layers 23 and 22 to a predetermined depth.

In addition, an etching mask in which the upper wiring trench pattern is defined is formed on the third insulating layer 23 on the portion including the first hole, and then the third insulating layer 23 is removed by dry etching using the etching mask. To form a trench. Therefore, when the trench is formed for etching, the first insulating layer 21 under the first hole is simultaneously etched to simultaneously form the via hole H2 having an extended upper portion with the trench T2. At this time, if the thicknesses of the third insulating layer and the first insulating layer are properly determined and formed, the formation of the second insulating layer, which is an etch stop layer, may be omitted.

Referring to FIG. 2B, the barrier layer 24 is contacted with a physical vapor deposition (PVD) or ionized metal plasma (IMP) to contact the substrate 20 exposed through trenches and via holes on the remaining third insulating layer 23. Form by law. In this case, the barrier layer 24 may be formed by depositing Ti, TiN, Ta, TaN, or the like, and may have a stacked structure thereof.

The conductive layer 25 is formed on the barrier layer 24 to form the upper wiring. In this case, when the conductive layer is formed using Cu, a copper seed layer (not shown) for forming a copper bulk layer on the surface of the barrier layer 24 is also deposited by PVD method. After the formation, the copper bulk layer 25 is formed to a thickness sufficiently filling the contact holes and the trenches by elecroplating using the copper seed layer. Thus, via holes were filled with a copper layer to simultaneously form interconnects and upper wiring forming layers.

Referring to FIG. 2C, a planarization process is performed on the formed copper bulk layer by the first CMP to expose the surface of the barrier layer 23 on the third insulating layer 23 to electrically expose the exposed conductive region of the substrate without a separate patterning process. A residual conductive layer 250 for upper wiring connected to each other is formed. At this time, the first CMP uses the surface of the barrier layer 23 as the polishing stop layer in order to prevent the third insulating layer from being excessively polished due to the difference in the polishing ratio between the copper and the oxide film.

However, even at this time, the upper surface of the conductive layer 250 remaining occurs in the dicing phenomenon, and the maximum thickness of the central portion of the conductive layer 250 reaches 'D2'.

Referring to FIG. 2D, buffing CMP is applied to the barrier layer and the third insulating layer to remove the barrier layer remaining on the third insulating layer, to expose and partially remove the surface of the third insulating layer. Accordingly, the remaining thickness of the third insulating layer 230 is reduced by 'd', and the upper surface of the conductive layer 251 is flattened again, and the entire third insulating layer 230 is flattened. At this time, the thickness of the third insulating layer 230 to be removed does not exceed 500Å maximum, the buffing CMP may be performed in the same metal CMP equipment as the first CMP equipment.

Referring to FIG. 2E, an additional conductive layer 26 is formed on the entire surface of the remaining conductive layer 251, the exposed barrier layer 240, and the third insulating layer 230. At this time, the additional conductive layer 26 forms copper by physical vapor deposition (PVD) to a thickness of about 1000 kPa.

Referring to FIG. 2F, a second CMP is performed on the additional conductive layer to leave the additional conductive layer 260 only on the conductive layer 251 and expose the surface of the third insulating layer 230 again. At this time, the polishing amount by the second CMP is about 1000 kPa.

Accordingly, even if the density of the upper wiring and the wiring pattern, which prevents the dimming phenomenon, is high, overall erosion is prevented and a flattened upper structure can be realized.

3 is a cross-sectional view of a wiring and a wiring connection part of a semiconductor device manufactured according to the present invention.

Referring to FIG. 3, a first insulating layer 21, a second insulating layer 22, which is an etch stop layer, and a third insulating layer are formed on a semiconductor substrate 20 made of silicon or the like on which elements such as transistors and capacitors are formed. 230 is formed in order, and a via hole or a contact hole is formed to remove predetermined portions of the first insulating layer and the second insulating layer to expose the surface of the predetermined portion of the substrate 20, and extends to the via hole. A trench for a wiring pattern formed by removing a predetermined portion of the third insulating layer is formed. In this case, the second insulating layer may be omitted.

The via hole and the trench are filled with a conductive layer 251 made of copper, and a diffusion barrier layer 240 is disposed between the conductive layer 251 and the inner surface of the hole and the trench.

The additional conductive layer 251 is thinly formed on the upper surface of the conductive layer 251, and the additional conductive layer 251 slightly protrudes from the surface of the third insulating layer 230.

The upper surface of the third conductive layer 230 is uniformly planarized as a whole, and a cross-sectional view of the entire damascene structure in which the respective wirings are combined is shown.

Therefore, the present invention manufactures the upper surface of the damascene structure in a convex form, thereby reducing the resistance of the wiring and at the same time preventing electromigration and reinforcing copper, thereby reducing the capacitance change between the metal wiring and the insulating layer. In addition, by further polishing the insulating layer by buffing CMP, the thickness of the entire insulating layer is uniformly controlled, thereby contributing to flattening and reducing various defects.

Claims (10)

An insulating layer formed on the semiconductor substrate, A hole having a lower portion of the insulating layer removed to expose a predetermined portion of the substrate and a trench extending from the hole to partially remove the upper portion of the insulating layer to have a predetermined wiring pattern; A barrier layer in contact with the exposed substrate and formed in the interior surfaces of the holes and trenches, A first conductive layer in contact with the barrier layer and completely filling the holes and trenches; And a second conductive layer formed only on the upper surface of the first conductive layer so as to partially protrude from the surface of the insulating layer. The method according to claim 1, And wherein the semiconductor substrate has an impurity diffusion region or a lower wiring formed in the predetermined portion. The method according to claim 1, And the first conductive layer is a copper layer formed by a plating method, and the second conductive layer is formed of a copper layer formed by physical vapor deposition (PVD). The wiring and wiring connection part of a semiconductor device according to claim 1, wherein the upper profile of the second conductive layer has a flat or convex shape. Forming a wiring insulation layer on the semiconductor substrate; Partially removing a lower portion of the insulating layer to expose a predetermined portion of the substrate, and extending from the hole to partially remove an upper portion of the insulating layer to form a trench having a predetermined wiring pattern; Forming a barrier layer in contact with the exposed substrate and in the inner surfaces of the holes and trenches; Forming a first conductive layer on the insulating layer in contact with the barrier layer and completely filling the holes and trenches; Subjecting the first conductive layer to a first chemical mechanical polishing using the barrier layer on the insulating layer as a polishing stop layer to leave the first conductive layer only inside the hole and the trench; Performing a buffing chemical mechanical polishing on the substrate to remove portions of the exposed barrier layer and the insulating layer and remove portions of the upper surface of the first conductive layer; Forming a second conductive layer on the entire surface of the substrate upper structure of the buffing chemical mechanical polishing by physical vapor deposition; Manufacturing a wiring and wiring connection part of a semiconductor device, comprising performing a second chemical mechanical polishing on the second conductive layer to expose an upper surface of the insulating layer and leaving the second conductive layer only on an upper surface of the first conductive layer. Way. The method according to claim 5, And the first conductive layer is formed of copper formed by plating, and the second conductive layer is formed of copper formed by physical vapor deposition. The method according to claim 5, And the second conductive layer is formed within 1000 mW. The method according to claim 5, And a thickness of the insulating layer removed by the buffing chemical mechanical polishing is at most 500 kW or less. The method according to claim 5, The predetermined portion of the exposed substrate further comprises forming a lower wiring on the upper portion of the semiconductor substrate or forming an impurity diffusion region on the predetermined portion of the semiconductor substrate. . The method according to claim 5, And the first chemical mechanical polishing and the buffing chemical mechanical polishing are performed on the same equipment.