KR20010004999A - Method of forming a inter-layer insulating film in a semiconductor device - Google Patents
Method of forming a inter-layer insulating film in a semiconductor device Download PDFInfo
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- KR20010004999A KR20010004999A KR1019990025778A KR19990025778A KR20010004999A KR 20010004999 A KR20010004999 A KR 20010004999A KR 1019990025778 A KR1019990025778 A KR 1019990025778A KR 19990025778 A KR19990025778 A KR 19990025778A KR 20010004999 A KR20010004999 A KR 20010004999A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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Abstract
Description
본 발명은 반도체 소자의 층간 절연막 형성 방법에 관한 것으로, 특히 1차 스핀 온 글라스막 도포 공정으로 제 1 절연막의 오버 행에 의하여 발생 가능한 보이드(void) 등과 같은 결함을 제거할 수 있어 보이드로 인한 소자의 전기적 특성 저하를 방지할 수 있고, 2차 스핀 온 글라스막 도포 공정으로 층간 절연막의 평탄화를 높일 수 있어 후속 공정을 용이하게 할 수 있는 반도체 소자의 층간 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device. In particular, the first spin-on glass film coating process eliminates defects such as voids caused by overhanging of the first insulating film, and is thus caused by voids. The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, which can prevent a decrease in electrical properties, and can increase the planarization of the interlayer insulating film by a second spin-on glass film coating process, thereby facilitating subsequent processes.
일반적으로, 반도체 소자의 제조 공정에서, 층간 절연막은 소자와 소자 또는 도전층과 도전층과의 전기적인 절연 및 평탄화를 목적으로 사용되며, 또한 외부의 환경으로 부터 소자를 보호하기 위한 보호막으로도 사용된다. 그런데, 반도체 소자의 고집적화에 따른 소자의 크기 감소로 인하여 배선간의 간격이 미세해지고 골이 깊어지기 때문에 기존의 플라즈마 증가형 화학기상증착법(PE-CVD)에 의하여 층간 절연막을 형성할 경우, 요구되는 갭 필링 특성 및 평탄화 특성을 얻을 수 없기 때문에 우수한 갭 필링(gap filling) 및 평탄화 특성을 나타내는 SOG막을 포함하는 층간 절연막 구조가 사용되고 있다.In general, in the manufacturing process of a semiconductor device, the interlayer insulating film is used for the purpose of electrical insulation and planarization between the device and the device or the conductive layer and the conductive layer, and also as a protective film to protect the device from the external environment. do. However, the gap between wirings becomes deeper and deeper due to the decrease in the size of the device due to the higher integration of semiconductor devices. Therefore, the gap required when forming an interlayer insulating film by conventional plasma enhanced chemical vapor deposition (PE-CVD) is required. Since the filling and flattening properties cannot be obtained, an interlayer insulating film structure including an SOG film exhibiting excellent gap filling and flattening properties is used.
도 1a 내지 도 1c는 종래 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a method of forming an interlayer insulating film of a conventional semiconductor device.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11)상에 다수의 금속 배선(12)을 형성한다. 다수의 금속 배선(12)을 포함한 기판(11) 표면부를 따라 절연 특성이 우수한 제 1 절연막(13)을 형성한다.Referring to FIG. 1A, a plurality of metal wires 12 are formed on a substrate 11 on which various elements for forming a semiconductor device are formed. A first insulating film 13 having excellent insulating properties is formed along the surface portion of the substrate 11 including the plurality of metal wires 12.
상기에서, 제 1 절연막(13)은 주로 SiON 등을 플라즈마 증가형 화학기상증착법으로 1000 내지 3000Å의 두께로 증착하여 형성하는데, 증착 특성상 금속 배선(12)의 모서리 부분에서 오버 행(13a)이 발생하게 된다. 이 오버 행(13a)은 반도체 소자가 고집적화 되어 감에 따라 이웃하는 오버 행(13a) 부분과 더욱 근접하게 된다.In the above description, the first insulating layer 13 is formed by depositing SiON or the like at a thickness of 1000 to 3000 kPa by a plasma enhanced chemical vapor deposition method. An overhang 13a occurs at a corner of the metal wiring 12 due to the deposition characteristics. Done. This overhang 13a is closer to the neighboring overhang 13a as the semiconductor elements become more integrated.
도 1b를 참조하면, 다수의 금속 배선(12)간을 채우면서 표면을 평탄화하기 위한 목적으로 제 1 절연막(13)상에 스핀 온 글라스막(14)을 형성한다.Referring to FIG. 1B, the spin-on glass film 14 is formed on the first insulating film 13 for the purpose of planarizing the surface while filling the plurality of metal wires 12.
상기에서, 스핀 온 글라스막(14)의 특성상 갭 필링 특성 및 평탄화 특성이 우수하지만, 제 1 절연막(13)의 오버 행(13a)이 심해지거나 금속 배선(12)간의 간격이 더욱 협소해 질 경우 금속 배선(12)간의 갭 부분에 보이드(10)가 발생된다.In the above, although the gap filling property and the planarization property are excellent due to the characteristics of the spin-on glass film 14, the overhang 13a of the first insulating film 13 becomes deeper or the gap between the metal wires 12 becomes smaller. The void 10 is generated in the gap portion between the metal wires 12.
도 1c를 참조하면, 스핀 온 글라스막(14)상에 제 2 절연막(15)을 형성하여 층간 절연막 형성을 완료한다.Referring to FIG. 1C, the second insulating film 15 is formed on the spin on glass film 14 to complete the formation of the interlayer insulating film.
상기한 종래 방법으로 층간 절연막을 형성할 경우 제 1 절연막의 오버 행에 의하여 보이드 등과 같은 결함이 발생되고, 이러한 보이드는 반도체 소자의 동작중 오동작을 유발시키는 등 신뢰성에 영향을 미치게 될 뿐만 아니라 수율을 감소시키는 문제가 있다.When the interlayer insulating film is formed by the conventional method described above, defects such as voids are generated due to overhang of the first insulating film, and such voids not only affect reliability, such as causing malfunction during operation of the semiconductor device, but also improve yield. There is a problem to reduce.
따라서, 본 발명은 1차 스핀 온 글라스막 도포 공정으로 제 1 절연막의 오버 행에 의하여 발생 가능한 보이드 등과 같은 결함을 제거할 수 있어 보이드로 인한 소자의 전기적 특성 저하를 방지할 수 있고, 2차 스핀 온 글라스막 도포 공정으로 층간 절연막의 평탄화를 높일 수 있어 후속 공정을 용이하게 할 수 있는 반도체 소자의 층간 절연막 형성 방법을 제공함에 그 목적이 있다.Therefore, the present invention can eliminate defects such as voids caused by overhang of the first insulating film by the first spin-on glass film coating process, thereby preventing deterioration of the electrical characteristics of the device due to voids, and secondary spin. It is an object of the present invention to provide a method for forming an interlayer insulating film of a semiconductor device, which can increase the planarization of the interlayer insulating film by an on glass film applying process, thereby facilitating subsequent processes.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 층간 절연막 형성 방법은 기판상에 다수의 금속 배선을 형성하고, 상기 다수의 금속 배선을 포함한 상기 기판상에 제 1 절연막을 형성하는 단계; 상기 제 1 절연막상에 제 1 스핀 온 글라스막을 형성하여 상기 다수의 금속 배선 사이의 갭을 매립하는 단계; 상기 제 1 스핀 온 글라스막상에 제 2 절연막을 형성하는 단계; 제 2 절연막상에 제 2 스핀 온 글라스막을 형성하여 표면 평탄화를 이루는 단계; 및 제 2 스핀 온 글라스막상에 제 3 절연막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The interlayer insulating film forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of forming a plurality of metal wiring on the substrate, and forming a first insulating film on the substrate including the plurality of metal wiring; Filling a gap between the plurality of metal wires by forming a first spin on glass film on the first insulating film; Forming a second insulating film on the first spin on glass film; Forming a second spin on glass film on the second insulating film to planarize the surface; And forming a third insulating film on the second spin on glass film.
도 1a 내지 도 1c는 종래 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming an interlayer insulating film of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of devices for explaining a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11, 21: 기판 12, 22: 금속 배선11, 21: substrate 12, 22: metal wiring
13, 23: 제 1 절연막 13a, 23a: 오버 행13, 23: 1st insulating film 13a, 23a: over row
14: 스핀 온 글라스막 24: 제 1 스핀 온 글라스막14: spin on glass film 24: first spin on glass film
15, 25: 제 2 절연막 10: 보이드15, 25: second insulating film 10: void
26: 제 2 스핀 온 글라스막 27: 제 3 절연막26: second spin on glass film 27: third insulating film
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도이다.2A through 2D are cross-sectional views of devices for describing a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(21)상에 다수의 금속 배선(22)을 형성한다. 다수의 금속 배선(22)을 포함한 기판(21) 표면부를 따라 절연 특성이 우수한 제 1 절연막(23)을 형성한다.Referring to FIG. 2A, a plurality of metal wires 22 are formed on a substrate 21 on which various elements for forming a semiconductor device are formed. A first insulating film 23 having excellent insulating properties is formed along the surface portion of the substrate 21 including the plurality of metal wires 22.
상기에서, 제 1 절연막(23)은 주로 SiON 등을 플라즈마 증가형 화학기상증착법으로 1000 내지 3000Å의 두께로 증착하여 형성하는데, 증착 특성상 금속 배선(22)의 모서리 부분에서 오버 행(23a)이 발생하게 된다. 이 오버 행(23a)은 반도체 소자가 고집적화 되어 감에 따라 이웃하는 오버 행(23a) 부분과 더욱 근접하게 된다.In the above, the first insulating film 23 is mainly formed by depositing SiON and the like at a thickness of 1000 to 3000 kPa by a plasma enhanced chemical vapor deposition method. An overhang 23a occurs at a corner of the metal wire 22 due to the deposition characteristics. Done. This overhang 23a is closer to the neighboring overhang 23a as the semiconductor elements become more integrated.
도 2b를 참조하면, 제 1 절연막(23)의 오버 행(23a)으로 인한 토폴러지(topology)를 완화시키기 위해 제 1 스핀 온 글라스막(24)을 얇게 형성한다.Referring to FIG. 2B, the first spin-on glass film 24 is thinly formed to alleviate the topology caused by the overrow 23a of the first insulating film 23.
상기에서, 제 1 스핀 온 글라스막(24)은 CxH2x+1의 결합 구조를 함유하고 있는 유기 실리콘계 스핀 온 글라스 물질을 사용하거나, 무기계열의 스핀 온 글라스 물질을 사용하며, 도포 타겟을 100 내지 3000Å으로 하여 도포한 후 300 내지 500℃의 온도에서 경화시켜, 오버 행(23a)의 도폴러지를 완화시키는 동시에 갭 부분을 어느 정도 채워주도록 형성한다. 제 1 스핀 온 글라스막(24)을 형성한 후, 소자의 제조 특성에 따라 전면 혹은 부분적으로 에치 백(etch back) 공정을 실시할 수 있다.In the above description, the first spin-on glass film 24 uses an organic silicon-based spin-on glass material containing a bonding structure of C × H 2x + 1 , or an inorganic spin-on glass material. After coating to 100-3000 Pa, it hardens at the temperature of 300-500 degreeC, and forms to fill the gap part to some extent, while alleviating the dopedness of the overhang 23a. After the first spin-on glass film 24 is formed, an etch back process may be performed on the entire surface or partially according to the manufacturing characteristics of the device.
도 2c를 참조하면, 제 1 스핀 온 글라스막(24)상에 제 2 절연막(25)을 형성하고, 제 2 절연막(25)상에 평탄화를 위해 제 2 스핀 온 글라스막(26)을 형성한다.Referring to FIG. 2C, a second insulating film 25 is formed on the first spin on glass film 24, and a second spin on glass film 26 is formed on the second insulating film 25 for planarization. .
상기에서, 제 2 절연막(25)은 제 1 절연막(23)과 유사하거나 동일한 물질로 형성한다. 제 2 스핀 온 글라스막(26)은 제 1 스핀 온 글라스막(24)과 유사하거나 동일한 물질로 형성한다.In the above, the second insulating film 25 is formed of a material similar to or the same as the first insulating film 23. The second spin on glass film 26 is formed of a material that is similar to or the same as the first spin on glass film 24.
도 2d를 참조하면, 제 2 스핀 온 글라스막(26)상에 제 3 절연막(27)을 형성하여 층간 절연막 형성을 완료한다.Referring to FIG. 2D, the third insulating film 27 is formed on the second spin on glass film 26 to complete the formation of the interlayer insulating film.
본 발명의 실시예에 따라 제 1 절연막/제 1 스핀 온 글라스막/제 2 절연막/제 2 스핀 온 글라스막/제 2 절연막이 적층된 층간 절연막을 형성한 후에 반도체 소자의 제조 공정상의 목적에 따라 금속 배선 상부의 제 1 절연막의 표면이 노출되는 시점까지 전면 식각 또는 연마 공정을 실시할 수도 있다.After forming the interlayer insulating film in which the first insulating film / the first spin on glass film / the second insulating film / the second spin on glass film / the second insulating film is laminated according to an embodiment of the present invention, according to the purpose of the manufacturing process of the semiconductor device The entire surface etching or polishing process may be performed until the surface of the first insulating film over the metal wiring is exposed.
상술한 바와 같이, 본 발명은 1차 스핀 온 글라스막 도포 공정으로 제 1 절연막의 오버 행에 의하여 발생 가능한 보이드 등과 같은 결함을 제거할 수 있어 보이드로 인한 소자의 전기적 특성 저하를 방지할 수 있고, 2차 스핀 온 글라스막 도포 공정으로 층간 절연막의 평탄화를 높일 수 있어 후속 공정을 용이하게 할 수 있어, 소자의 신뢰도 및 수율을 향상시킬 수 있다.As described above, the present invention can remove defects such as voids, etc., which may occur due to the overhang of the first insulating film by the first spin-on glass film applying process, thereby preventing deterioration of the electrical characteristics of the device due to voids, The second spin-on glass film coating process can increase the planarization of the interlayer insulating film, thereby facilitating subsequent processes, thereby improving the reliability and yield of the device.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990025778A KR20010004999A (en) | 1999-06-30 | 1999-06-30 | Method of forming a inter-layer insulating film in a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101034407B1 (en) * | 2009-02-23 | 2011-05-12 | 주식회사 하이닉스반도체 | Nonvolatile memory device and manufacturing method of the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101034407B1 (en) * | 2009-02-23 | 2011-05-12 | 주식회사 하이닉스반도체 | Nonvolatile memory device and manufacturing method of the same |
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