KR100325616B1 - a method manufacturing a semiconductor device - Google Patents
a method manufacturing a semiconductor device Download PDFInfo
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- KR100325616B1 KR100325616B1 KR1019990067698A KR19990067698A KR100325616B1 KR 100325616 B1 KR100325616 B1 KR 100325616B1 KR 1019990067698 A KR1019990067698 A KR 1019990067698A KR 19990067698 A KR19990067698 A KR 19990067698A KR 100325616 B1 KR100325616 B1 KR 100325616B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000000034 method Methods 0.000 title abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000010936 titanium Substances 0.000 claims abstract description 10
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 10
- 238000011065 in-situ storage Methods 0.000 claims abstract description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 102
- 238000004544 sputter deposition Methods 0.000 claims description 10
- 229910052736 halogen Inorganic materials 0.000 claims description 3
- 150000002367 halogens Chemical class 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 abstract description 8
- 239000010937 tungsten Substances 0.000 abstract description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 description 8
- 239000010410 layer Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
절연막 위에 티타늄막과 질화 티타늄막, 알루미늄막, 질화 티타늄막으로 이루어진 금속 배선을 형성하고, 그 위에 SOG막을 형성하고, SOG막 위에 TEOS 산화막으로 이루어진 층간 절연막을 증착하고 평탄화한다. 이어, 층간 절연막과 SOG막, 질화 티타늄막을 식각하여 알루미늄막을 드러내는 접촉 구멍을 형성한다. 이어, 배리어막을 형성하는 스퍼터 시스템을 이용하여 인시튜로 SOG막의 내부에 유입되어 있는 수분을 제거한 다음, 접촉 구멍에 티타늄막 및 질화 티타늄막으로 이루어진 배리어막을 형성한다. 이어, 텅스텐을 적층하여 접촉 구멍을 메운 다음, 층간 절연막이 드러날 때까지 평탄화 공정을 실시한다. 본 발명에서는 배리어막을 형성하는 단계에서 인시튜로 SOG막의 수분을 제거함으로써 제조 설비를 추가하지 않고 접촉 구멍에 텅스텐막을 충분히 채울 수 있어 접촉 구멍의 접촉 저항을 최소화하여 소자의 특성을 향상시킬 수 있다.A metal wiring consisting of a titanium film, a titanium nitride film, an aluminum film and a titanium nitride film is formed on the insulating film, an SOG film is formed thereon, and an interlayer insulating film made of a TEOS oxide film is deposited and planarized on the SOG film. Subsequently, the interlayer insulating film, the SOG film, and the titanium nitride film are etched to form a contact hole that exposes the aluminum film. Subsequently, the water flowing into the SOG film is removed in-situ using a sputter system for forming the barrier film, and then a barrier film made of a titanium film and a titanium nitride film is formed in the contact hole. Next, tungsten is laminated to fill the contact holes, and then a planarization process is performed until the interlayer insulating film is exposed. In the present invention, by removing the moisture of the SOG film in-situ at the step of forming the barrier film, the tungsten film can be sufficiently filled in the contact hole without adding manufacturing equipment, thereby minimizing the contact resistance of the contact hole, thereby improving the characteristics of the device.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 층간에 절연막을 사이에 두고 다층 구조로 이루어진 배선을 가지는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having wiring having a multilayer structure with an insulating film therebetween.
일반적으로 반도체 소자에는 n형 또는 p형의 기판 위에 채널, 소스, 드레인 영역 등의 불순물이 도핑되어 있는 활성(active) 영역이 형성되어 있으며, 그 위에는 각각의 영역 상부에 접촉 구멍(contact)을 가지는 절연막이 형성되어 있으며 절연막 위에는 접촉 구멍을 통하여 각각의 영역과 연결되는 배선이 형성되어 있다.In general, a semiconductor device is formed with an active region doped with impurities such as a channel, a source, and a drain region on an n-type or p-type substrate, and a contact hole is formed over each region. An insulating film is formed, and wirings connected to the respective regions are formed on the insulating film through contact holes.
여기서, 반도체 소자가 점점 집적화될수록 반도체 소자의 면적이 줄어들기 때문에 배선을 무한정 길게 형성하는 데는 한계가 있다. 따라서, 이를 해결하기위해서는 배선 층간에 절연막을 형성하고 절연막에 뚫린 접촉 구멍(via)을 통해 배선을 서로 연결하는 다층 배선을 형성하는 것이 효과적이다.Here, there is a limit to forming the wiring indefinitely because the area of the semiconductor element is reduced as the semiconductor element is gradually integrated. Therefore, in order to solve this problem, it is effective to form an insulating film between the wiring layers and to form a multilayer wiring that connects the wirings to each other through contact holes (vias) formed in the insulating film.
이러한 다층 배선의 구조에서는 절연막의 평탄도가 우수해야 한다. 이러한 절연막에는 액체 상태의 SOG(spin-on-glass)를 경화시킨 절연막과TEOS(tetraethoxysilane)를 이용한 층간 금속 절연막(intermetal dielectric)을 함께 사용하는데, 이때 SOG막은 배선간의 간극(gap)을 메워 평탄화시키는 역할을 한다.In such a multilayer wiring structure, the flatness of the insulating film should be excellent. The insulating film is a combination of an insulating film of liquid spin-on-glass (SOG) and an intermetal dielectric using tetraethoxysilane (TEOS), wherein the SOG film fills the gaps between the wirings and flattens them. Play a role.
그러면, 종래의 다층 배선을 갖는 반도체 소자에 제조 방법에 대하여 도 1a 내지 도 1e를 을 참조하여 상세히 설명한다.Next, a manufacturing method for a semiconductor device having a conventional multilayer wiring will be described in detail with reference to FIGS. 1A to 1E.
도 1a 내지 도 1e는 종래의 기술에 따른 반도체 소자의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art in the order of their processes.
먼저, 도 1a에서와 같이 절연막(10) 위에 알루미늄 등을 포함하는 금속막을 적층하고 패터닝하여 다수의 금속 배선(20)을 형성한다.First, as shown in FIG. 1A, a plurality of metal wires 20 are formed by stacking and patterning a metal film including aluminum on the insulating film 10.
이어, 도 1b에서와 같이 금속 배선(20)을 덮는 SOG막(30)을 도포한 후 열처리하여 경화시킨 다음, TEOS 산화막 따위의 층간 절연막(40)을 증착하고 평탄화 공정을 실시한다.Subsequently, as shown in FIG. 1B, the SOG film 30 covering the metal wiring 20 is applied and then thermally cured. Then, an interlayer insulating film 40 such as a TEOS oxide film is deposited and a planarization process is performed.
이어, 도 1c에서와 같이 사진 식각 공정을 통하여 층간 절연막(40)과 SOG막(30)을 식각하여 금속 배선(20)을 드러내는 접촉 구멍(41)을 형성한다. 이때, 금속 배선(20)의 상부가 식각될 수도 있다.Subsequently, as shown in FIG. 1C, the interlayer insulating film 40 and the SOG film 30 are etched through the photolithography process to form the contact holes 41 exposing the metal wires 20. In this case, an upper portion of the metal wire 20 may be etched.
이어, 도 1d에서와 같이 티타늄 및 질화 티타늄과 같은 도전 물질을 차례로적층하여 배리어막(50)을 형성하고, 이어, 텅스텐으로 이루어진 금속막(60)을 증착하여 접촉 구멍(41)을 채운다.Subsequently, as shown in FIG. 1D, conductive materials such as titanium and titanium nitride are sequentially stacked to form a barrier film 50. Then, a metal film 60 made of tungsten is deposited to fill the contact hole 41.
이어, 도 1e에서와 같이 층간 절연막(40)이 드러날 때까지 텅스텐 금속막(60)과 배리어막(50)을 평탄화한다.Next, as shown in FIG. 1E, the tungsten metal film 60 and the barrier film 50 are planarized until the interlayer insulating film 40 is exposed.
이러한 순서에 따른 제조 공정은 절연막(10)을 사이에 두고 층간의 금속 배선(20)을 연결할 때 반복적으로 이루어진다.The manufacturing process according to this order is repeatedly performed when connecting the metal wires 20 between the layers with the insulating film 10 therebetween.
그러나, 이러한 종래의 기술에 따른 반도체 장치의 제조 방법에서는, SOG막(30)에 흡수된 수분으로 인하여 접촉 구멍(41)의 내부에 텅스텐 금속막(60)이 완전히 채워지지 않아 소자의 특성을 저하시키는 문제점이 발생한다. 구체적으로, 접촉 구멍(41)을 형성한 후에 세정하는 단계에서 접촉 구멍(41)의 측벽을 통하여 노출되어 있는 SOG막(30)은 다량의 수분을 흡수하게 되는데, 400℃ 이상의 고온 공정으로 기체인 WF6과 질화티타늄을 포함하는 배리어막(50)의 반응을 통하여 금속막(60)을 형성할 때 증발하게 된다. 그러므로, 수분이 증발되는 부분에서는 WF6과 질화티타늄이 반응하지 않아 텅스텐이 적층되지 않게 되어 텅스텐이 채워지지 않은 빈 공간(V)이 형성된다. 이로 인하여, 접촉 구멍(41)에서의 접촉 저항을 크게 증가하여 소자의 특성을 저하시킨다.However, in the method of manufacturing a semiconductor device according to the related art, the tungsten metal film 60 is not completely filled in the contact hole 41 due to the moisture absorbed in the SOG film 30, thereby degrading the characteristics of the device. Problem occurs. Specifically, the SOG film 30 exposed through the sidewall of the contact hole 41 absorbs a large amount of moisture in the cleaning step after the contact hole 41 is formed. When the metal film 60 is formed through the reaction of the barrier film 50 including WF 6 and titanium nitride, the evaporation is performed. Therefore, in the part where moisture is evaporated, WF 6 and titanium nitride do not react and tungsten is not laminated, thereby forming an empty space (V) not filled with tungsten. For this reason, the contact resistance in the contact hole 41 is greatly increased, and the characteristic of an element is reduced.
본 발명이 이루고자 하는 기술적 과제는 접촉 저항을 최소화하여 소자의 특성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공하는 것이다.The technical problem to be achieved by the present invention is to provide a method of manufacturing a semiconductor device that can improve the characteristics of the device by minimizing contact resistance.
도 1a 내지 도 1e는 종래의 기술에 따른 반도체 소자의 제조 방법을 그 공정 순서에 따라 도시한 단면도이고,1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art in the order of their processes;
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention according to a process sequence thereof.
이러한 과제를 달성하기 위하여 본 발명에서는 배리어막을 형성하는 공정에서 스퍼터 시스템을 이용하여 SOG막에 잔류하는 수분을 증발시키고 배리어막을 적층한다.In order to achieve this problem, the present invention evaporates the moisture remaining in the SOG film by using a sputtering system in the process of forming the barrier film and stacks the barrier film.
우선, 제1 절연막 위에 금속 배선을 형성하고 금속 배선을 덮는 위에 SOG막을 형성한다. 이어, SOG막 위에 제2 절연막을 형성하고, 제2 절연막 및 SOG막을 식각하여 금속 배선을 드러내는 접촉 구멍을 형성한다. 이어, 접촉 구멍에 배리어막을 형성하고, 접촉 구멍을 매립용 금속막으로 채운다. 이때, 배리어막은 스퍼터링을 통하여 박막을 형성하는 스퍼터 시스템을 이용하여 형성하며, 배리어막을 적층하기 전에 스퍼터 시스템을 이용하여 인시튜(in-situ)로 SOG막의 내부에 유입되어 있는 수분을 제거한다.First, a metal wiring is formed over the first insulating film, and an SOG film is formed over the metal wiring. Subsequently, a second insulating film is formed on the SOG film, and the second insulating film and the SOG film are etched to form contact holes for exposing the metal wiring. Next, a barrier film is formed in the contact hole, and the contact hole is filled with a buried metal film. In this case, the barrier film is formed by using a sputtering system for forming a thin film through sputtering, and before the barrier film is stacked, moisture introduced into the SOG film is removed in-situ using the sputtering system.
여기서, 금속 배선은 티타늄, 질화 티타늄 및 알루미늄을 포함하는 도전막으로 형성하는 것이 바람직하며, 배리어막은 티타늄 및 질화 티타늄으로 형성하는 것이 좋다.Here, the metal wiring is preferably formed of a conductive film containing titanium, titanium nitride and aluminum, and the barrier film is preferably formed of titanium and titanium nitride.
스퍼터 시스템은 할로겐 램프를 포함하는 발열 장치를 가지는 디개스(degas)용 챔버를 가지고 있으며, SOG막 내부의 수분은 디개스용 챔버를 이용하여 제거할 수 있다. 이때 수분 제거하기 위해서는 디개스용 챔버의 온도는 250~300℃ 범위에서 설정하는 것이 바람직하다.The sputter system has a degas chamber having a heating device including a halogen lamp, and moisture inside the SOG film can be removed using the degas chamber. At this time, in order to remove the water, the temperature of the degas chamber is preferably set in the range of 250 ~ 300 ℃.
그러면, 첨부한 도면을 참조하여 본 발명의 실시예에 따른 반도체 소자의 제조 방법에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있을 정도로 상세히 설명한다.Next, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same.
도 2a 내지 도 2f를 참조하여 본 발명의 실시예에 따른 반도체 소자의 제조 방법에 대하여 상세히 설명한다. 도 2a 내지 도 2f에서는 다층 금속 배선의 구조에서 반복되는 하나의 층만을 예를 들어 도시한 것이다.A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2F. 2A to 2F show only one layer which is repeated in the structure of the multi-layer metal wiring, for example.
먼저, 도 2a에서와 같이 절연막(10) 위에 저저항을 가지는 알루미늄 등을 포함하는 금속막을 적층하고 패터닝하여 다수의 금속 배선(20)을 형성한다. 이때, 도면으로 나타나지 않았지만, 절연막(10)에는 접촉 구멍이 형성되어 있으며, 금속 배선(20)은 절연막(10) 하부에 형성되어 있는 다른 금속 배선과 접촉 구멍을 연결되어 있다. 여기서, 금속 배선(20)은 알루미늄막(23)을 도전막을 포함하며, 알루미늄막(23)의 하부에는 티타늄막(21)과 질화 티타늄막(22)을 추가로 형성하는 것이 바람직하며, 알루미늄막(23)의 상부에도 질화 티타늄막(24)을 추가로 형성하는 것이 바람직하다, 여기서, 하부의 티타늄막(21) 및 질화 티타늄막(22)은 절연막(10)과 알루미늄막(23)의 접촉 특성을 좋게 하기 위해 형성하는 것이고, 상부의 질화 티타늄막(24)은 사진 식각 공정에서의 노광 공정에서 알루미늄막(23)으로부터 반사되는 빛을 줄이기 위한 것이며, 이들은 절연막(10)으로부터 알루미늄막(23)으로 유입되는 불순물을 방지하는 역할도 가진다.First, as shown in FIG. 2A, a plurality of metal wires 20 are formed by stacking and patterning a metal film including aluminum having low resistance on the insulating film 10. At this time, although not shown in the drawing, a contact hole is formed in the insulating film 10, and the metal wire 20 connects the contact hole with another metal wire formed under the insulating film 10. Here, the metal wire 20 may include an aluminum film 23 as a conductive film, and a titanium film 21 and a titanium nitride film 22 may be further formed below the aluminum film 23. It is preferable to further form a titanium nitride film 24 on the upper part of the upper part 23, wherein the lower titanium film 21 and the titanium nitride film 22 are in contact with the insulating film 10 and the aluminum film 23. It is formed to improve the characteristics, the upper titanium nitride film 24 is to reduce the light reflected from the aluminum film 23 in the exposure step in the photolithography process, these are the aluminum film 23 from the insulating film 10 It also has a role of preventing impurities from entering.
이어, 도 2b에서와 같이 금속 배선(20)을 덮는 SOG막(30)을 도포한 후 열처리하여 경화시킨 다음, TEOS 산화막 따위의 층간 절연막(40)을 증착하고 평탄화 공정을 실시한다. 이때, SOG막(30)과 금속 배선(20) 사이의 반응을 억제하기 위하여 SOG막(30)의 하부에 TEOS 산화막 따위로 이루어진 절연막을 추가로 형성할 수 있다. 이때, SOG막(30)을 이용하는 이유는, 경화시키기 전의 SOG막(30)은 유동성을 가지므로 배선(20)의 간격이 0.3 또는 0.5μm 이하인 경우에도 다수의 배선(20) 사이에 채워지게 되어 동일한 층으로 형성되는 다수의 배선(20)을 서로 절연시킬 수 있기 때문이다.Subsequently, as shown in FIG. 2B, the SOG film 30 covering the metal wiring 20 is coated and then cured by heat treatment. Then, an interlayer insulating film 40 such as a TEOS oxide film is deposited and a planarization process is performed. At this time, in order to suppress the reaction between the SOG film 30 and the metal wiring 20, an insulating film made of a TEOS oxide film or the like may be further formed below the SOG film 30. At this time, the reason why the SOG film 30 is used is that the SOG film 30 before curing is fluidized, so that even if the distance of the wiring 20 is 0.3 or 0.5 μm or less, it is filled between the plurality of wirings 20. This is because a plurality of wirings 20 formed of the same layer can be insulated from each other.
이어, 도 2c에서와 같이 층간 절연막(40)과 SOG막(30), 상부의 질화 티타늄막(24)을 식각하여 알루미늄막(23)을 드러내는 접촉 구멍(41)을 형성한 후, 식각 공정에서의 잔유물을 제거하기 위해 세정 공정을 실시한다. 이때 도면에서와 같이 알루미늄막(23)의 상부가 식각될 수도 있다. 이때, 접촉 구멍(41)의 폭은 0.3-0.5μm 정도로 형성하는 것이 바람직하다.Subsequently, as shown in FIG. 2C, the interlayer insulating film 40, the SOG film 30, and the upper titanium nitride film 24 are etched to form contact holes 41 exposing the aluminum film 23. A washing process is performed to remove the residues. In this case, as shown in the figure, the upper portion of the aluminum film 23 may be etched. At this time, it is preferable to form the width of the contact hole 41 about 0.3-0.5 micrometer.
이어, 도 2d에서 보는 바와 같이, 열처리 공정을 통하여 세정 공정에서 SOG막(30) 내부에 유입되어 있는 수분을 증발시킨다. 이때, 열처리 공정은 별도의 공정 및 장비를 추가하지 않고, 이후의 배리어막을 적층하는 공정 설비인 스퍼터 시스템(sputter system)을 이용한다. 이러한 스퍼터 시스템은 도전 물질로 이루어진 박막을 스퍼터링(sputtering)을 통하여 형성하는 장비로써, 할로겐 램프 따위의 발열 장치를 가지는 디개스용 챔버(degas chamber)를 가지고 있으며, 박막 형성 공정은 도전 물질을 적층하기 전에 100~200℃ 범위에서 웨이퍼 표면의 수분을 포함하는 불순물을 디개스하는 공정을 포함하고 있다. 이때, 디개스 공정의 온도를 250~300℃ 정도로 설정하고 디개스하는 공정을 실시하면, 웨이퍼 표면의 불순물을 제거하는 동시에 인시튜(in-situ)로 접촉 구멍(41)을 통하여 SOG막(30)의 내부에 유입되어 있는 수분을 제거할 수 있다. 250℃ 이하의 범위에서 열처리 공정을 실시하는경우에는 수분 증발이 완전히 이루어지지 않아 종래의 문제점을 유발할 수 있으며, 300℃ 이상의 범위에서 열처리 공정을 실시하는 경우에는 접촉 구멍(41)을 통하여 노출되어 있는 알루미늄막(23)이 손상되어 소자가 동작하지 않는 문제점이 발생할 수 있다.Next, as shown in FIG. 2D, moisture flowing into the SOG film 30 in the cleaning process is evaporated through the heat treatment process. In this case, the heat treatment process uses a sputter system, which is a process facility for laminating a barrier layer thereafter without adding a separate process and equipment. The sputtering system is a device for forming a thin film made of a conductive material through sputtering, and has a degas chamber having a heating device such as a halogen lamp. Previously, the step of degassing impurities including moisture on the surface of the wafer in the range of 100 to 200 ° C is included. At this time, when the temperature of the degas process is set to about 250 to 300 ° C. and the degas process is performed, impurities on the surface of the wafer are removed, and the SOG film 30 is in-situ through the contact hole 41 in-situ. It can remove the water flowing into the inside of). When the heat treatment process is performed in the range of 250 ° C. or less, evaporation of moisture is not completely performed, which may cause a conventional problem. When the heat treatment process is performed in the range of 300 ° C. or more, the contact hole 41 is exposed. The aluminum film 23 may be damaged, which may cause a problem that the device may not operate.
이어, 도 2e에서와 같이 티타늄막(51) 및 질화 티타늄막(52)을 차례로 적층하여 배리어막(50)을 형성하고, 그 상부에 텅스텐을 포함하는 기체를 이용한 CVD 방법으로 매입용 금속막(60)을 증착하여 접촉 구멍(41)을 채운다.Next, as shown in FIG. 2E, the titanium film 51 and the titanium nitride film 52 are sequentially stacked to form a barrier film 50, and the metal film for embedding by a CVD method using a gas containing tungsten thereon is formed. 60 is deposited to fill the contact holes 41.
이어, 도 2f에서와 같이 층간 절연막(40)이 드러날 때까지 매입용 금속막(60)과 배리어막(50)을 평탄화한다.Next, as shown in FIG. 2F, the embedding metal film 60 and the barrier film 50 are planarized until the interlayer insulating film 40 is exposed.
이와 같은 본 발명의 실시예에서는 별도의 설비를 추가하지 않고 스퍼터 시스템을 이용하여 배리어막(50)을 적층하기 전에 열처리 공정을 실시하여 SOG막에 유입되어 있는 수분을 제거함으로써, 접촉 구멍에 매립용 금속을 충분히 채울 수 있다.In this embodiment of the present invention to remove the water flowing into the SOG film by performing a heat treatment process before laminating the barrier film 50 by using a sputter system without adding a separate equipment, for embedding in the contact hole The metal can be filled sufficiently.
따라서, 본 발명에서는 접촉 구멍에서의 접촉 저항을 최소화할 수 있어 소자의 특성을 향상시킬 수 있다.Therefore, in the present invention, the contact resistance at the contact hole can be minimized, thereby improving the characteristics of the device.
Claims (5)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030090869A (en) * | 2002-05-22 | 2003-12-01 | 동부전자 주식회사 | Method for treating with heat for stability of reflection-prevention layer in metalization process |
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|---|---|---|---|---|
| JPH0414833A (en) * | 1990-05-08 | 1992-01-20 | Matsushita Electron Corp | Semiconductor device |
| JPH053255A (en) * | 1991-06-24 | 1993-01-08 | Kawasaki Steel Corp | Method of forming multilayer metallic wiring later in semiconductor device |
| JPH065715A (en) * | 1992-06-18 | 1994-01-14 | Sony Corp | Formation of wiring layer |
| JPH0878528A (en) * | 1994-09-05 | 1996-03-22 | Sony Corp | Formation of wiring for semiconductor device |
| JPH0964037A (en) * | 1995-08-23 | 1997-03-07 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0414833A (en) * | 1990-05-08 | 1992-01-20 | Matsushita Electron Corp | Semiconductor device |
| JPH053255A (en) * | 1991-06-24 | 1993-01-08 | Kawasaki Steel Corp | Method of forming multilayer metallic wiring later in semiconductor device |
| JPH065715A (en) * | 1992-06-18 | 1994-01-14 | Sony Corp | Formation of wiring layer |
| JPH0878528A (en) * | 1994-09-05 | 1996-03-22 | Sony Corp | Formation of wiring for semiconductor device |
| JPH0964037A (en) * | 1995-08-23 | 1997-03-07 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030090869A (en) * | 2002-05-22 | 2003-12-01 | 동부전자 주식회사 | Method for treating with heat for stability of reflection-prevention layer in metalization process |
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