KR0172526B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR0172526B1 KR0172526B1 KR1019950065622A KR19950065622A KR0172526B1 KR 0172526 B1 KR0172526 B1 KR 0172526B1 KR 1019950065622 A KR1019950065622 A KR 1019950065622A KR 19950065622 A KR19950065622 A KR 19950065622A KR 0172526 B1 KR0172526 B1 KR 0172526B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Abstract
본 발명은 포토레지스트 패턴을 식각 마스크로하여 비아홀을 형성하고, 이온주입공정 또는 Ar 스퍼터링공정으로 비아홀 측벽에 경화막을 형성한 후, O2플라즈마 처리를 통해 포토레지스트 패턴 제거공정을 실시하므로, O2플라즈마 처리동안 비아홀에 노출된 SOG막이 경화막에 의해 식각되는 것이 방지된다.Since the present invention is carried out after forming the via hole with the photoresist pattern as an etch mask to form the ion implantation process or Ar sputtering process hardening on the via hole side wall film, O 2 to remove the photoresist pattern through the plasma treatment process, O 2 The SOG film exposed to the via hole during the plasma treatment is prevented from being etched by the cured film.
따라서, 본 발명은 비아홀부분으로 노출된 SOG막에 리세스가 생기는 것을 방지하므로 추후 금속배선 공정에서 알루미늄 층덮힘이 개선되고, 비아홀부분으로 노출된 SOG막의 표면에 경화막이 형성되어있어 추후 열공정에서 SOG막으로부터의 수분 배출이 억제되어 금속배선의 신뢰성을 향상시킬 수 있다.Therefore, the present invention prevents recesses in the SOG film exposed through the via hole, so that the aluminum layer covering is improved in the metallization process later, and a cured film is formed on the surface of the SOG film exposed through the via hole. Discharge of moisture from the SOG film can be suppressed to improve the reliability of the metal wiring.
Description
제1a 내지 1c도는 종래 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.
제2a 내지 2c도는 본 발명의 실시예에 의한 반도체 소자의 제조 방법을 설명하기 위해 도시한 소자의 단면도.2A through 2C are cross-sectional views of a device for explaining the method for manufacturing a semiconductor device according to the embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11 : 실리콘 기판 2,12 : 폴리-금속층간 절연막1,11 silicon substrate 2,12 poly-metal interlayer insulating film
3,13 : 하부 금속배선 4,14 : 제1절연막3,13: lower metal wiring 4,14: first insulating film
5,15 : SOG막 6,16 : 제2절연막5,15 SOG film 6,16 Second insulating film
7,17 : 포토레지스트 패턴 8,18 : 비아홀7,17 photoresist pattern 8,18 via hole
9,19 : 상부 금속배선 10 : 리세스9,19 upper metal wiring 10: recess
20 : 경화막20: cured film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다중 금속 배선 구조에서 금속층간 절연막의 평탄화막으로 사용되는 SOG막이 비아홀에서 리세스(recess)현상이 유발되는 것을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a method of manufacturing a semiconductor device capable of preventing a recess phenomenon from occurring in a via hole of an SOG film used as a planarization film of an intermetallic insulating film in a multi-metal wiring structure. It is about.
다중 금속배선 구조의 반도체 소자에서 하부 금속배선과 상부 금속 배선사이를 절연하기 위하여 금속층간 절연막이 형성된다. 금속층간 절연막은 2개 이상의 절연층을 적층하여 형성되는데, 표면 평탄화를 향상시키기 위하여 SOG막이 포함되도록 한다. SOG막은 표면 평탄화 특성이 우수한 반면에 친수성이 강한 관계로 내부에 수분이 다량 함유되어 있다. 따라서, SOG막의 수분이 하부 금속배선으로 확산되는 것을 막기 위하여 SOG막을 도포하기 전에 제1절연막을 형성하고, 상부 금속배선으로 확산되는 것을 방지하기 위하여 SOG막상에 제2절연막을 형성한다. 그런데, 포토레지스트 패턴을 식각 마스크로하여 비아홀을 형성한 후, 포토레지스트 패턴을 제거하는 공정동안 비아홀에 노출된 SOG막이 일부 식각되어 리세스가 형성된다. 이 SOG막의 리세스는 추후 금속배선 공정에서 알루미늄 층덮힘성(step-coverage)을 저하시키며, 심지어 금속배선을 단락시키는 경우도 발생시키므로 금속배선 신뢰성을 저하시키고 있다. 그러면 제1a 내지 1c도를 참조하여 종래의 문제점을 설명하기로 한다.In the semiconductor device having a multi-metal interconnection structure, an interlayer insulating film is formed to insulate between the lower metal interconnection and the upper metal interconnection. The intermetallic insulating film is formed by stacking two or more insulating layers, so that the SOG film is included to improve surface planarization. While the SOG film has excellent surface planarization characteristics, the SOG film contains a large amount of water due to its strong hydrophilicity. Therefore, in order to prevent the moisture of the SOG film from diffusing to the lower metal wiring, a first insulating film is formed before applying the SOG film, and a second insulating film is formed on the SOG film to prevent the diffusion of the SOG film into the upper metal wiring. However, after the via hole is formed using the photoresist pattern as an etching mask, the SOG film exposed to the via hole is partially etched during the process of removing the photoresist pattern to form a recess. The recess of the SOG film lowers the aluminum step-coverage in the metallization process later, and even shorts the metallization, thereby lowering the metallization reliability. Next, a conventional problem will be described with reference to FIGS. 1A to 1C.
제1a 내지 1c도는 종래 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.
제1a도를 참조하면, 폴리-금속 층간절연막(2)이 실리콘 기판(1)상에 형성되고, 폴리-금속층간절연막(2)상에는 금속배선 공정을 통해 다수의 하부 금속배선(3)이 형성된다. 다수의 하부 금속배선(3)을 포함한 층간절연막(2)상에 제1절연막(4), SOG막(5) 및 제2절연막(6)이 순차적으로 형성된다. 제2절연막(6)상에 포토레지스트 패턴(7)이 형성되며, 포토레지스트 패턴(7)을 식각 마스크로 한 습식 및 건식식각방식으로 제2절연막(6), SOG막(5) 및 제1절연막(4)을 순차적으로 식각함에 의해 비아홀(8)이 형성된다.Referring to FIG. 1A, a poly-metal interlayer insulating film 2 is formed on a silicon substrate 1, and a plurality of lower metal wirings 3 are formed on a poly-metal interlayer insulating film 2 through a metal wiring process. do. The first insulating film 4, the SOG film 5, and the second insulating film 6 are sequentially formed on the interlayer insulating film 2 including the plurality of lower metal wires 3. The photoresist pattern 7 is formed on the second insulating layer 6, and the second insulating layer 6, the SOG film 5, and the first are formed by wet and dry etching methods using the photoresist pattern 7 as an etching mask. The via holes 8 are formed by sequentially etching the insulating film 4.
상기에서, 제1 및 2절연막(4 및 6)각각은 플라즈마 화학기상증착법에 의해 TEOS 산화막, SiH4 산화막 또는 실리콘 과다 산화막 등으로 형성되며, 이들 막(4 및 6)은 SOG막(5)에 함유된 수분이 외부확산되는 것을 방지하면서 금속배선간을 전기적으로 절연시킨다. SOG막(5)은 다수의 하부 금속배선(3)이 조밀하게 형성됨에 의해 생기는 갭(gap)을 매우기 위해 스핀방식으로 제1절연막(4)상에 형성된다.In the above, each of the first and second insulating films 4 and 6 is formed of a TEOS oxide film, a SiH4 oxide film or a silicon overoxide film by plasma chemical vapor deposition, and these films 4 and 6 are contained in the SOG film 5. Electrically insulates the metal wires while preventing moisture from spreading outside. The SOG film 5 is formed on the first insulating film 4 in a spin manner in order to fill gaps caused by densely forming a plurality of lower metal wirings 3.
제1b도는 포토레지스트 패턴(7)을 식각 마스크로한 식각공정에 의해 비아홀(8)을 형성한 후, 포토레지스트 패턴(7)을 제거하기 위하여 O2플라즈마 처리를 실시하는 것이 도시된다. 포토레지스트 패턴(7)을 제거하기 위한 O2플라즈마 처리동안에 의해 비아홀(8)의 측벽부분에 노출된 SOG막(5)이 일부 식각되어 SOG막 리세스(10)가 생기게 된다.FIG. 1B shows that the via hole 8 is formed by an etching process using the photoresist pattern 7 as an etching mask, and then subjected to O 2 plasma treatment to remove the photoresist pattern 7. During the O 2 plasma treatment for removing the photoresist pattern 7, the SOG film 5 exposed to the sidewall portion of the via hole 8 is partially etched, resulting in the SOG film recess 10.
제1c도는 O2플라즈마 처리에 의해 포토레지스트 패턴(7)을 완전히 제거한 후, 금속배선 공정을 통해 상부 금속배선(9)을 형성하는데, 비아홀(8)부분에 형성된 SOG막 리세스(10)로 인하여 상부 금속배선(9)의 층덮힘이 열악한 것이 도시된다.FIG. 1C illustrates that the photoresist pattern 7 is completely removed by the O 2 plasma process, and then the upper metal wiring 9 is formed through the metal wiring process. The SOG film recess 10 formed in the via hole 8 is formed. Due to the poor layer covering of the upper metallization 9 is shown.
상술한 바와같이 종래의 방법에 의하면, 포토레지스트 패턴을 식각 마스크로하여 비아홀을 형성한 후, O2플라즈마 처리에 의한 포토레지스트 패턴 제거공정동안 비아홀에 노출된 SOG막이 일부 식각되어 리세스가 형성되고, 이 SOG막의 리세스는 추후 금속배선 공정에서 알루미늄 층덮힘성을 저하시켜 금속배선을 단락시키거나 선이 가늘게 되는 현상을 유발시키므로 인하여 금속배선 신뢰성을 저하시키는 문제가 있다.As described above, according to the conventional method, after the via hole is formed using the photoresist pattern as an etching mask, the SOG film exposed to the via hole is partially etched during the photoresist pattern removal process by O 2 plasma treatment to form a recess. In addition, the recess of the SOG film has a problem of deteriorating the metal wiring reliability by deteriorating the aluminum layer covering property in the metal wiring process in the future, causing short circuit or thinning of the metal wiring.
따라서, 본 발명은 다중 금속배선 구조에서 금속층간 절연막의 평탄화막으로 사용되는 SOG막이 비아홀에서 리세스현상이 유발되는 것을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which a SOG film used as a planarization film of an intermetallic insulating film in a multi-metal wiring structure can prevent a recess phenomenon from occurring in a via hole.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 폴리-금속 층간 절연막상에 다수의 하부 금속배선이 형성된 실리콘 기판이 제공되고, 상기 하부 금속배선을 포함한 상기 폴리-금속층간 절연막상에 제1절연막, SOG막 및 제2절연막을 순차적으로 형성하는 단계; 상기 제2절연막상에 포토레지스트 패턴을 형성한 후, 상기 포토레지스트 패턴을 식각 마스크로한 식각공정으로 상기 제2절연막,상기 SOG막 및 상기 제1절연막을 순차적으로 식각함에 의해 비아홀이 형성되는 단계; 상기 비아홀 측벽에 경화막이 형성하는 단계; 및 상기 포토레지스트 패턴을 제거한 후, 상부 금속배선을 형성하는 단계로 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is provided with a silicon substrate formed with a plurality of lower metal wiring on the poly-metal interlayer insulating film, and is formed on the poly-metal interlayer insulating film including the lower metal wiring Sequentially forming the first insulating film, the SOG film, and the second insulating film; After the photoresist pattern is formed on the second insulating layer, a via hole is formed by sequentially etching the second insulating layer, the SOG layer, and the first insulating layer by an etching process using the photoresist pattern as an etching mask. ; Forming a cured film on sidewalls of the via hole; And after removing the photoresist pattern, forming an upper metal wiring.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a 내지 2c도는 본 발명의 실시예에 의한 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도이다.2A through 2C are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device according to the embodiment of the present invention.
제2a도를 참조하면, 폴리-금속층간 절연막(12)이 실리콘 기판(11)상에 형성되고, 폴리-금속층간 절연막(12)상에는 금속배선공정을 통해 다수의 하부 금속배선(13)이 형성된다. 다수의 하부 금속배선(13)을 포함한 층간절연막(12)상에 제1절연막(14), SOG막(15) 및 제2절연막(16)이 순차적으로 형성된다. 제2절연막(16)상에 포토레지스트 패턴(17)이 형성되며, 포토레지스트 패턴(17)을 식각 마스크로 한 습식 및 건식식각방식으로 제2절연막(16), SOG막(15) 및 제1절연막(14)을 순차적으로 식각함에 의해 비아홀(18)이 형성된다. 포토레지스트 패턴(17)을 마스크로 한 이온주입공정 또는 Ar 스퍼터링공정에 의해 비아홀(18)의 측벽 즉, 제1절연막(14), SOG막(15) 및 제2절연막(16)의 노출면이 치밀화되어 경화막(20)이 형성된다.Referring to FIG. 2A, a poly-metal interlayer insulating film 12 is formed on the silicon substrate 11, and a plurality of lower metal wirings 13 are formed on the poly-metal interlayer insulating film 12 through a metal wiring process. do. The first insulating film 14, the SOG film 15, and the second insulating film 16 are sequentially formed on the interlayer insulating film 12 including the plurality of lower metal wires 13. The photoresist pattern 17 is formed on the second insulating layer 16, and the second insulating layer 16, the SOG film 15, and the first insulating layer 16 are formed by wet and dry etching using the photoresist pattern 17 as an etching mask. The via holes 18 are formed by sequentially etching the insulating layer 14. The sidewalls of the via holes 18, that is, the first insulating film 14, the SOG film 15, and the second insulating film 16 are exposed by an ion implantation process or an Ar sputtering process using the photoresist pattern 17 as a mask. By densification, the cured film 20 is formed.
상기에서, 제1 및 2절연막(14 및 16)각각은 플라즈마 화학기상증착법에 의해 TEOS 산화막, SiH4 산화막 또는 실리콘 과다 산화막 등으로 형성되며, 이들 막(14 및 16)은 SOG막(15)에 함유된 수분이 외부확산되는 것을 방지하면서 금속배선간을 전기적으로 절연시킨다. SOG막(15)은 다수의 하부 금속배선(13)이 조밀하게 형성됨에 의해 생기는 갭(gap)을 매우기 위해 스핀방식으로 제1절연막(14)상에 형성된다. 경화막(20)을 형성하기 위한 이온주입공정은 As, B, BF2, Si중 어느하나 또는 그 이상의 이온을 사용하여 실시되며, 이온입사방식은 수직입사 보다는 경사(tilt)입사방식이 바람직하다.In the above, each of the first and second insulating films 14 and 16 is formed of a TEOS oxide film, a SiH4 oxide film or a silicon overoxide film by plasma chemical vapor deposition, and these films 14 and 16 are contained in the SOG film 15. Electrically insulates the metal wires while preventing moisture from spreading outside. The SOG film 15 is formed on the first insulating film 14 in a spin manner in order to fill gaps formed by densely forming a plurality of lower metal wirings 13. The ion implantation process for forming the cured film 20 is performed using any one or more ions of As, B, BF 2 , Si, and the ion incidence method is preferably a tilt incidence method rather than a vertical incidence method. .
제2b도는 O2플라즈마 처리를 통해 포토레지스트 패턴(17)을 제거하는 것이 도시된다. O2플라즈마 처리동안에 경화막(20)이 SOG막(15)의 식각을 방지하므로 제1b도에 도시된 SOG막 리세스(10)가 생기지 않게 된다.2B shows the removal of the photoresist pattern 17 through an O 2 plasma treatment. Since the cured film 20 prevents etching of the SOG film 15 during the O 2 plasma treatment, the SOG film recess 10 shown in FIG. 1B is not generated.
제2c도는 O2플라즈마 처리에 의해 포토레지스트 패턴(17)을 완전히 제거한 후, 금속배선 공정을 통해 상부 금속배선(19)을 형성하는데, 비아홀(18)부분의 SOG막(15)에 종래와 같은 리세스(10)가 생기지 않으므로 인하여 상부 금속배선(19)의 층덮힘이 개선된 것이 도시된다.FIG. 2C shows that the photoresist pattern 17 is completely removed by the O 2 plasma treatment, and then the upper metal wiring 19 is formed through the metal wiring process. The SOG film 15 of the via hole 18 is similar to the conventional method. It is shown that the layer covering of the upper metallization 19 is improved because the recess 10 does not occur.
상술한 바와같이 본 발명의 실시예에 의하면, 포토레지스트 패턴을 식각 마스크로하여 비아홀을 형성하고, 이온주입공정 또는 Ar 스퍼터링공정으로 비아홀 측벽에 경화막을 형성한 후, O2플라즈마 처리를 통해 포토레지스트 패턴 제거공정을 실시하므로, O2플라즈마 처리동안 비아홀에 노출된 SOG막이 경화막에 의해 식각되는 것이 방지된다.As described above, according to the exemplary embodiment of the present invention, via holes are formed using the photoresist pattern as an etching mask, a cured film is formed on the sidewalls of the via holes by an ion implantation process or an Ar sputtering process, and then photoresist is performed by O 2 plasma treatment. By performing the pattern removal process, the SOG film exposed to the via hole during the O 2 plasma treatment is prevented from being etched by the cured film.
따라서, 본 발명은 비아홀부분으로 노출된 SOG막에 리세스가 생기는 것을 방지하므로 추후 금속배선 공정에서 알루미늄 층덮힘이 개선되고, 비아홀부분으로 노출된 SOG막의 표면에 경화막이 형성되어있어 추후 열공정에서 SOG막으로부터의 수분 배출이 억제되어 금속배선의 신뢰성을 향상시킬 수 있다.Therefore, the present invention prevents recesses in the SOG film exposed through the via hole, so that the aluminum layer covering is improved in the metallization process later, and a cured film is formed on the surface of the SOG film exposed through the via hole. Discharge of moisture from the SOG film can be suppressed to improve the reliability of the metal wiring.
Claims (7)
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| KR1019950065622A KR0172526B1 (en) | 1995-12-29 | 1995-12-29 | Fabrication method of semiconductor device |
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| KR1019950065622A KR0172526B1 (en) | 1995-12-29 | 1995-12-29 | Fabrication method of semiconductor device |
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| US9466623B2 (en) | 2013-08-02 | 2016-10-11 | Samsung Display Co., Ltd. | Method of fabricating display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9466623B2 (en) | 2013-08-02 | 2016-10-11 | Samsung Display Co., Ltd. | Method of fabricating display device |
| US9711545B2 (en) | 2013-08-02 | 2017-07-18 | Samsung Display Co., Ltd. | Method of fabricating display device |
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