KR19980054485A - Metal wiring formation method of semiconductor device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. The technical problem to be solved by the invention

The present invention provides a method for forming a metal wiring in a semiconductor device to remove the peaks of the contact hole inlet and to completely fill the metal film to the bottom of the contact hole.

3. Summary of Solution to Invention

The present invention forms a wine glass contact hole by an isotropic wet etching process and a dry etching process, forms a material film for forming a spacer on the entire structure, and then forms a spacer on the sidewalls of the contact hole by etching the entire surface. The present invention provides a method for forming metal wirings in a semiconductor device to improve the peeling talk of a metal film for forming metal wirings by removing a dot formed at a hole inlet.

4. Important uses of the invention

Used in the metallization process of semiconductor devices.

Description

Metal wiring formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double layer metallization (DLM) process in which an interconnection is formed by using metal wiring as a process after the formation of a capacitor during a semiconductor device manufacturing process. A metal wiring forming method of a semiconductor device for embedding.

In general, the DLM (Double Layer Metalization) process is a process after transistors and capacitors, which are the basis of DRAM devices, are formed to define metal wiring for high speed and reduction of device size. to be.

As the semiconductor device becomes more integrated, the contact hole size decreases and the aspect ratio increases, and as step coverage becomes worse, the metal film for forming the metal wiring is formed. There is not enough filling.

Hereinafter, the metal wire forming process according to the prior art will be described.

First, an insulating film for interlayer insulation and planarization is formed on a semiconductor substrate on which lower metal wiring is already formed, and the interlayer insulation and planarization is performed until the lower metal wiring of a predetermined portion is exposed using a mask for forming a metal wiring contact hole. The insulating film was etched to form a metal wiring contact hole, and then an upper metal wiring metal film was formed.

However, as the metal wiring contact hole formed by the conventional technique has a nearly right-shaped profile, a point (a reference numeral A) is formed at the entrance of the contact hole, and the metal for forming the metal wiring thereafter. In the film formation process, not only the metal film is broken at the tip of the contact hole inlet, but also due to the poor step coverage, the metal film is not buried under the contact hole. There was a problem that the failure of the device by the moisture generated after.

Disclosure of Invention The present invention devised to solve the above problems is to provide a method for forming a metal wiring of a semiconductor device for completely filling a metal film to a lower portion of a contact hole while removing the peaks of the contact hole inlet.

1A to 1D are cross-sectional views of metal wire forming processes in a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: semiconductor substrate 20: lower metal wiring

30, 70: oxynitride film 40: SOG film

50 silicon rich oxide film 60 photoresist pattern

80: titanium film 90: upper metal wiring

In order to achieve the above object, the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate formed with a predetermined lower metal wiring; Etching the interlayer insulating film having a predetermined thickness by isotropic wet etching using a metal wiring contact hole forming mask; Etching the interlayer insulating film having a residual thickness by a dry etching process using the metal wiring contact hole forming mask to form a contact hole exposing a semiconductor substrate of a predetermined portion; Forming a spacer material layer over the entire structure and forming a spacer on the sidewall of the contact hole by etching the entire surface without a mask; And sequentially forming a barrier metal film and an upper metal wiring metal film on the entire structure.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A to 1D are cross-sectional views of a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.

First, FIG. 1A illustrates forming a first aluminum film on a predetermined semiconductor substrate 10, etching the first aluminum film using a metal wiring forming mask to form a lower metal wiring 20, and then overlying the entire structure. The first oxynitride film 30, the SOG film 40, and the silicon rich oxide film 50 are sequentially formed on the substrate to realize insulation and planarization with the upper metal wiring to be formed later, and then the upper portion of the silicon rich oxide film 50. The photoresist is applied to the photoresist, and then the photoresist pattern 60 is formed by an exposure and development process using a mask for forming a metal wiring contact hole.

In this case, instead of the silicon rich oxide film 50, an oxide film may be formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.

Subsequently, in FIG. 1B, a silicon-rich oxide film 50 having a predetermined thickness is removed by an isotropic wet etching process using a BOE solution using the photoresist pattern 60 as an etch mask to widen the contact hole entrance, and the photoresist pattern 60 is removed. ) As an etch mask, the residual silicon rich oxide film 50, the SOG film 40, and the first oxynitride film 30 are sequentially etched until the lower metal wiring 20 of the predetermined portion is exposed to form a wine glass contact hole. After the formation, the photoresist pattern 60 is removed, and then the second oxynitride layer 70 is formed as a spacer material layer on the entire structure. A, B) occurs.

Meanwhile, a titanium film, a titanium nitride film, or a titanium film / titanium nitride film, which is a barrier metal material to be formed later, may be formed instead of the second oxynitride film 70 serving as the spacer material film.

Subsequently, in FIG. 1C, the entire surface of the second oxynitride layer 70 is etched without a mask, and the contact hole is opened by the dry etching, that is, the first oxynitride layer 30, the SOG film 40, and the predetermined portion. The second oxynitride layer spacer 70a is formed on the sidewalls of the silicon rich oxide layer 50 of the silicon rich oxide layer 50. In this case, the peaks A and B are formed during the entire surface etching process for forming the second oxynitride layer spacer 70a. Is removed.

Finally, FIG. 1D sequentially forms a titanium film 80 as a barrier metal film and a second aluminum film for upper metal wiring on the entire structure, and then uses the mask for forming metal wiring to form the second aluminum film and the titanium film 80. ) Is sequentially etched to form the upper metal wiring 90.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention, the wine glass contact hole is formed by an isotropic wet etching process and a dry etching process, a material film for forming a spacer is formed on the entire structure, and then the entire surface is etched to form a spacer on the sidewall of the contact hole. At the same time, by removing the peaks formed at the inlet of the contact hole, it is possible to improve the peeling talkability of the metal film for forming the metal wiring to prevent the PCT fail later to improve the yield and reliability of the semiconductor device.

Claims (2)

Forming an interlayer insulating film on a semiconductor substrate on which a predetermined lower metal wiring is formed; Etching the interlayer insulating film having a predetermined thickness by isotropic wet etching using a metal wiring contact hole forming mask; Etching the interlayer insulating film having a residual thickness by a dry etching process using the metal wiring contact hole forming mask to form a contact hole exposing a semiconductor substrate of a predetermined portion; Forming a spacer material layer over the entire structure and forming a spacer on the sidewall of the contact hole by etching the entire surface without a mask; And Forming a barrier metal film and an upper metal wiring metal film in order on the entire structure. The method of claim 1, And the interlayer insulating film is a film in which an oxynitride film, an SOG film, and a silicon rich oxide film are sequentially stacked.