KR100336653B1 - Method for forming via contact in semiconductor device - Google Patents
Method for forming via contact in semiconductor device Download PDFInfo
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- KR100336653B1 KR100336653B1 KR1019950026725A KR19950026725A KR100336653B1 KR 100336653 B1 KR100336653 B1 KR 100336653B1 KR 1019950026725 A KR1019950026725 A KR 1019950026725A KR 19950026725 A KR19950026725 A KR 19950026725A KR 100336653 B1 KR100336653 B1 KR 100336653B1
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- metal wiring
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- via contact
- film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 비아콘택 형성방법에 관한 것으로, 제1금속 배선에 제2금속배선을 콘택시킬 때 콘택부위에 발생할 수 있는 단점을 방지하기위하여 제1금속배선의 측벽에 절연막 스페이서를 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.The present invention relates to a method for forming a via contact of a semiconductor device, by forming an insulating film spacer on the sidewall of the first metal wiring in order to prevent the disadvantage that may occur in the contact portion when contacting the second metal wiring to the first metal wiring. The present invention relates to a technology capable of improving the characteristics and reliability of semiconductor devices.
종래의 비아콘택 형성방법은 제1금속배선을 형성하고 전체표면상부를 에스.오.지 ( SOG : Spin On Glass, 이하에서 SOG 라 함 ) 막을 층간절연막으로하여 평탄화시킨다. 그리고, 비아콘택마스크(도시안됨)를 이용한 식각공정으로 상기 제1금속개선을 노출시키는 비아콘택홀을 형성한다. 그리고, 상기 비아콘택홀을 통하여 상기 제1금속배선에 접속되는 제2금속배선을 형성한다.In the conventional via contact forming method, the first metal wiring is formed and planarized by using an SG (Spin On Glass, SOG) film as the interlayer insulating film on the entire surface. A via contact hole exposing the first metal improvement is formed by an etching process using a via contact mask (not shown). A second metal wiring connected to the first metal wiring is formed through the via contact hole.
그러나, 상기 종래기술은 콘택홀 형성후에 노출되는 상기 제1금속배선이 상기 SOG 막에 함유되어 있는 수분으로 인하여 부식되는 경우가 발생됨으로써 반도체소자의 특성, 수율 및 신뢰성을 저하시키는 문제점이 있다.However, the prior art has a problem in that the first metal wiring exposed after the formation of the contact hole is corroded due to moisture contained in the SOG film, thereby degrading the characteristics, yield and reliability of the semiconductor device.
따라서, 본 발명은 종래기술의 문제점을 해결하기위하여, 제1금속배선과 층간절연막의 집적적인 접촉을 방지하여 상기 층간절연막으로인한 문제점을 해결함으로써 반도체소자의 특성, 수율 및 신뢰성을 향상시킬 수 있는 반도체소자의 비아콘택 형성방법을 제공하는데 그 목적이 있다.Therefore, the present invention can improve the characteristics, yield and reliability of the semiconductor device by solving the problems caused by the interlayer insulating film by preventing the integrated contact between the first metal wiring and the interlayer insulating film to solve the problems of the prior art. It is an object of the present invention to provide a method for forming a via contact of a semiconductor device.
이상의 목적을 달성하기위한 본 발명인 반도체소자의 비아콘택 형성 방법의 특징은, 하부구조물이 형성된 반도체기판 상부에 제1금속배선 물질을 일정두께 형성하는 공정과,Features of the via contact forming method of the semiconductor device of the present invention for achieving the above object is a step of forming a predetermined thickness of the first metal wiring material on the upper surface of the semiconductor substrate formed with a lower structure,
상기 제1금속배선물질 상부에 반사방지막을 형성하는 공정과,Forming an anti-reflection film on the first metal wiring material;
마스크를 이용한 식각공정으로 상기 비아콘택될 부분을 제외한 부분을 일정두께 식각함으로써 제1금속배선을 형성하는 공정과,Forming a first metal interconnection by etching a portion except for the via contact portion by an etching process using a mask;
전체표면상부에 제1금속층간절연막을 형성하는 공정과,Forming a first interlayer insulating film over the entire surface;
전체표면상부에 평탄화층을 형성하는 공정과,Forming a planarization layer on the entire surface;
전면식각공정으로 상기 평탄화층을 일정두께 식각하는 동시에 상기 제1금속배선의 식각면에 제1금속층간절연막 스페이서를 형성하는 공정과,Forming a first interlayer dielectric layer spacer on an etched surface of the first metal wiring at the same time by etching the planarization layer to a predetermined thickness by a front surface etching process;
전체표면상부에 제2금속층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
비아콘택마스크를 이용한 식각공정으로 상기 제1금속배선을 노출시키는 비아콘택홀을 형성하는 공정과,Forming a via contact hole exposing the first metal wiring by an etching process using a via contact mask;
상기 비아콘택홀을 통하여 상기 제1금속배선에 접속되는 제2금속배선을 형성하는 공정을 포함하는데 있다.And forming a second metal wiring connected to the first metal wiring through the via contact hole.
또한, 상기 제1금속배선은 알루미늄박막으로 형성되는 것과,In addition, the first metal wiring is formed of an aluminum thin film,
상기 제1금속배선은 상기 제2금속배선이 형성될 부분까지 두껍게 형성되는는 것과,The first metal wiring is formed to be thick to the portion where the second metal wiring is to be formed,
상기 반사방지막은 티타늄막/티타늄질화막 적층구조로 형성되는 것과,The anti-reflection film is formed of a titanium film / titanium nitride film laminated structure,
상기 제 1, 2 층간절연막은 TEOS 산화막으로 형성되는 것과,The first and second interlayer insulating film is formed of a TEOS oxide film,
상기 평탄화층은 SOG 막으로 형성되는 것과,The planarization layer is formed of an SOG film,
상기 제2금속배선은 알루미늄박막으로 형성되는 것이다.The second metal wiring is formed of an aluminum thin film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1A도 내지 제1E도는 본 발명의 실시예에 따른 반도체소자의 비아콘택 형성방법을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a method for forming a via contact of a semiconductor device according to an embodiment of the present invention.
제1A도를 참조하면, 단위 셀을 구비한 반도체기판(1)에 제1금속배선(2)물질을 증착한 후 사진공정을 위한 반사방지막(3)을 증착후 사진, 식각공정을 거쳐 제1금속배선(2)을 정의한다.Referring to FIG. 1A, after depositing a first metal interconnection (2) material on a semiconductor substrate 1 having unit cells, an antireflection film 3 for a photographing process is deposited, followed by a photograph and an etching process. The metal wiring 2 is defined.
여기에서 제1금속배선(2)물질의 두께는 제2금속배선층(도시안됨)이 증착될 높이까지 두껍게 증착한다.Here, the thickness of the material of the first metal wiring 2 is deposited to a height where the second metal wiring layer (not shown) is deposited.
그리고, 상기 제1금속배선(2)은 알루미늄박막이나 텅스텐으로 형성된 것이다.The first metal wire 2 is made of aluminum thin film or tungsten.
제1B도를 참조하면, 제1A도와 같이 형성한 제1금속배선(2)물질을 사진, 식각공정을 거쳐 제2금속배선층과 콘택될 부위를 남기고 나머지 금속배선을 일정두께만 식각하여 제1금속배선층(2)을 플러그 형태로 만든 상태를 나타내는 단면도이다. 이때, 상기 일정두께는 상기 제1금속배선층(2) 전체두께의 1/4 내지 3/4 두께이다.Referring to FIG. 1B, the first metal wiring (2) material formed as shown in FIG. 1A is photographed and etched, leaving portions to be contacted with the second metal wiring layer and etching the remaining metal wiring only a predetermined thickness. It is sectional drawing which shows the state which made the wiring layer 2 into plug shape. In this case, the predetermined thickness is 1/4 to 3/4 of the total thickness of the first metal wiring layer 2.
제1C도를 참조하면, 제1B도와 같이 형성한 플러그 형태의 제1금속배선층(2)위에 제1금속층간절연막(4)을 일정두께 증착한다. 그리고, 상기 제1금속층간절연막(4) 상부에 SOG 막(5)을 형성하여 평탄화시킨다.Referring to FIG. 1C, a first metal interlayer insulating film 4 is deposited to a predetermined thickness on the plug-shaped first metal wiring layer 2 formed as in FIG. 1B. Then, an SOG film 5 is formed on the first interlayer insulating film 4 and planarized.
여기서, 상기 제1금속층간절연막(4)은 TEOS 산화막, 과잉 실리콘산화막 또는 산화질화막으로 형성된 것이다.Here, the first intermetallic insulating film 4 is formed of a TEOS oxide film, an excess silicon oxide film, or an oxynitride film.
제1D도를 참조하면, 전면식각을 실시하여 제1금속배선(2)의 플러그 측벽에 제1금속층간절연막(4)이 드러나도록 한다. 이때, 제1층간절연막(4)과 SOG 막(5)간의 식각선택비 차이는 상기 SOG 막(5)이 더욱 빠르기 때문에 제1금속배선층(2)의 측벽에 제1금속절연막층(4) 스페이서를 형성할 수 있다. 그리고, 전체표면상부에 제2금속층간절연막(7)을 증착한다.Referring to FIG. 1D, the first metal interlayer insulating film 4 is exposed on the sidewall of the plug of the first metal wire 2 by performing an entire surface etching. At this time, the difference in etching selectivity between the first interlayer insulating film 4 and the SOG film 5 is faster because the SOG film 5 is faster, so that the spacers of the first metal insulating film layer 4 on the sidewalls of the first metal wiring layer 2 are different. Can be formed. Then, the second intermetallic insulating film 7 is deposited on the entire surface.
여기서, 상기 제2금속층간절연막(7)은 TEOS 산화막, 과잉 실리콘산화막 또는 산화질화막으로 형성된 것이다.The second metal interlayer insulating film 7 is formed of a TEOS oxide film, an excess silicon oxide film, or an oxynitride film.
제1E도를 참조하면, 비아콘택마스크(도시안됨)를 이용한 식각공정으로 상기 제2금속층간절연막(7)을 식각함으로써 상기 제1금속배선(2)의 플러그 형상 상부를노출시키는 비아콘택홀(8)을 형성한다. 그리고, 상기 비아콘택홀(8)을 통하여 상기 제1금속배선(2)에 접속되는 제2금속배선(9)을 형성한다.Referring to FIG. 1E, a via contact hole exposing an upper portion of a plug shape of the first metal interconnection 2 by etching the second interlayer insulating layer 7 by an etching process using a via contact mask (not shown). 8) form. Then, the second metal wiring 9 connected to the first metal wiring 2 is formed through the via contact hole 8.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 비아콘택 형성방법은, 제1금속배선과 평탄화층으로 사용되는 SOG 막과의 접촉을 방지하여 비아콘택의 열화를 억제함으로써 반도체소자의 특성, 수율 및 신뢰성을 향상시킬 수 있는 잇점이 있다.As described above, the method for forming a via contact of a semiconductor device according to the present invention prevents contact between the first metal wiring and the SOG film used as the planarization layer, thereby suppressing deterioration of the via contact, thereby improving characteristics, yield and There is an advantage in improving reliability.
제 1A 도 내지 제 1E 도는 본 발명의 실시예에 따른 반도체소자의 비아콘택 형성공정을 도시한 단면도.1A to 1E are cross-sectional views illustrating a via contact forming process of a semiconductor device in accordance with an embodiment of the present invention.
◈ 도면의 주요부분에 대한 부호의 설명◈ Explanation of symbols for the main parts of the drawings
1 : 반도체기판 2 : 제1금속배선1: semiconductor substrate 2: first metal wiring
3 : 반사방지막 4 : 제1금속층간절연막3: antireflection film 4: first metal interlayer insulating film
5 : SOG 막 7 : 제2금속층간절연막5: SOG film 7: Second metal interlayer insulating film
8 : 비아콘택홀 9 : 제2금속배선8: Via contact hole 9: Second metal wiring
Claims (7)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950026725A KR100336653B1 (en) | 1995-08-26 | 1995-08-26 | Method for forming via contact in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950026725A KR100336653B1 (en) | 1995-08-26 | 1995-08-26 | Method for forming via contact in semiconductor device |
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| KR970013044A KR970013044A (en) | 1997-03-29 |
| KR100336653B1 true KR100336653B1 (en) | 2002-11-02 |
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| KR1019950026725A KR100336653B1 (en) | 1995-08-26 | 1995-08-26 | Method for forming via contact in semiconductor device |
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