KR100486610B1 - Method for manufacturing capacitor of semiconductor device - Google Patents

Abstract

The present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Selectively etching the interlayer insulating layer to form a bit line contact hole; Forming a polysilicon layer to fill the bit line contact holes; Forming a WSi layer on the polysilicon layer using DCS as a source; Forming a mask oxide film on the WSi layer; Patterning the mask oxide film and the WSi layer to form a bit line formed of the polysilicon layer and the WSi layer; Forming a spacer on a side of the bit line; Forming a barrier nitride film having a high etching selectivity with respect to an oxide film on an entire surface including the bit line; Forming an oxide film having a high etching ratio on the barrier nitride film; Selectively etching the oxide layer and the barrier nitride layer to form a contact hole in which a storage node is to be formed; Forming an amorphous silicon layer on the entire surface of the substrate including the contact hole; Forming a buried material layer on the amorphous silicon layer; Etching the buried material layer over the entire surface to simultaneously expose the oxide layer and the amorphous silicon layer having a high etching ratio; Forming a cup-type storage node inside the contact hole by etching the amorphous silicon layer over the entire surface; Wet etching the oxide layer and the buried material layer having a high etching ratio; Removing the barrier nitride layer by etching the entire surface; And forming a selective hemispherical silicon on the front surface of the storage node, and pretreatment of the semiconductor device to reduce the content of F in the WSi layer before forming the mask oxide film, the spacer, and the barrier nitride film. By providing a method, it is possible to suppress the external diffusion of elements with high diffusion coefficients, thereby eliminating the factor of decreasing the grain size of the hemispherical silicon, thereby increasing the capacitor effective surface area, thereby increasing the charge capacity.

Description

METHODS FOR MANUFACTURING CAPACITOR OF SEMICONDUCTOR DEVICE

The present invention relates to a method of manufacturing a capacitor of a semiconductor device using hemispherical silicon, and more particularly, to a method of forming a charge storage electrode under a capacitor using hemispherical silicon.

As semiconductor devices have been highly integrated, process margins have become smaller, and techniques for securing process margins during contact etching, such as nitride barrier self aligned contact (NBSAC) processes, have been used. Accordingly, in the element of 0.25 µm or less in design rule, a contact and a capacitor are formed using an NBSAC structure. In addition, a COB (capacitor over bit line) process is used in which a capacitor is formed on the bit line to secure sufficient charge capacity for device operation in a narrow space. In order to increase the effective surface area on the capacitor thus formed, hemispherical silicon may be formed, but a selective hemispherical silicon forming method is gradually being used.

In general, the selective hemispherical silicon formation process is performed after spinning the silicon gas, and the underlying silicon atoms are surface migrated by subsequent heat treatment around the nucleus formed by the silicon source, so that the growth of grain is achieved. This is possible with amorphous silicon. When the selective hemispherical silicon is used, there is no need to separate the cell from the cell, and thus, it is evaluated that the process margin can be secured and the mass production can be secured due to the high integration of the device.

However, since the selective hemispherical silicon formation process is grain growth by surface movement, it should provide a condition that does not prevent surface movement. These attributes selective hemispherical silicon forming step is to proceed predominantly in the ultra-high vacuum ^(~ 10 ^-4 Torr) the state of the surface oxide film is removed completely by hydrofluoric acid solution in the state. However, when the capacitor is formed by the NBSAC process, the nitride film, which is an etch stop film, is exposed in the peripheral circuit area, and thus must be removed because it serves as an etch stop film in the subsequent multi-layer metalization (MLM) process. In general, such a nitride film removal process is performed through full surface etching. If the front side etching is performed after the formation of the hemispherical silicon, the hemispherical silicon of the cell region is also cut to some extent to lose the charge capacity. Etching the nitride film is advantageous in terms of securing a filling capacity. However, if the nitride film is etched before the formation of the selective hemispherical silicon, the formation of the selective hemispherical silicon is difficult to occur. This results in a layer having a high diffusion coefficient during the process, which causes silicon atoms to be out-diffused. This is because it hinders the surface movement of the metals, thereby preventing the formation of selective hemispherical silicon. A representative example of such an element having a high diffusion coefficient is F (fluorine), which is a selective hemispheric type of WF6, which is a reaction gas used for depositing WSi in the bit line forming process, and does not react during deposition. When the silicon forming process ( ^~ 600 ℃) is in progress, it is diffused out. Therefore, a new process is needed to prevent the external diffusion of elements with high diffusion coefficients.

1A and 1B illustrate a cup-shaped capacitor manufacturing process according to the prior art. FIG. 1A is a cross-sectional view after forming a bit line. First, a word line 4 is formed, a first interlayer insulating film 6 is formed, and a source / drain region penetrates through the first interlayer insulating film 6. After forming the first contact hole in contact with the first contact hole, the first doped polysilicon is embedded in the first contact hole to form the contact plug 8. This contact plug 8 comes into contact with the capacitor storage node in a subsequent process. Subsequently, after forming a capping oxide film for insulation between the contact plug 8 and the bit line to be formed later, a bit line contact hole penetrating the capping oxide film and the first interlayer insulating film 6 is formed. The second doped polysilicon filling the line contact hole is deposited, and the WSi is deposited on the entire surface of the substrate to form the bit line 10 through a mask etching process. The second doped polysilicon and WSi form a bit line 10. In the mask etching process, a mask oxide layer is deposited on the WSi to prevent a short circuit between the barrier for etching and the storage node formed in a subsequent process. In general, the mask oxide film is deposited at 1000Å and then the photolithography process is performed. The thickness of the mask oxide film is the etching process, that is, the oxide film during the contact etching process for the loss of the oxide film during the bit line etching process and the storage node formation of the capacitor. Loss, oxide loss during the entire surface etching process of the barrier nitride film, and loss of oxide film during the cleaning process before and after each process.

1B illustrates a process of forming a cup-shaped capacitor storage node after the bit line is formed. First, a second interlayer insulating film 12, for example, MTO or TEOS, is formed on the entire structure including the bit line 10 and the first interlayer insulating film 6 (the capping oxide film is etched away during bit line etching). . Part of the second interlayer insulating film 12 is etched so that the storage node to be formed later and the first interlayer insulating film 6 are connected to each other so that the second interlayer insulating film 12 is formed to have a thickness of, for example, 200 Å or less. Subsequently, after forming the barrier nitride film 14 thereon, an oxide film such as PSG having a high etching ratio is formed on the entire surface of the substrate. Subsequently, a second contact hole is formed through the PSG film and in contact with the contact plug 8. In the etching process of forming the second contact hole, the barrier nitride layer 14 serves as an etch stop layer of the PSG layer. Therefore, after the PSG film is etched, the nitride film 14 must be etched. At this time, the nitride film is excessively etched. Accordingly, the second interlayer insulating film is simultaneously etched, so that the second interlayer insulating film hardly remains on the side of the bit line 10.

Subsequently, after the third doped amorphous silicon 16 is deposited along the second contact hole, a buried material such as photoresist, PSG, SOG, and the like is deposited thereon. The buried material should be formed in a low temperature process such that the third doped amorphous silicon layer 16 is not converted into polysilicon.

Subsequently, the buried material layer is etched by using an entire surface etching process or a CMP to expose the third amorphous silicon layer 16, and then, by removing the third amorphous layer on the oxide layer through the entire surface etching, inter-cell insulation is realized. do. Subsequently, the buried material filling the inside of the cup is removed (wet dipping in the case of an oxide film, CMP, full etching or exposure in the case of a photoresist), and then wet dipped in the oxide film to remove the cup structure. The capacitor storage node 16 is completed. Then, a selective hemispherical silicon formation process (not shown) is performed.

Since the process of removing the nitride film during the process is performed only in the second contact hole, it is necessary to etch again to form the contact hole during the subsequent MLM process. Since the nitride film etching process is performed before the selective hemispherical silicon forming process, the etching damage of the hemispherical silicon can be reduced, which is advantageous in terms of increasing the capacitor value. However, if the nitride film is removed before the hemispherical silicon formation process, the bit line is exposed (especially in the peripheral circuit area), so that the F element having a high diffusion coefficient penetrates through the thin oxide film surrounding the bit line, thus preventing the surface movement of the silicon atom. Prevents hemispherical silicon formation

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and by suppressing the external diffusion of elements having high diffusion coefficients to eliminate the factor of decreasing the grain size of the hemispherical silicon, the effective surface area of the capacitor can be increased to increase the charging capacity. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device.

A capacitor manufacturing method of a semiconductor device for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Selectively etching the interlayer insulating layer to form a bit line contact hole; Forming a polysilicon layer to fill the bit line contact holes; Forming a WSi layer on the polysilicon layer using DSC as a source; Forming a mask oxide film on the WSi layer; Patterning the mask oxide film and the WSi layer to form a bit line formed of the polysilicon layer and the WSi layer; Forming a spacer on a side of the bit line; Forming a barrier nitride film having a high etching selectivity with respect to an oxide film on an entire surface including the bit line; Forming an oxide film having a high etching ratio on the barrier nitride film; Selectively etching the oxide layer and the barrier nitride layer to form a contact hole in which a storage node is to be formed; Forming amorphous silicon on the entire surface of the substrate including the contact hole; Forming a buried material layer on the amorphous silicon layer; Etching the buried material layer over the entire surface to simultaneously expose the oxide layer and the amorphous silicon layer having a high etching ratio; Forming a cup-type storage node inside the contact hole by etching the amorphous silicon layer over the entire surface; Wet vision of the oxide layer and the buried material layer having a high etching ratio; Removing the barrier nitride layer by etching the entire surface; And forming a selective hemispherical silicon on the front surface of the storage node, and performing pre-heat treatment to reduce the content of F in the WSi layer before forming the mask oxide film, the spacer, and the barrier nitride film.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A, 2B, and 2C illustrate a method of manufacturing a capacitor of a semiconductor device using hemispherical silicon according to the present invention in accordance with a process sequence.

First, referring to FIG. 2A, the same process is performed until the WSi deposition process of forming the bit line of FIG. 1A of the prior art. Subsequently, the mask oxide film 18 is formed to be thicker than the thickness conventionally used in the mask oxide film process, for example, 1500 Å or more, and then the bit line 10 is formed through the mask etching process. As the mask oxide film 18, an LPCVD oxide film such as MTO TEOS HTO or a PECVD oxide film such as PE-oxide film or PE-TEOS is used. Next, as a spacer oxide film, an LPCVD oxide film such as MTO, TEOS, HTO, etc. is formed on the entire surface including the bit line at a predetermined thickness (600-1000 kPa), and the entire surface is etched to form the spacer 20 on the side of the bit line. do.

Next, referring to FIG. 2B, a second interlayer insulating film 12, for example, MTO or TEOS, is formed on the entire surface of the substrate. Part of the second interlayer insulating film 12 is etched so that the storage node to be formed later and the first interlayer insulating film 6 are connected to each other so that the second interlayer insulating film 12 is formed to have a thickness of, for example, 200 Å or less. Subsequently, after forming the barrier nitride film 14 thereon, an oxide film such as PSG having a high etching ratio is formed on the entire surface of the substrate. Subsequently, a second contact hole is formed through the PSG film and in contact with the contact plug 8. In the etching process of forming the second contact hole, the barrier nitride layer 14 serves as an etch stop layer of the PSG layer. Subsequently, after the third doped amorphous silicon 16 is deposited along the second contact hole, a buried material such as photoresist, PSG, SOG, and the like is deposited thereon. Formation of this buried material proceeds to a low temperature process such that the third doped amorphous silicon layer 16 is not converted to polysilicon. The third amorphous silicon 16 is preferably formed to a thickness of 300-3000 kPa at a temperature of 450-530 ℃. In addition, the third amorphous silicon layer may be formed of a structure in which undoped amorphous silicon and doped amorphous silicon are laminated. In this case, the thickness of the undoped amorphous silicon is preferably 30-150 kPa, and the doped The impurity concentration in the amorphous silicon is preferably set to 10 ²⁰ -10 ²² atoms / cm ³ .

Subsequently, the buried material layer is etched by using an entire surface etching process or a CMP to expose the third amorphous silicon layer 16, and then, by removing the third amorphous layer on the oxide layer through the entire surface etching, inter-cell insulation is realized. do. Subsequently, the buried material filling the inside of the cup is removed (wet dipping in the case of an oxide film, wet dipping in the case of a photoresist, CMP, full etching or exposure in the case of a photoresist), and then the oxide film is wet dipped to remove the cup structure. Complete the capacitor storage node 16.

Next, referring to FIG. 2C, hemispherical silicon 20 is formed on the entire surface of the capacitor storage node 16. As described above, the process of removing the nitride film during the process is performed only in the second contact hole, so that the etching process is performed once again to form the contact hole during the subsequent MLM process. In the cup-shaped capacitor storage node structure formed by the present invention, since the bit line is wrapped with the thick mask oxide film 18 and the spacer 20, the external diffusion of F, an element having a high diffusion coefficient in the bit line, is suppressed. Therefore, it is possible to remove the nitride film through the barrier nitride film front etching process before the selective hemispherical silicon forming process. Subsequently, the selective hemispherical silicon formation process can be used to maximize the effective surface area of the capacitor since there is no need to perform full etching later. In addition, when the cup-shaped capacitor is formed according to the present invention, since a thick oxide film exists between the bit line and the storage node, the parasitic charging capacity can be reduced, thereby increasing the reliability of device operation.

Another way to reduce the F content in the bitline is as follows. In general, dichlorosilane (DCS) and monosilane (MS) are used as silicon sources in the reaction gas for depositing WSi. The smaller F content in the film after deposition is the case of using DCS. When using the MS but there are F containing ^{20 to} 10 degree in the film, there are contained ^{17 to} 10 degree when using the DCS. Therefore, in order to reduce the absolute amount of F using the WSi using a DCS source and, in a subsequent deposition step (e.g., the mask oxide film, a spacer oxide film, a barrier nitride layer, such as a bit line forming step of the layer is in contact directly) prior to the deposition N _2, Preheat treatment at a constant temperature (eg, 30 minutes) at a constant temperature (eg, 600 ° C.) in an atmosphere of an inert gas such as Ar reduces the F content in the WSi film to form selective hemispherical silicon so as not to disturb surface movement.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

In the process of forming a cup-shaped capacitor storage node in the conventional NBSAC process, a thick oxide film is formed around the bit line by depositing a thick mask oxide film when forming the bit line, and forming a spacer oxide film after forming the bit line. This made it possible to etch the barrier nitride film prior to the selective hemispherical silicon deposition process. Therefore, it is possible to reduce the grain size of the hemispherical silicon to contribute to increase the effective surface area of the capacitor, and to improve the device characteristics by reducing the parasitic charge capacity.

1A and 1B are cross-sectional views illustrating a method of forming a capacitor storage node according to the prior art.

2A to 2C are cross-sectional views illustrating a method of forming a capacitor storage node according to the present invention.

* Description of the main parts of the drawing

16: capacitor storage node 20: spacer

18: mask oxide film

Claims (16)

Forming an interlayer insulating film on the semiconductor substrate; Selectively etching the interlayer insulating layer to form a bit line contact hole; Forming a polysilicon layer to fill the bit line contact holes; Forming a WSi layer on the polysilicon layer using DSC as a source; Forming a mask oxide film on the WSi layer; Patterning the mask oxide film and the WSi layer to form a bit line formed of the polysilicon layer and the WSi layer; Forming a spacer on the side of the bit line; Forming a barrier nitride film having a high etching selectivity with respect to an oxide film on an entire surface including the bit line; Forming an oxide film having a high etching ratio on the barrier nitride film; Selectively etching the oxide layer and the barrier nitride layer to form a contact hole in which a storage node is to be formed; Forming an amorphous silicon layer on the entire surface of the substrate including the contact hole; Forming a buried material layer on the amorphous silicon layer; Etching the buried material layer over the entire surface to simultaneously expose the oxide layer and the amorphous silicon layer having a high etching ratio; Forming a cup-type storage node inside the contact hole by etching the amorphous silicon layer over the entire surface; Wet etching the oxide layer and the buried material layer having a high etching ratio; Removing the barrier nitride layer by etching the entire surface; And Forming a selective hemispherical silicon on the front side of the storage node; And pretreatment the semiconductor device to reduce the content of F in the WSi layer before forming the mask oxide film, the spacer, and the barrier nitride film. The method of claim 1, And the mask oxide film is formed to a thickness of about 1500-2000 microns. The method of claim 1, An LPCVD oxide film such as MTO, TEOS, HTO, etc. is used as the mask oxide film. The method of claim 1, The preheating treatment performed before the mask oxide film is formed is performed in an inert gas atmosphere. The method of claim 4, wherein The pre-heat treatment is carried out at 600-700 ° C capacitor manufacturing method of a semiconductor device. The method of claim 4, wherein The preheating process is performed for 30 minutes to 60 minutes. The method of claim 1, And a PECVD oxide film such as PE-oxide film, PE-TEOS, etc. as the mask oxide film. The method of claim 1, And forming an oxide film on the spacers. The method of claim 8, And an LPCVD oxide film such as MTO, TEOS, HTO, etc., as the oxide film. The method of claim 1, The preheating process performed before the spacer is formed, the method of manufacturing a capacitor of a semiconductor device, characterized in that the progress in an inert gas atmosphere. The method of claim 10, The pre-heat treatment is performed at 600-700 ° C capacitor manufacturing method of a semiconductor device. The method of claim 10, The pre-heat treatment is performed for 30 minutes-60 minutes capacitor manufacturing method of a semiconductor device. The method of claim 8, And forming the oxide film at a thickness of 600-1000 kPa. The method of claim 1, The preheating process performed before the barrier nitride film is formed is performed in an inert gas atmosphere. The method of claim 14, The preheating process is a capacitor manufacturing method of a semiconductor device, characterized in that proceeding at 600-700 ℃. The method of claim 14, And said preheating is performed for 30 minutes to 60 minutes.

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