JPS6321850A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6321850A
JPS6321850A JP16711586A JP16711586A JPS6321850A JP S6321850 A JPS6321850 A JP S6321850A JP 16711586 A JP16711586 A JP 16711586A JP 16711586 A JP16711586 A JP 16711586A JP S6321850 A JPS6321850 A JP S6321850A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor device
photoresist
liquid material
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16711586A
Other languages
Japanese (ja)
Inventor
Masaaki Ikegami
雅明 池上
Mitsuyoshi Nakamura
充善 中村
Hajime Arai
新井 肇
Masanori Obata
正則 小畑
Junichi Arima
純一 有馬
Junichi Moriya
純一 守谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16711586A priority Critical patent/JPS6321850A/en
Publication of JPS6321850A publication Critical patent/JPS6321850A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To increase the thickness of a flattened insulating film and uniformize the film, and to prevent it from cracking by forming the insulating film before removing a photoresist and dipping it in a liquid material. CONSTITUTION:With a photoresist 3 as a mask a gate electrode 2 is etched. Then, the edged electrode 2 is dipped, for example, together with the photoresist 3 in a liquid material, such as an SOG to form a flattened insulating film 4, and is heat treated. Further, after the photoresist is removed to flatten the film 4, an insulating film 5 made of PSG or BPSG is formed, for example, by depositing by a CVD method, heat treated, and flattened. That is, the film is formed by dipping it in the liquid material to increase the thickness of the film and to uniformize it, thereby preventing it from cracking.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は半導体装置の製造方法に関し、特に半導体基
板上に配線または電極を形成する半導体装置の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device in which wiring or electrodes are formed on a semiconductor substrate.

[従来の技術] 第2図は従来技術による半導体装置の製造工程の主要部
を示す断面図である。
[Prior Art] FIG. 2 is a cross-sectional view showing the main part of the manufacturing process of a semiconductor device according to the prior art.

図において、たとえばCVD法による堆積等によりシリ
コン基板1上にゲート電極2を形成し、その上にレジス
トを塗布し写真製版等によってフオドレジスト3を作製
する(第2図(a)参照)。
In the figure, a gate electrode 2 is formed on a silicon substrate 1 by, for example, deposition using the CVD method, a resist is applied thereon, and a photoresist 3 is produced by photolithography or the like (see FIG. 2(a)).

次に・フォトレジスト3をマスクとしてゲート電極2を
エツチング(第2図(b)参照)しだ後・フォトレジス
トを除去する(第2図(C)参照)。
Next, the gate electrode 2 is etched using the photoresist 3 as a mask (see FIG. 2(b)), and then the photoresist is removed (see FIG. 2(c)).

さらに、たとえばSOG (Spin  On  Gl
ass)等の液体材料を回転塗布して平坦化絶縁膜4を
形成し、熱処理を施すことによって平坦化絶縁膜4を安
定化させる(第2図(d)W照)。
Furthermore, for example, SOG (Spin On Gl
A flattened insulating film 4 is formed by spin-coating a liquid material such as (as) or the like, and the flattened insulating film 4 is stabilized by heat treatment (see W in FIG. 2(d)).

最後に、たとえばPSG(Phospho  Si11
cate  Glass)膜、または、BPSG(Bo
rophospho  5ilicateGlass)
等の絶縁膜5をCVD法等による堆積で形成(第2図(
e)参照)させ、熱処理を施した後に平坦化させる。
Finally, for example PSG (Phospho Si11
cate Glass) membrane or BPSG (Bo
rophospho 5ilicateGlass)
An insulating film 5 such as the one shown in FIG.
(see e)), and after heat treatment, it is flattened.

第3図は上記第2図(d)に示している平坦化絶縁膜4
まわりの拡大図であり、平坦化絶縁膜4のコーナ部にク
ラック6が発生しているところである。
FIG. 3 shows the flattened insulating film 4 shown in FIG. 2(d) above.
This is an enlarged view of the surrounding area, showing a crack 6 occurring at a corner of the flattened insulating film 4.

[発明が解決しようとする問題点] 上記のような従来の半導体装置の製造方法では、平坦化
絶縁膜4を回転塗布によって形成しているため、平坦化
絶縁膜4の厚膜化が難しく、また、第3図に示すように
十分な平坦化がなされないため膜厚が不均等になってい
た。したがって、平坦化絶縁膜4の回転塗布の熱処理に
よる熱応力によって第3図に示すような平坦化絶縁膜4
のコーナ部にクラックが生じ易く、このクラック6が、
絶縁層の耐絶縁性および耐湿性の低下をもたろし、半導
体装置の電気特性上に悪影響を及ぼしていた。
[Problems to be Solved by the Invention] In the conventional semiconductor device manufacturing method as described above, the planarizing insulating film 4 is formed by spin coating, so it is difficult to increase the thickness of the planarizing insulating film 4. Further, as shown in FIG. 3, the film thickness was uneven because sufficient planarization was not achieved. Therefore, due to the thermal stress caused by the heat treatment during spin coating of the flattened insulating film 4, the flattened insulating film 4 as shown in FIG.
Cracks are likely to occur at the corners of the
This causes a decrease in the insulation resistance and moisture resistance of the insulating layer, and has an adverse effect on the electrical characteristics of the semiconductor device.

この発明は、かかる問題を解決するためになされたもの
で、平坦化絶縁膜の厚膜化および均一化を図り、クラッ
クの発生を防止することによって良好な電気特性をもつ
半導体装置の製造方法を得ることを目的とする。
This invention was made to solve this problem, and provides a method for manufacturing a semiconductor device that has good electrical characteristics by increasing the thickness and uniformity of the planarizing insulating film and preventing the occurrence of cracks. The purpose is to obtain.

[問題点を解決するための手段] この発明に係る半導体装置の製造装置は、平坦化絶縁膜
の形成をフォトレジストの除去前に、液体材料に浸漬す
ることによって得るものである。
[Means for Solving the Problems] The semiconductor device manufacturing apparatus according to the present invention forms a flattened insulating film by immersing it in a liquid material before removing the photoresist.

[作用] この発明においては、平坦化絶縁膜の形成を液体材料の
浸漬によって得るので、平坦化絶縁膜の厚膜化および均
一化が可能となり、クラックの発生を防止することがで
きる。
[Function] In the present invention, since the planarized insulating film is formed by immersion in a liquid material, the planarized insulating film can be made thicker and more uniform, and cracks can be prevented from occurring.

[発明の実施例] 第1図はこの発明の一実施例による半導体装置の製造工
程の主要部を示す断面図である。
[Embodiment of the Invention] FIG. 1 is a sectional view showing the main part of the manufacturing process of a semiconductor device according to an embodiment of the invention.

図中、符号1〜5は、従来技術と同一、または相当部分
である。
In the figure, numerals 1 to 5 are the same or equivalent parts as in the prior art.

第1図(a)および(b)は従来技術を示す第2図(a
)および(b)と同一工程部を示し、ゲート電極2をフ
ォトレジスト3をマスクとしてエツチングしたところで
ある。
Figures 1(a) and (b) show the prior art; Figure 2(a) shows the prior art.
) and (b), the gate electrode 2 is etched using the photoresist 3 as a mask.

次にエツチングされたゲート電極2をフォトレジスト3
とともに、たとえばSOG等の液体祠料中に浸13して
平坦化絶縁膜4を形成し、熱処理を行なう(第1図(C
)参照)。さらに、フォトレジストを除去して平坦化絶
縁膜4を平坦化(第1図(d)参照)した後、PSGま
たはBPSG等の絶縁膜5をたとえばCVD法による堆
積により形成させ、熱処理を施した後平坦化させる(第
1図(e)参照)。
Next, the etched gate electrode 2 is covered with a photoresist 3.
At the same time, a flattened insulating film 4 is formed by dipping 13 in a liquid abrasive such as SOG, and heat treatment is performed (see FIG. 1 (C).
)reference). Furthermore, after removing the photoresist and planarizing the planarizing insulating film 4 (see FIG. 1(d)), an insulating film 5 of PSG or BPSG was formed by depositing, for example, by a CVD method, and heat treatment was performed. After that, it is flattened (see FIG. 1(e)).

ところで、上記実施例では半導体装置における絶縁膜の
形成方法として述べたが、回転塗布が不具合であるよう
な他の製造方法において、この浸漬方法を用いることが
できるのは言うまでもない。
Incidentally, although the above embodiment has been described as a method for forming an insulating film in a semiconductor device, it goes without saying that this dipping method can be used in other manufacturing methods in which spin coating is inconvenient.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体装置の装造工
程の主要部を示す断面図であり、第2図は従来技術によ
る半導体装置の製造工程の主要部を示す断面図である。 第3図は従来技術の製造工程のうち、平坦化絶縁膜形成
時における拡大図である。 図中、同一符号は同一、ま
たは相当部分を示し、1はシリコン基板、2はゲート電
極、3はフォトレジスト、4は平坦化絶縁膜、5は絶縁
膜、6はクラックである。 代理9人 大岩増雄 −へ閂+Sり
FIG. 1 is a cross-sectional view showing the main part of the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the main part of the manufacturing process of a semiconductor device according to the prior art. FIG. 3 is an enlarged view of the process of forming a flattened insulating film in the conventional manufacturing process. In the drawings, the same reference numerals indicate the same or corresponding parts; 1 is a silicon substrate, 2 is a gate electrode, 3 is a photoresist, 4 is a flattening insulating film, 5 is an insulating film, and 6 is a crack. 9 substitutes Masuo Oiwa-he bolt + S-ri

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板、この上に形成される配線または電極
、およびこれらの間に形成される層間膜を有する半導体
装置の製造方法であって、前記配線または電極用の層を
前記基板上に形成する工程と、 前記配線または電極層をパターニングするために前記配
線または電極層の上にフォトレジストを形成する工程と
、 前記フォトレジストをマスクとして露出した前記配線ま
たは電極層をエッチングする工程と、エッチングされた
所望のパターンの前記配線または電極を前記フォトレジ
ストとともに液体材料に浸漬して、前記配線または電極
の間に層間絶縁膜を形成する工程と、 前記フォトレジストを除去する工程と、 前記配線または電極、ならびに前記層間絶縁膜上に絶縁
膜を形成する工程とを備えた、半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device having a semiconductor substrate, a wiring or an electrode formed on the substrate, and an interlayer film formed between these, wherein a layer for the wiring or electrode is formed on the substrate. forming a photoresist on the wiring or electrode layer in order to pattern the wiring or electrode layer; etching the exposed wiring or electrode layer using the photoresist as a mask; immersing the wires or electrodes in a desired pattern together with the photoresist in a liquid material to form an interlayer insulating film between the wires or electrodes; removing the photoresist; A method for manufacturing a semiconductor device, comprising an electrode and a step of forming an insulating film on the interlayer insulating film.
(2)前記液体材料はスピン・オン・グラス(Spin
OnGlass)であることを特徴とする、特許請求の
範囲第1項記載の半導体装置の製造方法。
(2) The liquid material is spin-on glass (Spin-on glass).
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is manufactured using a semiconductor device (OnGlass).
(3)前記液体材料はポリイミドであることを特徴とす
る、特許請求の範囲第1項記載の半導体装置の製造方法
(3) The method for manufacturing a semiconductor device according to claim 1, wherein the liquid material is polyimide.
JP16711586A 1986-07-15 1986-07-15 Manufacture of semiconductor device Pending JPS6321850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16711586A JPS6321850A (en) 1986-07-15 1986-07-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16711586A JPS6321850A (en) 1986-07-15 1986-07-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6321850A true JPS6321850A (en) 1988-01-29

Family

ID=15843715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16711586A Pending JPS6321850A (en) 1986-07-15 1986-07-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6321850A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0235756A (en) * 1988-07-26 1990-02-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5444023A (en) * 1993-01-11 1995-08-22 Nec Corporation Method of fabricating a semiconductor device having a multilayer wiring structure and using a fluorine compound-containing gas

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323542A (en) * 1976-08-17 1978-03-04 Matsushita Electric Ind Co Ltd Pi ezoelectric element parts
JPS59144151A (en) * 1983-02-08 1984-08-18 Nec Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323542A (en) * 1976-08-17 1978-03-04 Matsushita Electric Ind Co Ltd Pi ezoelectric element parts
JPS59144151A (en) * 1983-02-08 1984-08-18 Nec Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0235756A (en) * 1988-07-26 1990-02-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5444023A (en) * 1993-01-11 1995-08-22 Nec Corporation Method of fabricating a semiconductor device having a multilayer wiring structure and using a fluorine compound-containing gas

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