JPH0778816A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0778816A
JPH0778816A JP16124293A JP16124293A JPH0778816A JP H0778816 A JPH0778816 A JP H0778816A JP 16124293 A JP16124293 A JP 16124293A JP 16124293 A JP16124293 A JP 16124293A JP H0778816 A JPH0778816 A JP H0778816A
Authority
JP
Japan
Prior art keywords
film
sog
substrate
sog film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16124293A
Other languages
Japanese (ja)
Inventor
So Sakairi
入 宗 坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP16124293A priority Critical patent/JPH0778816A/en
Publication of JPH0778816A publication Critical patent/JPH0778816A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To uniform the quality of an SOG film, and reduce a part where film is locally weak on a step-difference or the like, by simultaneously performing the etch-back and the heat treatment of an SOG film. CONSTITUTION:SOG coating solution is spread on a substrate 4 provided with wiring layers 1a, 1b, and a P-SiO2 layer insulating film 3 covering the whole part of the wiring layers 1a, 1b and step-difference part 2a-2c, and an SOG coating film 5 is formed. Some amount of organic solvent in the SOG coating film 5 is evaporated by prebaking. The substrate 4 is heat-treated in a low pressure reaction vessel, and etching gas is supplied. The SOG film is subjected to etch-back process by plasma generated by applying high frequency to the etching gas. The SOG film 7 is left in the manner in which recessed parts 6a-6c on the step-difference parts 2a-2c are filled with the SOG film 7, and the superflous SOG film 7 is eliminated. A flattened interlayer insulating film 8 is formed of the P-SiO2 layer insulating film 3 and the SOG film 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に簡便かつ短時間の工程で、膜質が均一で平
坦なSOG膜を含む層間絶縁膜を有する半導体装置を得
ることができる方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for obtaining a semiconductor device having an interlayer insulating film including a flat SOG film having a uniform film quality by a simple and short process. Regarding

【0002】[0002]

【従来の技術】一般に、半導体装置における配線の信頼
性を確保するために、配線間の層間絶縁膜を平坦化する
技術が必要となる。特に、近年の配線の多層化、複雑化
の進行に伴って、配線の信頼性を確保するために、層間
絶縁膜の平坦化技術は、重要な技術となっている。この
層間絶縁膜の平坦化技術として、シラノール系化合物を
有機溶剤に溶解してなる塗布液を、スピン塗布法によっ
て、配線層、SiO2 層間絶縁膜等が形設された基板上
に塗布した後、プリベークにより有機溶剤を蒸発させ、
2 、空気等の雰囲気中、400〜450℃の温度で熱
処理しシラノール系化合物をガラス化してSOG膜を形
成する方法がある。このSOG膜は、液状の塗布液をス
ピン塗布して形成するため、凸部に薄く、凹部に厚く形
成されるという特性を有するため、層間絶縁膜の平坦化
には適している。しかしながら、SOG膜は吸湿しやす
く、熱処理時の脱ガス量も多い問題がある。そのため、
SOG膜を層間絶縁膜の一部として用いる場合、ビアホ
ール等の側壁が露出しないようにエッチバックを行な
い、配線上の余剰SOGを除去するという方法が採用さ
れている。
2. Description of the Related Art Generally, in order to secure reliability of wiring in a semiconductor device, a technique for flattening an interlayer insulating film between wirings is required. In particular, with the progress of multilayering and complexity of wiring in recent years, a technique for planarizing an interlayer insulating film has become an important technique in order to secure reliability of the wiring. As a flattening technique for the interlayer insulating film, a coating solution obtained by dissolving a silanol compound in an organic solvent is applied by spin coating on a substrate on which a wiring layer, a SiO 2 interlayer insulating film, etc. are formed. , Evaporate the organic solvent by pre-baking,
There is a method of forming an SOG film by vitrifying a silanol compound by heat treatment at a temperature of 400 to 450 ° C. in an atmosphere of N 2 , air or the like. Since this SOG film is formed by spin-coating a liquid coating solution, it has characteristics that it is formed thin in the convex portion and thick in the concave portion, and is therefore suitable for flattening the interlayer insulating film. However, the SOG film has a problem that it tends to absorb moisture and the amount of degassing during heat treatment is large. for that reason,
When the SOG film is used as a part of the interlayer insulating film, a method is adopted in which etching back is performed so that the sidewalls of via holes and the like are not exposed and excess SOG on the wiring is removed.

【0003】[0003]

【発明が解決しようとする課題】しかし、従来のSOG
膜の形成方法では、400〜450℃での熱処理が2〜
3時間もの長時間を要し、さらに、その後、SOG膜の
エッチバック処理を行なうため、平坦な層間絶縁膜を形
成するためには非常に多くの時間を必要とする。
[Problems to be Solved by the Invention] However, the conventional SOG
In the film forming method, heat treatment at 400 to 450 ° C. is 2 to
It takes a long time of 3 hours, and since the SOG film is etched back thereafter, it takes a very long time to form a flat interlayer insulating film.

【0004】また、従来のN2 、空気等の雰囲気中で行
なう熱処理においては、段差部などに溜まったSOG膜
の膜質に不均一な部分が生じ、脱ガス等によって、得ら
れる半導体装置の信頼性が低下する原因となるという問
題があった。
Moreover, the conventional N 2, in the heat treatment performed in an atmosphere of such air, uneven portions occurs in the film quality of the accumulated SOG film such as stepped portion, by degassing, etc., reliability of the semiconductor device obtained There is a problem that it causes the deterioration of sex.

【0005】そこで本発明の目的は、簡便かつ短時間の
工程で、膜質が均一で平坦なSOG膜を含む層間絶縁膜
を有する半導体装置を得ることができる方法を提供する
ことにある。
Therefore, an object of the present invention is to provide a method capable of obtaining a semiconductor device having an interlayer insulating film including a flat SOG film having a uniform film quality by a simple and short-time process.

【0006】[0006]

【課題を解決するための手段】前記課題を解決するため
に、本発明は、SOG膜を含む層間絶縁膜を有する半導
体装置の製造方法であって、基板上にSOG膜を形成し
てプリベークする工程と、減圧された反応容器におい
て、該基板を加熱して熱処理するとともに、反応容器内
にエッチングガスを供給し、該エッチングガスに高周波
を印加して発生するプラズマによってSOG膜のエッチ
バック処理を同時に行なう工程を含む半導体装置の製造
方法を提供するものである。
In order to solve the above problems, the present invention is a method of manufacturing a semiconductor device having an interlayer insulating film including an SOG film, wherein an SOG film is formed on a substrate and prebaked. In the process and in a depressurized reaction container, the substrate is heated and heat-treated, an etching gas is supplied into the reaction container, and an SOG film is etched back by plasma generated by applying a high frequency to the etching gas. The present invention provides a method for manufacturing a semiconductor device including steps to be performed simultaneously.

【0007】以下、本発明の半導体装置の製造方法(以
下、「本発明の方法」という)について、半導体装置の
基板上に形成された配線層の上に平坦な層間絶縁層を形
成する工程を例にとり、この工程を示す図1にしたがっ
て、詳細に説明する。
Hereinafter, in the method of manufacturing a semiconductor device of the present invention (hereinafter referred to as the “method of the present invention”), a step of forming a flat interlayer insulating layer on a wiring layer formed on a substrate of the semiconductor device will be described. As an example, the process will be described in detail with reference to FIG. 1.

【0008】この図1に示す工程において、まず、図1
(a)に示すように、配線層1a,1bと、該配線層1
a,1bおよび段差部2a,2b,2cの全面を被覆す
るP−SiO2 層間絶縁層3とを有する基板4に、スピ
ンコート法により、SOG塗布液を塗布してSOG塗膜
5を形成する。
In the process shown in FIG. 1, first, as shown in FIG.
As shown in (a), the wiring layers 1a and 1b and the wiring layer 1
The SOG coating liquid is applied to the substrate 4 having the P-SiO 2 interlayer insulating layer 3 covering the entire surfaces a, 1b and the step portions 2a, 2b, 2c by the spin coating method to form the SOG coating film 5. .

【0009】スピンコート法によるSOG塗布液の塗布
は、特に制限されず、常法にしたがって、行なうことが
できる。SOG塗布液の調製は、特に制限されず、常法
に従って、行うことができる。用いられるシラノール系
化合物としては、例えば、モノメチルシラノール、ジメ
チルシラノール等が挙げられ、また、用いられる有機溶
剤としては、例えば、アルコール類、エステル類、ケト
ン類等が挙げられるが、本発明はこれに制限されない。
The application of the SOG coating solution by the spin coating method is not particularly limited and can be performed according to a conventional method. The preparation of the SOG coating liquid is not particularly limited and can be performed according to a conventional method. Examples of silanol compounds used include monomethylsilanol, dimethylsilanol, and the like, and examples of organic solvents used include alcohols, esters, ketones, and the like, but the present invention is not limited thereto. Not limited.

【0010】また、SOG塗膜の膜厚は、SOG塗布液
の種類、下地段差等に応じて適宜調整される。通常、無
機SOGを用いる場合、0.1〜0.3μm程度であ
り、有機SOGを用いる場合には、0.3〜0.6μm
程度であるのが好ましい。
Further, the film thickness of the SOG coating film is appropriately adjusted according to the type of the SOG coating liquid, the step difference of the base and the like. Usually, it is about 0.1 to 0.3 μm when using an inorganic SOG, and 0.3 to 0.6 μm when using an organic SOG.
It is preferably about the same.

【0011】次に、プリベークを行い、SOG塗膜中の
有機溶剤をある程度蒸発させる。このプリベークは、例
えば、ホットプレート等を用いて、100〜250℃程
度の温度で基板を加熱することによって行なうことがで
きる。
Next, prebaking is performed to evaporate the organic solvent in the SOG coating film to some extent. This prebaking can be performed by heating the substrate at a temperature of about 100 to 250 ° C. using a hot plate or the like.

【0012】次いで、減圧された反応容器において、基
板を加熱して熱処理するとともに、エッチングガスを供
給し、該エッチングガスに高周波を印加して発生するプ
ラズマによってSOG膜のエッチバック処理を行い、図
1(b)に示すとおり、段差部2a,2b,2cの上部
の凹部6a,6b,6c内がSOG膜7で充填されるよ
うに、SOG膜7を残して、余剰のSOG膜が除去さ
れ、P−SiO2 層間絶縁層3とSOG膜7とで、平坦
化された層間絶縁膜8が形成される。配線層1aおよび
1bの上部のP−SiO2 層間絶縁層3aおよび3bの
上面9a,9bは、図1(b)に示すとおりに露出され
ていてもよいし、SOG膜に被覆されていてもよい。
Then, in a depressurized reaction vessel, the substrate is heated to be heat-treated, an etching gas is supplied, and an SOG film is etched back by plasma generated by applying a high frequency to the etching gas. As shown in FIG. 1 (b), the excess SOG film is removed leaving the SOG film 7 so that the recesses 6a, 6b, 6c above the stepped portions 2a, 2b, 2c are filled with the SOG film 7. , P-SiO 2 interlayer insulating layer 3 and the SOG film 7 form a planarized interlayer insulating film 8. The upper surfaces 9a and 9b of the P-SiO 2 interlayer insulating layers 3a and 3b above the wiring layers 1a and 1b may be exposed as shown in FIG. 1B, or may be covered with the SOG film. Good.

【0013】以上、本発明の方法の一実施態様である図
1(a)および(b)に示す工程に基づいて、本発明の
方法を説明したが、本発明の方法は、この図1(a)お
よび(b)に示す工程に限定されず、層間絶縁膜を有す
る各種の半導体装置の製造に適用できることは勿論であ
る。例えば、メモリまたはロジック素子を有する多層メ
タル配線のバイポーラ半導体装置、MOS半導体装置等
に適用できる。
The method of the present invention has been described above based on the steps shown in FIGS. 1 (a) and 1 (b), which are one embodiment of the method of the present invention. It is needless to say that the present invention is not limited to the steps shown in a) and (b) and can be applied to the manufacture of various semiconductor devices having an interlayer insulating film. For example, it can be applied to a bipolar semiconductor device having a multi-layer metal wiring having a memory or a logic element, a MOS semiconductor device, and the like.

【0014】本発明の方法において、基板の熱処理およ
びエッチバック処理を行なう反応容器は、特に制限され
ず、熱処理およびエッチバック処理を同時に行なうこと
ができる装置であれば、いずれの装置を用いてもよい。
この反応容器の具体例として、図2および図3に概略断
面図を示す装置が挙げられる。
In the method of the present invention, the reaction vessel for carrying out the heat treatment and the etchback treatment of the substrate is not particularly limited, and any equipment can be used as long as it can perform the heat treatment and the etchback treatment at the same time. Good.
As a specific example of this reaction container, an apparatus whose schematic sectional views are shown in FIGS. 2 and 3 can be mentioned.

【0015】図2に示す装置は、いわゆるバッチ式プラ
ズマエッチング装置であり、反応容器の外側を構成する
アウターチューブ11と、該アウターチューブ11の内
側に配設されたインナーチューブ12と、多数の基板1
3を水平に保持し、回転台座14により回転可能に支持
された基板支持ポート15と、ガス供給口16から導入
されるエッチングガスを基板13に供給するインジェク
ター17とを有するものである。また、アウターチュー
ブ11の外側には、高周波電源18に接続された、少な
くとも一対の高周波発生用電極19と、基板を加熱する
ためのヒーター20が配設され、さらに、排気孔21に
連結された減圧装置(図示せず)によってアウターチュ
ーブ11内部を排気して、減圧状態にすることができる
ように構成されている。
The apparatus shown in FIG. 2 is a so-called batch type plasma etching apparatus, and comprises an outer tube 11 constituting the outside of the reaction vessel, an inner tube 12 arranged inside the outer tube 11, and a large number of substrates. 1
3 is held horizontally, and has a substrate support port 15 rotatably supported by a rotation base 14, and an injector 17 for supplying the substrate 13 with an etching gas introduced from a gas supply port 16. Further, on the outer side of the outer tube 11, at least a pair of high-frequency generating electrodes 19 connected to a high-frequency power source 18 and a heater 20 for heating the substrate are arranged, and further connected to an exhaust hole 21. The inside of the outer tube 11 is evacuated by a decompression device (not shown) so that the outer tube 11 can be decompressed.

【0016】この図2に示す装置においては、基板13
を基板支持ポート15に載置した後、減圧装置によって
アウターチューブ11内の雰囲気を排気して減圧し、回
転台座14によって矢印Aの方向に回転されている基板
13をヒーター20によって加熱するとともに、インジ
ェクター17からエッチングガスを供給すると同時に、
高周波電源18によって高周波発生用電極19から高周
波を印加して、エッチングガスをプラズマ化して、基板
13のSOG膜をエッチバック処理することができる。
In the apparatus shown in FIG. 2, the substrate 13
After mounting the substrate on the substrate support port 15, the atmosphere inside the outer tube 11 is exhausted by a decompression device to reduce the pressure, and the substrate 13 rotated in the direction of the arrow A by the rotating pedestal 14 is heated by the heater 20. At the same time as supplying the etching gas from the injector 17,
A high frequency power can be applied from the high frequency power generation electrode 19 by the high frequency power supply 18 to turn the etching gas into plasma to etch back the SOG film on the substrate 13.

【0017】また、図3に示す装置は、いわゆる枚葉式
プラズマエッチング装置であり、反応容器の本体31
と、該本体31の上部に配設されたガス導入口32と、
本体31の下部に配設された排気孔33とを有し、本体
内部31には、基板34が載置される高周波発生用の下
部電極35と、上部電極36とが配設され、下部電極3
5と上部電極36とは、高周波電源37に接続されてな
るものである。また、下部電極35の下側には基板34
を加熱するためのヒーター38が配設され、上部電極3
6には、ガス導入口32から導入されるエッチングガス
を基板13上に供給するためのガス供給孔39が穿設さ
れている。
The apparatus shown in FIG. 3 is a so-called single-wafer type plasma etching apparatus, which is a main body 31 of the reaction vessel.
And a gas introduction port 32 arranged on the upper part of the main body 31,
The main body 31 has an exhaust hole 33 disposed below the main body 31. Inside the main body 31, a lower electrode 35 for generating a high frequency on which a substrate 34 is mounted and an upper electrode 36 are disposed. Three
5 and the upper electrode 36 are connected to a high frequency power source 37. The substrate 34 is provided below the lower electrode 35.
A heater 38 for heating the upper electrode 3 is provided.
6 is provided with a gas supply hole 39 for supplying the etching gas introduced from the gas introduction port 32 onto the substrate 13.

【0018】この図3に示す装置においては、基板34
を下部電極35の上に載置した後、排気孔33に連結さ
れた減圧装置(図示せず)によって反応容器の本体31
内を排気して減圧し、ヒーター38によって基板34を
加熱するとともに、ガス導入口32から導入されたエッ
チングガスを、ガス供給孔39を通じて基板34上に供
給すると同時に、高周波電源37によって上部電極36
と下部電極35から高周波を印加して、エッチングガス
をプラズマ化して基板34をエッチバック処理すること
ができる。
In the apparatus shown in FIG. 3, the substrate 34
Is placed on the lower electrode 35, and then the main body 31 of the reaction container is removed by a pressure reducing device (not shown) connected to the exhaust hole 33.
The inside is evacuated to reduce the pressure, the substrate 34 is heated by the heater 38, and the etching gas introduced from the gas inlet 32 is supplied onto the substrate 34 through the gas supply hole 39, and at the same time, the high frequency power supply 37 is used to supply the upper electrode 36.
A high frequency can be applied from the lower electrode 35 to turn the etching gas into plasma to etch back the substrate 34.

【0019】本発明の方法において、減圧によって反応
容器内の圧力は、通常、0.1〜0.8Torr程度に
調整される。
In the method of the present invention, the pressure inside the reaction vessel is usually adjusted to about 0.1 to 0.8 Torr by reducing the pressure.

【0020】本発明の方法において、基板の熱処理にお
ける加熱温度は、通常、300〜450℃程度であり、
Al配線への熱ストレスを少なくするという点で、好ま
しくは350〜400℃程度である。また、このとき、
急激に高温で加熱すると、厚膜化したSOG膜の場合、
クラックが発生しやすくなり、また、図4に各温度にお
けるSOG膜のエッチング速度を示すとおり、エッチン
グ速度も急激に変動するため、エッチング量の制御が難
しくなる。また、SOG膜の膜質を均一にする上でも、
急激に加熱することは良くない。そこで、昇温は最低で
も2ステップで行なうことが望ましい。まず、第1ステ
ップで200℃前後の温度で一定に保ち、SOG膜の乾
燥と、配線上の余剰SOG膜を8割程度除去する。次
に、400℃程度まで昇温し、下地の酸化膜とエッチン
グ速度が近づいた状態で、残りの余剰SOG膜をエッチ
ングするように調整すれと、好ましい。
In the method of the present invention, the heating temperature in the heat treatment of the substrate is usually about 300 to 450 ° C.,
The temperature is preferably about 350 to 400 ° C. from the viewpoint of reducing thermal stress on the Al wiring. Also, at this time,
When heated rapidly at high temperature, in the case of thickened SOG film,
Cracks are likely to occur, and as shown in FIG. 4 showing the etching rate of the SOG film at each temperature, the etching rate also changes rapidly, making it difficult to control the etching amount. Moreover, in order to make the quality of the SOG film uniform,
It is not good to heat rapidly. Therefore, it is desirable to raise the temperature in at least two steps. First, in the first step, the temperature is kept constant at around 200 ° C., the SOG film is dried, and the excess SOG film on the wiring is removed by about 80%. Next, it is preferable that the temperature is raised to about 400 ° C. and the remaining excess SOG film is etched while the etching rate is close to that of the underlying oxide film.

【0021】エッチバック処理に用いられるエッチング
ガスは、特に制限されず、この種の処理に用いられる常
用のものでよい。例えば、CF4 +O2 ガス、CF4
CHF3 ガス、NF3 ガス等が挙げられる。特に、CF
4 +O2 ガス、CF4 +CHF3 ガス等のCF4 系のエ
ッチングガスでSOG膜のエッチバック処理を行なう
と、エッチバック後のSOG膜表面が疎水性となり、エ
ッチバック後に上層絶縁膜を成膜する場合、密着力に問
題が生じることがある。そこで、SOG膜のエッチバッ
ク終了後にエッチングガスをO2 のみとしO2 プラズマ
によりエッチバック後の表面改質を行なうと有効であ
る。
The etching gas used in the etch-back process is not particularly limited and may be a conventional gas used in this type of process. For example, CF 4 + O 2 gas, CF 4 +
Examples include CHF 3 gas and NF 3 gas. Especially CF
When the SOG film is etched back with a CF 4 -based etching gas such as 4 + O 2 gas or CF 4 + CHF 3 gas, the SOG film surface after the etching back becomes hydrophobic, and the upper insulating film is formed after the etching back. If so, there may be a problem in adhesion. Therefore, it is effective to perform the surface modification after the etch back with O 2 plasma by using only O 2 as the etching gas after the etching back of the SOG film is completed.

【0022】本発明の方法によって得られるSOG膜
は、通常のN2 もしくはAir雰囲気中で熱処理したも
のと比べよりち密で膜中深くまで均一な膜質となる。
The SOG film obtained by the method of the present invention is denser and has a uniform film quality deep inside the film, as compared with the SOG film heat-treated in a normal N 2 or air atmosphere.

【0023】[0023]

【発明の効果】本発明の方法によれば、SOG膜のエッ
チバックと熱処理とを同時に行なうことにより、SOG
膜の膜質が均一となり、段差部などで局所的に膜質の弱
い(エッチバックが速い)部分が少なくなる。また、エ
ッチバックと熱処理とを同時に行なうことにより工程も
大幅に短縮することができる。さらにエッチバック時の
昇温ステップの工夫によりSOG膜を厚膜化した時のク
ラック発生の軽減可能となり、半導体装置の信頼性向上
につながる利点もある。
According to the method of the present invention, the SOG film is etched back and heat-treated at the same time, and
The quality of the film becomes uniform, and the number of locally weak parts (fast etchback) such as stepped parts decreases. Further, the steps can be significantly shortened by simultaneously performing the etch back and the heat treatment. Further, by devising a temperature raising step at the time of etching back, it is possible to reduce the occurrence of cracks when the SOG film is made thicker, which has an advantage of improving the reliability of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の方法の一実施態様における主要工程
を説明する概略断面図。
FIG. 1 is a schematic cross-sectional view illustrating main steps in an embodiment of the method of the present invention.

【図2】 バッチ式プラズマエッチング装置の一例の模
式断面図。
FIG. 2 is a schematic sectional view of an example of a batch type plasma etching apparatus.

【図3】 枚葉式プラズマエッチング装置の一例の模式
断面図。
FIG. 3 is a schematic cross-sectional view of an example of a single-wafer plasma etching apparatus.

【図4】 キュア温度とエッチング速度の関係を示す
図。
FIG. 4 is a diagram showing a relationship between a curing temperature and an etching rate.

【符号の説明】[Explanation of symbols]

1a,1b 配線層 2a,2b,2c 段差部 3 P−SiO2 層間絶縁層 4 基板 5 SOG塗膜 6a,6b,6c 凹部 7 SOG膜 8 層間絶縁膜 9a,9b P−SIO2 層間絶縁層の上面 11 アウターチューブ 12 インナーチューブ 13 基板 14 回転台座 15 基板支持ポート 16 ガス供給口 17 インジェクター 18 高周波電源 19 高周波発生用電極 20 ヒーター 21 排気孔 31 反応容器の本体 32 ガス導入口 33 排気孔 34 基板 35 下部電極 36 上部電極 37 高周波電源 38 ヒーター 39 ガス供給孔1a, 1b wiring layers 2a, 2b, 2c stepped portion 3 P-SiO 2 interlayer insulating layer 4 substrate 5 SOG coating 6a, 6b, 6c recess 7 SOG film 8 interlayer insulating film 9a, the 9b P-SIO 2 interlayer insulation layer Upper surface 11 Outer tube 12 Inner tube 13 Substrate 14 Rotating pedestal 15 Substrate supporting port 16 Gas supply port 17 Injector 18 High frequency power source 19 High frequency generating electrode 20 Heater 21 Exhaust hole 31 Reaction vessel body 32 Gas inlet 33 Exhaust hole 34 Substrate 35 Lower electrode 36 Upper electrode 37 High frequency power supply 38 Heater 39 Gas supply hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】SOG膜を含む層間絶縁膜を有する半導体
装置の製造方法であって、基板上にSOG膜を形成して
プリベークする工程と、減圧された反応容器において、
該基板を加熱して熱処理するとともに、反応容器内にエ
ッチングガスを供給し、該エッチングガスに高周波を印
加して発生するプラズマによってSOG膜のエッチバッ
ク処理を同時に行なう工程を含む半導体装置の製造方
法。
1. A method of manufacturing a semiconductor device having an interlayer insulating film including an SOG film, comprising the steps of forming an SOG film on a substrate and pre-baking, and using a depressurized reaction container,
A method of manufacturing a semiconductor device, including the steps of heating the substrate for heat treatment, supplying an etching gas into a reaction vessel, and simultaneously performing an etchback process of an SOG film by plasma generated by applying a high frequency to the etching gas. .
JP16124293A 1993-06-30 1993-06-30 Manufacture of semiconductor device Pending JPH0778816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16124293A JPH0778816A (en) 1993-06-30 1993-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16124293A JPH0778816A (en) 1993-06-30 1993-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0778816A true JPH0778816A (en) 1995-03-20

Family

ID=15731356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16124293A Pending JPH0778816A (en) 1993-06-30 1993-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0778816A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330301A (en) * 1995-05-22 1996-12-13 Hyundai Electron Ind Co Ltd Formation of sog film of semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330301A (en) * 1995-05-22 1996-12-13 Hyundai Electron Ind Co Ltd Formation of sog film of semiconductor element

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