JP2557916B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2557916B2
JP2557916B2 JP62299926A JP29992687A JP2557916B2 JP 2557916 B2 JP2557916 B2 JP 2557916B2 JP 62299926 A JP62299926 A JP 62299926A JP 29992687 A JP29992687 A JP 29992687A JP 2557916 B2 JP2557916 B2 JP 2557916B2
Authority
JP
Japan
Prior art keywords
coating film
film
semiconductor device
plasma
coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62299926A
Other languages
Japanese (ja)
Other versions
JPH01143321A (en
Inventor
成彦 梶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
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Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP62299926A priority Critical patent/JP2557916B2/en
Publication of JPH01143321A publication Critical patent/JPH01143321A/en
Application granted granted Critical
Publication of JP2557916B2 publication Critical patent/JP2557916B2/en
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Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、半導体装置の製造方法に係わり、特に基板
に形成された配線等の段差部を被覆する絶縁膜の平坦化
の方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to planarizing an insulating film covering a stepped portion such as wiring formed on a substrate. Regarding the method.

(従来の技術) 半導体装置の製造にあたり、通常、半導体素子あるい
は配線上には他の領域と絶縁性を保つために絶縁膜を形
成する。この場合、前記配線や半導体素子は通常、段差
を有しているので、前記配線や半導体素子を被覆した絶
縁膜表面は凹凸となる。前記絶縁膜の凹凸のうち特に角
部では、他の部分に比べてストレスが多くかかり、この
ため前記絶縁膜にクラックが生じる等、絶縁性を保てな
くなるという問題が生じることがある。
(Prior Art) In manufacturing a semiconductor device, an insulating film is usually formed on a semiconductor element or a wiring in order to maintain an insulating property from other regions. In this case, since the wiring or the semiconductor element usually has a step, the surface of the insulating film covering the wiring or the semiconductor element becomes uneven. Particularly in the corners of the unevenness of the insulating film, more stress is applied than in other parts, and therefore, there is a problem that the insulating property cannot be maintained, such as cracks in the insulating film.

特に、この問題は、近年半導体装置の大容量化・高集
積化に伴い用いられる多層配線構造のものにおいて顕著
である。つまり、前記多層配線構造の半導体装置を形成
する場合、配線層と層間絶縁膜を繰り返し積層して形成
するがその繰り返しによって段差は急峻となり、前記絶
縁膜に物理的なストレスが多くかかる。又、場合によっ
ては配線の方に断線の方に断線を生じることもある。
In particular, this problem is remarkable in the multi-layer wiring structure used in recent years with the increase in capacity and integration of semiconductor devices. That is, in the case of forming the semiconductor device having the multilayer wiring structure, the wiring layer and the interlayer insulating film are repeatedly laminated, but the repetition causes a steep step, so that the insulating film is subjected to many physical stresses. In some cases, the wiring may be broken and the wiring may be broken.

前述した問題を生じないように凹凸のある前記絶縁膜
表面を平坦化し、前記絶縁膜に物理的なストレスが発生
しないようにすることが行なわれている。前記平坦化の
方法としては、レジストエッチングバック法、バイアス
スパッタ法が主に行なわれている。しかしながら、前者
は半導体素子の微細化が進行するにつれて、プロセスの
制御が困難となっており、後者では素子に損傷を与えて
しまうという欠点がある。
In order to avoid the above-mentioned problems, the surface of the insulating film having irregularities is flattened so that physical stress does not occur in the insulating film. A resist etching back method and a bias sputtering method are mainly used as the planarization method. However, the former has a drawback that the process control becomes difficult as the miniaturization of the semiconductor device progresses, and the latter damages the device.

そこで、上記2つの方法とは別の方法として液体の流
動性を用いた塗布法により、前記段差を平坦化する方法
が有力となってきた。
Therefore, as a method different from the above two methods, a method of flattening the step by a coating method using the fluidity of the liquid has become effective.

前記塗布法により形成される塗布膜は配線や半導体素
子を絶縁膜で被覆した後、前記絶縁膜上に硅素化合物を
溶媒中に溶解させた塗布膜形成溶液等を回転塗布し、そ
の後熱処理により溶媒を揮発させた上、膜の硬化を行な
って形成している。
The coating film formed by the coating method is formed by coating the wiring or the semiconductor element with an insulating film, and then spin coating a coating film forming solution or the like in which a silicon compound is dissolved in a solvent on the insulating film, and then applying a solvent by heat treatment. Is vaporized and the film is cured to form the film.

しかしながら、前記熱処理は半導体素子等への影響を
考えると高温で行なうことはできず溶媒は、十分には揮
発していない。そのため塗布膜中に含まれる水分がエッ
チングプロセスで使用されたハロゲンガスの残留元素等
と反応して配線あるいは半導体素子を腐食させる等、耐
湿性に問題がある。このため、単独で層間絶縁膜として
用いず、例えばプラズマCVD絶縁膜/塗布膜/プラズマC
VD絶縁膜等塗布膜を他の絶縁膜で挟み込む積層構造を形
成することが多い。
However, the heat treatment cannot be performed at a high temperature in consideration of the influence on the semiconductor element and the like, and the solvent is not sufficiently volatilized. Therefore, there is a problem in moisture resistance such that moisture contained in the coating film reacts with residual elements of halogen gas used in the etching process to corrode wiring or semiconductor elements. Therefore, instead of using it alone as an interlayer insulating film, for example, plasma CVD insulating film / coating film / plasma C
In many cases, a laminated structure is formed in which a coating film such as a VD insulating film is sandwiched between other insulating films.

しかしながら基板上の配線層等と、絶縁膜及び塗布膜
の熱膨張係数(α)はそれぞれ異なり、特に前記配線層
がアルミニウム合金で、絶縁膜がプラズマCVDによるSiO
2膜の場合、αは2ケタ異なる。従って、積層構造の層
間絶縁膜を形成しても塗布膜の硬化のための熱処理時に
配線層と絶縁膜の間で熱応力が発生し、前記絶縁膜にク
ラックが生じる場合があり問題となっている。
However, the coefficient of thermal expansion (α) of the wiring layer on the substrate is different from that of the insulating film and the coating film. In particular, the wiring layer is made of aluminum alloy, and the insulating film is made by plasma CVD CVD
In the case of two membranes, α differs by two digits. Therefore, even if the interlayer insulating film having a laminated structure is formed, thermal stress may occur between the wiring layer and the insulating film during the heat treatment for curing the coating film, which may cause a crack in the insulating film, which is a problem. There is.

(発明が解決しようとする問題点) 本発明は上記した従来の配線あるいは半導体素子を絶
縁膜で被覆する方法では、前記絶縁膜の凹凸を平坦化
し、かつ、前記絶縁膜へのクラックの発生が生じてしま
うという問題を鑑みてなされたものである。すなわち、
本発明は配線層等の段差部を被覆する絶縁膜とこの絶縁
膜上に形成される塗布膜を低温で形成し、前記絶縁膜へ
のクラックの発生が生じないようにする半導体装置の製
造方法を提供することを目的とする。
(Problems to be Solved by the Invention) In the present invention, in the above-described conventional method of coating a wiring or a semiconductor element with an insulating film, the unevenness of the insulating film is flattened, and a crack is generated in the insulating film. This is done in view of the problem that it will occur. That is,
The present invention relates to a method for manufacturing a semiconductor device, in which an insulating film for covering a stepped portion such as a wiring layer and a coating film formed on the insulating film are formed at a low temperature to prevent cracks from occurring in the insulating film. The purpose is to provide.

〔発明の構成〕[Structure of Invention]

(問題点を解決するための手段) 本発明は上記目的を達成するために表面に段差部を有
する基板上に少なくとも前記段差部を被覆する第1の絶
縁層を形成する工程と、前記第1の絶縁層上に塗布膜を
形成し、前記第1の絶縁膜の形成された基板表面を平坦
化する工程と、その後、少なくとも前記塗布膜をプラズ
マ中にさらす工程と、前記平坦化された塗布膜上に第2
の絶縁層を形成する工程とを含む半導体装置の製造方法
を提供する。
(Means for Solving the Problems) In order to achieve the above object, the present invention comprises a step of forming a first insulating layer covering at least the stepped portion on a substrate having a stepped portion on the surface, and the first step. Forming a coating film on the insulating layer and flattening the substrate surface on which the first insulating film is formed; thereafter, exposing at least the coating film to plasma; and the flattening coating. Second on the membrane
And a step of forming an insulating layer, the method for manufacturing a semiconductor device.

(作用) 本発明により段差部を被覆した第1の絶縁層上の塗布
膜をプラズマ中にさらすことにより低温で前記絶縁膜表
面を平坦化することができ、前記第1の絶縁膜にクラッ
クを発生することはない。
(Operation) By exposing the coating film on the first insulating layer covering the step portion to the plasma according to the present invention, the surface of the insulating film can be flattened at a low temperature, and the first insulating film is cracked. It never happens.

また、塗布膜の硬化処理は低温におけるプラズマFで
反応が促進せしめることができ、耐湿性を向上せしめる
ことが可能である。
Further, in the curing treatment of the coating film, the reaction can be promoted by the plasma F at a low temperature, and the moisture resistance can be improved.

例えば、前記塗布膜がSi(OH)4等の硅素化合物の場
合、Si−OH OH−Siの間で脱水縮合反応を起こし、Si−
O−Siの網目を広げることにより前記塗布膜の硬化が進
行するとともに耐湿性を向上せしめることができる。こ
の場合の処理温度は、熱処理により硬化を行なうには40
0℃以上の加熱が必要である(この場合絶縁膜にはクラ
ックが生じる)のに対し、前記クラックを生じることな
く400℃以下の低温で行なうことができる。また、配線
にも応力が加わらないので断線が生じることはない。
For example, when the coating film is a silicon compound such as Si (OH) 4 , a dehydration condensation reaction occurs between Si--OH OH--Si, and Si--
By expanding the network of O-Si, the curing of the coating film can proceed and the moisture resistance can be improved. The processing temperature in this case is 40 for hardening by heat treatment.
While heating at 0 ° C. or higher is required (in this case, a crack is generated in the insulating film), the heating can be performed at a low temperature of 400 ° C. or lower without causing the crack. In addition, since no stress is applied to the wiring, no disconnection occurs.

これは、プラズマ中に前記塗布膜をさらすと、Si−OH
あるいはO−H結合がプラズマのエネルギーにより活性
化され反応性に富むからである。
This is because when the coating film is exposed to plasma, Si-OH
Alternatively, the O—H bond is activated by the energy of the plasma and is highly reactive.

従って、本発明によれば低温で平坦性、耐湿性の良好
な塗布膜を形成することができる。また、これにより、
絶縁層へのクラックの発生あるいは配線層の断線等を生
じることはない。
Therefore, according to the present invention, a coating film having good flatness and moisture resistance can be formed at low temperature. This also gives
There is no occurrence of cracks in the insulating layer or disconnection of the wiring layer.

(実施例) 以下、本発明の実施例について図面を用いて詳細に説
明する。第1図は、この工程断面図である。
(Example) Hereinafter, the Example of this invention is described in detail using drawing. FIG. 1 is a sectional view of this step.

先ず、第1図(a)に示すように例えば第n番目のア
ルミニウム等の配線(1)が形成された基板(6)に第
1プラズマCVD−SiO2膜(2)を形成する。次に第1図
(b)に示す様に、前記プラズマCVD−SiO2膜(2)の
形成された基板全面にシリケート系化合物を含む塗布膜
形成溶液を塗布し、その後、減圧下で塗布膜形成溶液の
溶媒を揮発させ塗布膜としてシリケート系化合物膜
(3)を基板上に残す。引続き第1図(c)に示す様に
酸素プラズマ中で硬化処理を施したシリケート系化合物
膜(3a)を形成する。ここで、シリケート系化合物膜
(3a)を形成した後、エッチングして全面により平坦性
をもたせるようにしてもよい。さらに第1図(d)に示
す様に第2プラズマCVD−SiO2膜(4)を層間絶縁膜と
して形成し、さらにその上に第1図(e)に示す様に第
(n+1)アルミニウム配線(5)を形成する。
First, as shown in FIG. 1A, a first plasma CVD-SiO 2 film (2) is formed on a substrate (6) on which a wiring (1) made of, for example, nth aluminum is formed. Next, as shown in FIG. 1 (b), a coating film forming solution containing a silicate compound is applied to the entire surface of the substrate on which the plasma CVD-SiO 2 film (2) is formed, and then the coating film is formed under reduced pressure. The solvent of the forming solution is volatilized to leave the silicate compound film (3) as a coating film on the substrate. Subsequently, as shown in FIG. 1 (c), a silicate compound film (3a) which has been subjected to a curing treatment in oxygen plasma is formed. Here, after forming the silicate-based compound film (3a), etching may be performed to make the entire surface flat. Further, as shown in FIG. 1 (d), a second plasma CVD-SiO 2 film (4) is formed as an interlayer insulating film, and further on it, as shown in FIG. 1 (e), (n + 1) th aluminum wiring. (5) is formed.

上記実施例で形成した第n番目のアルミニウム配線
(1)がアルミニウム幅2μm、スペース幅2μm、ア
ルミニウム厚1μmのラインアンドスペースパターンで
あり、第1プラズマCVD−SiO2膜(2)の膜厚0.2μmの
条件で450℃の熱処理により塗布膜(3)を硬化させた
場合、第1プラズマCVD−SiO2膜(2)に生じるクラッ
クの発生率は30%であった。その後、さらに基板温度を
室温〜300℃、酸素圧力1Torr、RFパワー800W、処理時間
60分の酸素プラズマ処理により塗布膜(3)を硬化させ
た場合、CVD−SiO2膜(2)にクラックは全く発生しな
い。
The n-th aluminum wiring (1) formed in the above embodiment is a line-and-space pattern having an aluminum width of 2 μm, a space width of 2 μm, and an aluminum thickness of 1 μm, and the first plasma CVD-SiO 2 film (2) has a film thickness of 0.2. When the coating film (3) was cured by heat treatment at 450 ° C. under the condition of μm, the crack generation rate in the first plasma CVD-SiO 2 film (2) was 30%. After that, the substrate temperature is further from room temperature to 300 ° C, oxygen pressure 1 Torr, RF power 800W, processing time
When the coating film (3) is cured by the oxygen plasma treatment for 60 minutes, no crack is generated in the CVD-SiO 2 film (2).

本発明により形成する塗布膜の膜質は、第1あるいは
第2の絶縁層との間で発生する応力の影響を抑制するた
めに膜質を極力近付けるのが望ましい。
The film quality of the coating film formed by the present invention is preferably as close as possible in order to suppress the influence of the stress generated between the coating film and the first or second insulating layer.

前記膜質の比較のため両者のエッチング速度を調べた
結果について以下説明する。
The results of investigating the etching rates of the two for comparison of the film quality will be described below.

第2図は塗布膜の硬化処理を施す際に基板温度を変化
させた時の塗布膜((A)熱処理、(B)プラズマ処
理)とプラズマCVD−SiO2膜(C)のエッチング速度を
示す特性図である。
FIG. 2 shows the etching rates of the coating film ((A) heat treatment, (B) plasma treatment) and the plasma CVD-SiO 2 film (C) when the substrate temperature was changed during the curing treatment of the coating film. It is a characteristic diagram.

ここでプラズマ処理は酸素(O2)雰囲気中で行ない、
酸素圧力1Torr、RF出力800W、処理時間60分の処理条件
である。また、プラズマCVD−SiO2膜のエッチング速度
は基板温度によらずエッチング速度はほぼ一定であり、
基板温度が300℃前後のときに両者のエッチング速度が
ほぼ同様であることがわかった。
Here, the plasma treatment is performed in an oxygen (O 2 ) atmosphere,
Oxygen pressure is 1 Torr, RF output is 800 W, and processing time is 60 minutes. Further, the etching rate of the plasma CVD-SiO 2 film is almost constant regardless of the substrate temperature,
It was found that the etching rates were almost the same when the substrate temperature was around 300 ° C.

さらに塗布膜の硬化処理後のエッチング速度を熱処理
で行った場合(A)と本発明によるプラズマ処理で行っ
た場合(B)で比較すると、例えば、プラズマ処理の30
0℃でのエッチング速度は、熱処理を600℃〜で行った場
合とほぼ同様であった。
Further, when the etching rate after the hardening treatment of the coating film is compared between the case of performing the heat treatment (A) and the case of performing the plasma treatment according to the present invention (B), for example, the plasma treatment of 30
The etching rate at 0 ° C. was almost the same as that when the heat treatment was performed at 600 ° C.

これらのことから、プラズマ処理により硬化させた塗
布膜の方が熱処理により硬化させたよりもプラズマCVD
−SiO2膜の膜質に近いことが推察される。
For these reasons, the coating film cured by plasma treatment is more likely to be plasma CVD than cured by heat treatment.
It is inferred near the quality of -SiO 2 film.

また、第2図から、プラズマ処理を施した塗布膜は同
一基板温度における通常の熱処理に比べた場合よりエッ
チング速度が遅く、膜が緻密であることがわかる。従っ
て、同一基板温度では、熱処理よりもプラズマ処理の方
が吸湿性が小さいことがわかる。
Further, it can be seen from FIG. 2 that the coating film subjected to the plasma treatment has a slower etching rate than that of the ordinary heat treatment at the same substrate temperature and the film is dense. Therefore, at the same substrate temperature, the hygroscopicity of the plasma treatment is smaller than that of the heat treatment.

このことは,塗布膜を沸騰水中に約30分浸した後、塗
布膜を加熱した時に放出される水の相対量を質量分析計
を用いて測定することにより明らかとなった。
This was clarified by immersing the coating film in boiling water for about 30 minutes and then measuring the relative amount of water released when the coating film was heated using a mass spectrometer.

すなわち、基板温度300℃、酸素圧力1Torr、RF.800
W、処理時間60分の条件で形成された塗布膜はプラズマC
VD−SiO2膜と同程度であり、熱処理により硬化せしめた
膜に比べ吸湿性は約1/10と大きく改善された。
That is, substrate temperature 300 ° C, oxygen pressure 1 Torr, RF.800
The coating film formed under the conditions of W and treatment time of 60 minutes is plasma C
It is similar to the VD-SiO 2 film, and its hygroscopicity is greatly improved to about 1/10 of that of the film cured by heat treatment.

なお、上記実施例では塗布膜を酸素プラズマにさらし
たが、窒素、アルゴン等のガスプラズマにさらしても同
様の効果が得られる。また、塗布膜形成溶液はプラズマ
にさらした時に硬化する材料であれば何でもよいが、望
しくは、シリコン(Si)と酸素(O)を含むものがよ
い。
Although the coating film was exposed to oxygen plasma in the above embodiment, the same effect can be obtained by exposing it to a gas plasma of nitrogen, argon or the like. Further, the coating film forming solution may be any material as long as it cures when exposed to plasma, but preferably contains silicon (Si) and oxygen (O).

また、前記塗布膜をプラズマにさらす直前あるいはプ
ラズマにさらしている間に基板に熱処理を加えると硬化
処理の時間を短縮でき、スループットを向上させること
ができる。
Further, if the substrate is subjected to heat treatment immediately before or during the exposure of the coating film to plasma, the curing treatment time can be shortened and the throughput can be improved.

〔発明の効果〕〔The invention's effect〕

以上述べたように本発明によれば基板の配線等の段差
部を被覆した絶縁層の表面を低温で平坦化することがで
き、プロセスにおける絶縁層あるいは、配線への影響を
抑制することができる。
As described above, according to the present invention, the surface of the insulating layer covering the stepped portion such as the wiring of the substrate can be flattened at a low temperature, and the influence on the insulating layer or the wiring in the process can be suppressed. .

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明による一実施例を示す工程断面図、第2
図は本発明の効果を説明するための特性図である。 1,5……配線、2……第1の絶縁層、3……塗布膜、4
……第2の絶縁層、6……基板。
FIG. 1 is a process sectional view showing one embodiment of the present invention, and FIG.
The figure is a characteristic diagram for explaining the effect of the present invention. 1,5 ... Wiring, 2 ... First insulating layer, 3 ... Coating film, 4
...... Second insulating layer, 6 ... Substrate.

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】表面に段差部を有する基板上に少なくとも
前記段差部を被覆する第1の絶縁層を形成する工程と、
前記第1の絶縁層上に塗布膜を形成し、前記第1の絶縁
膜の形成された基板表面を平坦化する工程と、その後、
少なくとも前記塗布膜をプラズマ中にさらす工程と、前
記平坦化された塗布膜上に第2の絶縁層を形成する工程
とを含む半導体装置の製造方法。
1. A step of forming a first insulating layer covering at least the step portion on a substrate having a step portion on the surface,
Forming a coating film on the first insulating layer and flattening the surface of the substrate on which the first insulating film is formed;
A method of manufacturing a semiconductor device, comprising: exposing at least the coating film to plasma; and forming a second insulating layer on the planarized coating film.
【請求項2】前記基板表面の段差部は、配線パターンあ
るいは半導体素子の形成された領域であり、前記領域上
に第1の絶縁膜を形成することを特徴とする特許請求の
範囲第1項記載の半導体装置の製造方法。
2. The stepped portion on the surface of the substrate is a region where a wiring pattern or a semiconductor element is formed, and a first insulating film is formed on the region. A method for manufacturing a semiconductor device as described above.
【請求項3】前記塗布膜は塗布膜形成溶液をスピンコー
ト法により前記第1の絶縁層上に被覆して形成すること
を特徴とする特許請求の範囲第1項記載の半導体装置の
製造方法。
3. The method for manufacturing a semiconductor device according to claim 1, wherein the coating film is formed by coating a coating film forming solution on the first insulating layer by a spin coating method. .
【請求項4】前記塗布膜形成溶液は硅素化合物を溶媒中
に分散あるいは溶解させたものを用いることを特徴とす
る特許請求の範囲第3項記載の半導体装置の製造方法。
4. The method for manufacturing a semiconductor device according to claim 3, wherein the coating film forming solution is a solution in which a silicon compound is dispersed or dissolved in a solvent.
【請求項5】前記塗布膜形成溶液は少なくともシリコン
(Si)元素とO(酸素)を含むことを特徴とする特許請
求の範囲第4項記載の半導体装置の製造方法。
5. The method of manufacturing a semiconductor device according to claim 4, wherein the coating film forming solution contains at least a silicon (Si) element and O (oxygen).
【請求項6】前記塗布膜をプラズマ中にさらす直前ある
いはプラズマにさらしている間に熱処理を加える工程を
含む特許請求の範囲第1項記載の半導体装置の製造方
法。
6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing heat treatment immediately before or during the exposure of the coating film to plasma.
JP62299926A 1987-11-30 1987-11-30 Method for manufacturing semiconductor device Expired - Lifetime JP2557916B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62299926A JP2557916B2 (en) 1987-11-30 1987-11-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62299926A JP2557916B2 (en) 1987-11-30 1987-11-30 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01143321A JPH01143321A (en) 1989-06-05
JP2557916B2 true JP2557916B2 (en) 1996-11-27

Family

ID=17878599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62299926A Expired - Lifetime JP2557916B2 (en) 1987-11-30 1987-11-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2557916B2 (en)

Also Published As

Publication number Publication date
JPH01143321A (en) 1989-06-05

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