JPH08236520A - Formation of insulation layer of semiconductor device - Google Patents
Formation of insulation layer of semiconductor deviceInfo
- Publication number
- JPH08236520A JPH08236520A JP7287009A JP28700995A JPH08236520A JP H08236520 A JPH08236520 A JP H08236520A JP 7287009 A JP7287009 A JP 7287009A JP 28700995 A JP28700995 A JP 28700995A JP H08236520 A JPH08236520 A JP H08236520A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- forming
- sog
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の絶縁
層の形成方法に関し、特に、超高集積回路（ＵＬＳＩ）
の多数層の金属配線間を絶縁させる絶縁層の形成方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating layer of a semiconductor device, and more particularly, an ultra high integrated circuit (ULSI).
The present invention relates to a method for forming an insulating layer that insulates a plurality of layers of metal wiring.
【０００２】[0002]
【従来の技術】半導体装置が高集積化されるにつれ、回
路が複雑になって、電気配線で利用される金属が多数の
層にて配線されている。このため、各金属配線層間に層
間絶縁層を形成させて互に絶縁させている。2. Description of the Related Art As semiconductor devices have been highly integrated, circuits have become complicated and metals used for electrical wiring have been wired in many layers. Therefore, an interlayer insulating layer is formed between the metal wiring layers to insulate each other.
【０００３】上記層間絶縁層は、通常、シリコン酸化膜
（Silicon Dioxide)で形成するが、電気配線を成す金属
の溶融と半導体基板にドーピングされた不純物の拡散と
による欠陥が発生することを防止するために、４００℃
以下の低い温度で形成することができるプラズマ化学気
相蒸着（Plasma Enhanced Chemical Vapor Deposion：
以下、ＰＥＣＶＤと呼ぶ）法で形成することが好まし
い。上記ＰＥＣＶＤ法によりシリコン酸化膜を形成する
場合、シラン（ＳｉＨ4）ガス、または、ＴＥＯＳ（テ
トラエトキシシラン：tetra ethoxi silane)をソース
（source）として使用することができる。The above-mentioned interlayer insulating layer is usually formed of a silicon oxide film (Silicon Dioxide), but it prevents the occurrence of defects due to the melting of the metal forming the electric wiring and the diffusion of the impurities doped in the semiconductor substrate. For 400 ℃
Plasma Enhanced Chemical Vapor Deposition (Plasma Enhanced Chemical Vapor Deposion:
Hereinafter, it is preferably formed by the PECVD method. When the silicon oxide film is formed by the PECVD method, silane (SiH 4 ) gas or TEOS (tetra ethoxisilane) can be used as a source.
【０００４】上記シランガスによる酸化膜は、上記シラ
ンガスが酸素（Ｏ2）または酸化窒素（Ｎ2Ｏ）とプラズ
マ状態で反応して形成されるが、段部での被覆性、すな
わち、ステップカバレージ（step coverage)が不良であ
る。また、微細な金属導線間にボイド（ｖｏｉｄ）が生
成されて電界強度が低下する。したがって、シランガス
により蒸着される酸化膜に比べ、ステップカバレージが
優秀なＴＥＯＳをソースとする酸化膜の導入が避けられ
なくなった。The oxide film formed by the silane gas is formed by the reaction of the silane gas with oxygen (O 2 ) or nitric oxide (N 2 O) in a plasma state, and the covering property at the step, that is, the step coverage ( The step coverage) is bad. In addition, voids are generated between the fine metal wires, and the electric field strength is reduced. Therefore, it is inevitable to introduce an oxide film using TEOS as a source, which has a better step coverage than an oxide film deposited by silane gas.
【０００５】しかし、このような場合でも、サブミクロ
ン（submicron)以下の微細な金属パタンの層間絶縁膜で
使用する時は、金属パターン間にボイドが形成されない
で、膜が完全に形成されることはむずかしい。However, even in such a case, when it is used as an interlayer insulating film of a fine metal pattern of submicron or less, voids are not formed between metal patterns and the film is completely formed. It's difficult.
【０００６】したがって、ステップカバレージを向上さ
せてボイドが形成されることを防止し、また、層間絶縁
膜の平坦化のための酸化膜間にガラス（ｇｌａｓｓ）が
回転塗布されて形成されたＳＯＧ（Spin-on Glass)膜を
有する多層構造の絶縁層が開発された。Therefore, the step coverage is improved to prevent the formation of voids, and the SOG (glass) formed by spin-coating the glass between the oxide films for flattening the interlayer insulating film is formed. A multi-layered insulating layer having a spin-on glass) film has been developed.
【０００７】[0007]
【発明が解決しようとする課題】上記従来技術に基づい
た半導体装置の絶縁層は、ＳＯＧ膜の上部および下部に
酸化膜が形成された構造を有する。上記のＳＯＧ膜は、
回転塗布された後、いろいろな種類の溶剤成分、揮発性
の有機成分および水分を、熱処理温度により種類別に徐
々に蒸発または揮発させて、亀裂発生が防止されるよう
に、数回の低温熱処理されて、つづけて高温熱処理によ
り硬化される。The insulating layer of the semiconductor device based on the above conventional technique has a structure in which an oxide film is formed on the upper and lower portions of the SOG film. The above SOG film is
After spin-coating, various kinds of solvent components, volatile organic components and water are gradually evaporated or volatilized according to the heat treatment temperature, and several low temperature heat treatments are performed to prevent cracks from occurring. Then, it is cured by high temperature heat treatment.
【０００８】しかし、シロキサン（siloxane）系ＳＯＧ
を使用する場合、ＳＯＧ膜内にＳｉ−ＣＨ3等の物質が
残留することになって、ＳＯＧ膜の硬化処理の過程が充
分な熱処理でなかった場合に、ＳＯＧ膜内には、水分お
よびＳｉ−ＯＨ物質が残留することになる。However, siloxane-based SOG
When Si is used, a substance such as Si—CH 3 remains in the SOG film, and if the curing process of the SOG film is not a sufficient heat treatment, moisture and Si are contained in the SOG film. -OH material will remain.
【０００９】上記残有物等は、ビアホール（ｖｉａ ｈ
ｏｌｅ）を形成する等の工程が後続する場合に、マスク
として利用された感光膜をＯ2プラズマ除去（photo res
istashing)時、Ｏ2プラズマによりＳＯＧ膜にＳｉ−Ｏ
Ｈ（シラノール系）および水分が含有されて、電流電圧
の特性が低下する問題点がある。[0009] The above-mentioned leftover materials are via holes (via h).
When a process such as the formation of ole) is performed subsequently, the photosensitive film used as a mask is removed by O 2 plasma (photo res
At the time of istashing), Si-O is formed on the SOG film by O 2 plasma.
Since H (silanol type) and water are contained, there is a problem that characteristics of current and voltage are deteriorated.
【００１０】したがって、本発明の目的は、残有物等が
生成されないようにＳＯＧ膜を硬化させることができる
半導体装置の絶縁膜の形成方法を提供することにある。Therefore, it is an object of the present invention to provide a method for forming an insulating film of a semiconductor device, which can cure an SOG film so as to prevent generation of residual substances and the like.
【００１１】本発明の他の目的は、後続するマスク工程
後、感光膜を除去する時、水分が生成されて電流電圧の
特性が低下されることを防ぐことができる半導体装置の
絶縁膜の形成方法を提供することにある。Another object of the present invention is to form an insulating film of a semiconductor device, which can prevent moisture from being generated and deteriorating current-voltage characteristics when the photoresist film is removed after a subsequent mask process. To provide a method.
【００１２】[0012]
【課題を解決するための手段】上記目的を達成するため
の本発明による半導体装置の絶縁層の形成方法は、基板
上に第１絶縁膜を形成する工程と、上記第１絶縁膜の上
部にＳＯＧ（スピンオングラス）膜物質を回転塗布して
第２絶縁膜を形成する工程と、上記第２絶縁膜に含んだ
溶剤成分、揮発性の有機成分および水分が除去されるよ
うに温度を順次的に上昇させながら数回の低温熱処理す
る工程と、プラズマ反応盧で、水素もしくは酸化窒素、
または、アルゴンもしくはヘリウム等の不活性ガスを使
用し、２００〜４５０℃程度の温度でプラズマ処理し
て、上記第２絶縁膜を稠密化させるように硬化させる工
程と、上記硬化された第２絶縁膜の上部にシランガスま
たはＴＥＯＳソースとするシリコン酸化膜をＰＥＣＶＤ
法により成膜して第３絶縁膜を形成する工程とを有す
る。A method of forming an insulating layer of a semiconductor device according to the present invention to achieve the above object comprises a step of forming a first insulating film on a substrate, and a step of forming a first insulating film on the first insulating film. A step of spin-coating an SOG (spin-on-glass) film material to form a second insulating film, and a temperature is sequentially adjusted so as to remove a solvent component, a volatile organic component and water contained in the second insulating film. The process of low temperature heat treatment several times while increasing the temperature to
Alternatively, a step of performing plasma treatment at a temperature of about 200 to 450 ° C. using an inert gas such as argon or helium to cure the second insulating film so as to make it dense, and the above-mentioned cured second insulating film. PECVD of silicon oxide film using silane gas or TEOS source on top of the film
And a step of forming a third insulating film by a method.
【００１３】[0013]
【発明の実施の形態】以下、添附した図を参照して、本
発明を詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the accompanying drawings.
【００１４】図１は、一般的な多層構造の絶縁層を有す
る半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device having a general multi-layered insulating layer.
【００１５】図１に示す半導体装置は、基板１の上部に
電気導線で利用される金属配線３と、この金属配線３と
この後に形成される上部の金属配線（図示せず）間を絶
縁させる第１、第２および第３絶縁膜５，７，９で構成
される絶縁層１１とで形成される。The semiconductor device shown in FIG. 1 insulates the metal wiring 3 used as an electric conductor on the upper portion of the substrate 1 and the metal wiring 3 and the upper metal wiring (not shown) formed thereafter. It is formed of an insulating layer 11 composed of the first, second and third insulating films 5, 7 and 9.
【００１６】上記基板１は、シリコンＳｉまたはガリウ
ム砒素（ＧａＡｓ）等で構成される半導体基板か、また
は、上記金属配線３の形成以前に形成された下部に、金
属配線（図示せず）間を絶縁させる上記絶縁層１１と同
一な構造を有する絶縁層であってもよい。The substrate 1 is a semiconductor substrate made of silicon Si, gallium arsenide (GaAs), or the like, or a metal wiring (not shown) is formed on a lower portion formed before the metal wiring 3 is formed. It may be an insulating layer having the same structure as the insulating layer 11 to be insulated.
【００１７】上記金属配線３は、アルミニウムＡｌまた
はチタンＴｉ等のように電気的な特性がよい導電性金属
にサブミクロン（sub-micron）またはハーフミクロン
（half-micron)程度の幅、例えば、０．３−１μｍの幅
を有するように形成される。The metal wiring 3 is made of a conductive metal having good electric characteristics such as aluminum Al or titanium Ti, and has a width of about sub-micron or half-micron, for example, 0. It is formed to have a width of 0.3-1 μm.
【００１８】絶縁層１１は、第１、第２および第３絶縁
膜５，７，９がシリコン酸化膜／ＳＯＧ膜／シリコン酸
化膜のサンドウイッチ構造を有するように形成される。The insulating layer 11 is formed so that the first, second and third insulating films 5, 7, 9 have a sandwich structure of silicon oxide film / SOG film / silicon oxide film.
【００１９】上記のシリコン酸化膜で構成される第１絶
縁膜５は、ステップカバレージがすぐれたＴＥＯＳをソ
ースとするＰＥＣＶＤ法により形成されて、金属配線３
と、ＳＯＧ膜で構成される第２絶縁膜７とのよくない親
和力により発生する接着不良を防ぐ。The first insulating film 5 made of the above-mentioned silicon oxide film is formed by the PECVD method using TEOS as a source, which has an excellent step coverage, and the metal wiring 3 is formed.
This prevents the adhesion failure caused by the poor affinity with the second insulating film 7 made of the SOG film.
【００２０】第２絶縁膜７は、ＳＯＧのフローイング
（flowing)により間隔埋め(gap fill)特性が良好なの
で、金属配線３により表面が出入りの基板１の上部に表
面が平坦に形成される。Since the second insulating film 7 has a good gap fill characteristic due to the SOG flowing, the metal wiring 3 forms a flat surface on the upper and lower surfaces of the substrate 1.
【００２１】第３絶縁膜９を成すシリコン酸化膜は、第
２絶縁膜７の表面が平坦化してボイドが形成されないの
で、シランガスまたはＴＥＯＳをソースとするＰＥＣＶ
Ｄ法により形成される。In the silicon oxide film forming the third insulating film 9, since the surface of the second insulating film 7 is flattened and voids are not formed, PECV using silane gas or TEOS as a source.
It is formed by the D method.
【００２２】上述した構造の半導体装置の製造におい
て、上記第３絶縁膜を形成する前に第２絶縁膜を形成す
るためのＳＯＧを塗布した後、溶剤成分および水分を揮
発させて硬化させなければならない。In the manufacture of the semiconductor device having the above-mentioned structure, after applying SOG for forming the second insulating film before forming the third insulating film, the solvent component and water must be volatilized and cured. I won't.
【００２３】上記プラズマ反応盧において、ガスのマス
流量（mass flow rate）の範囲は、例えば、１００〜１
０００ｓｃｃｍとすることができる。また、チャンバ内
の圧力は、例えば、５０〜１０００ｍＴｏｒｒとするこ
とができる。ガスとしては、例えば、水素、酸化窒素、
アルゴン、ヘリウム等のうちの１種を使用することがで
きる。In the above plasma reaction rod, the mass flow rate of the gas is, for example, 100 to 1
It can be 000 sccm. Further, the pressure in the chamber can be set to, for example, 50 to 1000 mTorr. Examples of the gas include hydrogen, nitric oxide,
One of argon, helium, etc. can be used.
【００２４】上記プラズマ反応盧は、例えば、１３．５
６ＭＨｚの高周波（ＲＦ）で０．２〜２．０Ｗ／ｃｍ2
のパワー密度のプラズマを生成する平行板プラズマ反応
盧を用いることができる。また、上記プラズマ処理は、
例えば、上記第２絶縁膜に残留するＳｉ−ＯＨおよびＳ
ｉ−ＣＨ3の結合を破ってＳｉ−Ｏの結合を強化させて
稠密化させるように硬化させることができる。The plasma reaction rod is, for example, 13.5.
0.2 to 2.0 W / cm 2 at 6 MHz radio frequency (RF)
A parallel plate plasma reaction rod that produces plasma with a power density of Further, the plasma treatment,
For example, Si—OH and S remaining in the second insulating film
beating binding of i-CH 3 to enhance the binding of Si-O may be cured so as to densify it.
【００２５】本発明の実施形態の一例としては、基板上
に第１絶縁膜を形成する工程と、上記第１絶縁膜の上部
にＳＯＧを回転塗布して第２絶縁膜を形成する工程と、
上記第２絶縁膜に含まれる溶剤成分、揮発性の有機成分
および水分が除かれるように、温度を順次的に上昇させ
ながら数回の低温熱処理する工程と、平行板プラズマ反
応盧で、水素もしくは酸化窒素、または、アルゴンもし
くはヘリウムの不活性ガスを使用して、０．２〜２．０
Ｗ／ｃｍ2のパワー密度を有する高周波電力でプラズマ
を生成して、２００〜４５０℃程度の温度において、上
記第２絶縁膜を処理して、稠密化させるように硬化させ
る工程と、上記硬化された第２絶縁膜の上部にシランガ
スまたはＴＥＯＳをソースとするシリコン酸化膜をＰＥ
ＣＶＤ法により成膜して第３絶縁膜を形成する工程とを
有するものが挙げられる。As an example of the embodiment of the present invention, a step of forming a first insulating film on a substrate, a step of spin-coating SOG on the first insulating film to form a second insulating film,
In order to remove the solvent component, the volatile organic component, and the water contained in the second insulating film, the low temperature heat treatment is performed several times while sequentially increasing the temperature, and hydrogen or hydrogen is used in the parallel plate plasma reaction chamber. 0.2 to 2.0 using nitric oxide or an inert gas such as argon or helium.
Plasma is generated with high frequency power having a power density of W / cm 2 , and the second insulating film is treated at a temperature of about 200 to 450 ° C. and hardened so as to be densified; A silicon oxide film with silane gas or TEOS as a source is formed on the second insulating film by PE.
And a step of forming a third insulating film by a CVD method.
【００２６】[0026]
【実施例】図２は、本発明に基づいた半導体装置の絶縁
膜の形成方法の一実施例を示すフロー図であり、図１の
半導体装置を引用して説明する。2 is a flow chart showing an embodiment of a method for forming an insulating film of a semiconductor device according to the present invention, which will be described with reference to the semiconductor device of FIG.
【００２７】第１段階２１は、金属配線３が形成された
基板１の上部にシランガスをソースとする酸化膜をＰＥ
ＣＶＤ法により成膜して第１絶縁膜５を形成する。In the first step 21, an oxide film using silane gas as a source is formed on the substrate 1 on which the metal wiring 3 is formed by PE.
The first insulating film 5 is formed by film formation by the CVD method.
【００２８】上記酸化膜で形成された第１絶縁膜５は、
上記基板１および金属配線３と親和力がよくて接着力が
向上される。The first insulating film 5 formed of the oxide film is
The affinity with the substrate 1 and the metal wiring 3 is good, and the adhesive force is improved.
【００２９】第２段階２２は、上記第１絶縁膜３の上部
に、結合剤として利用されて膜の内亀裂性を向上させる
メチル（ＣＨ3）またはフェニル（Ｃ6Ｈ5）等の有機物
を含むシロキサン（siloxane）系ＳＯＧ物質を、表面が
平坦化することになるように回転塗布して第２絶縁膜７
を形成する。シロキサン系のＳＯＧ物質としては、例え
ば、アライド・シグナル社（Allied Signal Company）
製のアキュグラス（Accuglass）２１１，アキュグラス
Ｔ−１４シリーズのうちの一つが用いられる。上記の第
２絶縁膜７の結合剤はＳｉ−ＣＨ3状態で結合される。In the second step 22, an organic substance such as methyl (CH 3 ) or phenyl (C 6 H 5 ) which is used as a binder and improves the internal cracking property of the film is formed on the first insulating film 3. The second insulating film 7 is formed by spin-coating a siloxane-based SOG material containing the same so that the surface is flattened.
To form. Examples of siloxane-based SOG substances include Allied Signal Company
One of the Accuglass 211 and the Accuglass T-14 series manufactured by Acuglass Corporation is used. Binding agent of the second insulating film 7 above are combined in Si-CH 3 state.
【００３０】第３段階２３は、温度を順次的に上昇させ
ながら数回の低温熱処理して、上記第２絶縁膜７に含ん
でいる結合剤として利用される有機物を除いた溶剤成
分、揮発性の有機成分および水分を除去する。上記の第
２絶縁膜７は、含んでいた上記のいろいろな種類の有機
溶剤と水分とが短い時間に急激に除去されることによる
亀裂の発生を防ぐため、温度を順次に上昇させながら数
回の低温熱処理を行なう。例えば、第１段階が７０〜９
０℃，第２段階が１４０〜１６０℃および第３段階が２
００〜２３０℃のように、階段状に順次昇温し、各段階
で各々１〜２分程度熱処理して、計３回の低温熱処理を
行なう。上記のいろいろな種類の溶剤成分、揮発性の有
機成分および水分を、熱処理した温度により、徐々に種
類別に蒸発または揮発させる。In the third step 23, the low temperature heat treatment is performed several times while sequentially increasing the temperature to remove the organic components used as the binder contained in the second insulating film 7 except the organic components and the volatility. To remove the organic components and water. The second insulating film 7 has a temperature which is sequentially increased several times in order to prevent the occurrence of cracks due to abrupt removal of the various kinds of contained organic solvents and water in a short time. Low temperature heat treatment. For example, the first stage is 70-9
0 ℃, 140 ~ 160 ℃ in the second stage and 2 in the third stage
As in the case of 00 to 230 ° C., the temperature is sequentially raised stepwise, and heat treatment is performed for 1 to 2 minutes at each stage, and low temperature heat treatment is performed three times in total. The above-mentioned various kinds of solvent components, volatile organic components and water are gradually evaporated or volatilized according to the type of heat treatment.
【００３１】第４段階２４は、熱処理を遂行した後、上
記第２絶縁膜７をプラズマ処理して、Ｓｉ−ＯＨ、Ｈ2
Ｏ、溶剤および揮発性の有機物等の残有物を除去して、
弾性が高い膜質を形成する。In the fourth step 24, after the heat treatment is performed, the second insulating film 7 is plasma-treated to obtain Si--OH and H 2
O, solvent and residual substances such as volatile organic substances are removed,
Form a film with high elasticity.
【００３２】上記プラズマ処理は、１３．５６ＭＨｚの
高周波（ＲＦ）を有する平行板プラズマ反応盧(paralle
l plate plasma reactor）で遂行する。プラズマ処理
時、水素（Ｈ2）もしくは酸化窒素（Ｎ2Ｏ）等、また
は、アルゴン（Ａｒ）もしくはヘリウム（Ｈｅ）等の不
活性ガスが使用される。プラズマを形成するために必要
なＲＦパワー密度は、０．２〜２．０Ｗ／ｃｍ2であ
る。また、ガスのマス流量（flow rate)は、１００〜１
０００ｓｃｃｍの範囲に使用し、チャンバ（chamber)内
の圧力は５０〜１０００ｍＴｏｒｒで維持する。The above plasma treatment is performed by a parallel plate plasma reactor having a radio frequency (RF) of 13.56 MHz.
l plate plasma reactor). During the plasma treatment, hydrogen (H 2 ) or nitric oxide (N 2 O) or the like, or an inert gas such as argon (Ar) or helium (He) is used. The RF power density required to form the plasma is 0.2 to 2.0 W / cm 2 . In addition, the mass flow rate of the gas is 100 to 1
It is used in the range of 000 sccm, and the pressure in the chamber is maintained at 50 to 1000 mTorr.
【００３３】上記の外部から電場が印加されれば、上記
プラズマが形成された反応盧で、イオンまたはラジカル
（radical)らが励起されて、上記第２絶縁膜７内で拡散
されて残留するＳｉ−ＯＨおよびＳｉ−ＣＨ3の結合を
破って、Ｓｉ−Ｏの結合を強化させる。結果として、上
記第２絶縁膜７を稠密化させるように硬化させる。When an electric field is applied from the outside, ions or radicals are excited in the reaction chamber in which the plasma is formed, and Si that is diffused and remains in the second insulating film 7 remains. The bond of —OH and Si—CH 3 is broken to strengthen the bond of Si—O. As a result, the second insulating film 7 is hardened so as to be densified.
【００３４】上記の−ＯＨおよび−ＣＨ3は、漏泄電流
の発生および絶縁破壊電圧を低くするので、炭素（Ｃ）
はＣＯ2の形で、水素（Ｈ）はＨ2Ｏの形で外部へ拡散さ
せて、第２絶縁膜７を稠密化させる。Since the above-mentioned --OH and --CH 3 reduce the generation of leakage current and the dielectric breakdown voltage, carbon (C)
In the form of CO 2 and hydrogen (H) in the form of H 2 O to the outside to densify the second insulating film 7.
【００３５】上記プラズマ処理時、２００〜４５０℃程
度の温度が適正であるが、処理時の温度が高ければ高い
ほどウェットエッチング率および稠密化（densificatio
n)が向上されて、第２絶縁膜７の電気的な特性を向上さ
せることができる。During the plasma treatment, a temperature of about 200 to 450 ° C. is appropriate, but the higher the temperature during the treatment, the higher the wet etching rate and the densificatio.
n) is improved, and the electrical characteristics of the second insulating film 7 can be improved.
【００３６】第５段階２５は、上記硬化された第２絶縁
膜７の上部にシランガスまたはＴＥＯＳをソースとする
シリコン酸化膜をＰＥＣＶＤ法により成膜して第３絶縁
膜９を形成して、絶縁層１１を完成させる。In the fifth step 25, a silicon oxide film using silane gas or TEOS as a source is formed on the hardened second insulating film 7 by PECVD to form a third insulating film 9, and insulation is performed. Complete layer 11.
【００３７】図３は、従来技術に基づいた熱によって硬
化処理されたＳＯＧ膜と本発明によるプラズマによって
硬化処理されたＳＯＧ膜とのウェットエッチング率を比
較図示したグラフである。上記グラフにおいて、（ａ）
は従来技術に基づいた熱によって硬化処理された場合を
表し、（ｂ）、（ｃ）および（ｄ）は本発明に基づいた
プラズマ処理によって硬化された場合を表し、プラズマ
処理に使用したガスが（ｂ）はアルゴン、（ｃ）は水
素、および、（ｄ）は酸化窒素に対応する。FIG. 3 is a graph showing a comparison of wet etching rates of the SOG film cured by heat and the SOG film cured by plasma according to the present invention. In the above graph, (a)
Represents the case of being cured by heat according to the prior art, and (b), (c) and (d) represents the case of being cured by the plasma treatment according to the present invention, in which the gas used for the plasma treatment is (B) corresponds to argon, (c) corresponds to hydrogen, and (d) corresponds to nitric oxide.
【００３８】上記のウェットエッチング率は、（ａ）が
約１４００オングストローム／分程度であり、（ｂ）は
約３９０オングストローム／分程度であり、（ｃ）は約
４１０オングストローム／分程度であり、（ｄ）は約７
００オングストローム／分程度である。したがって、従
来技術に基づいた硬化処理方法による場合に比べ、本発
明の硬化処理の方法による場合は、ウェットエッチング
率が２〜３．５倍程度おくれる。上記ウェットエッチン
グ率の減少は、プラズマ処理によりＳＯＧ膜が構造的に
精密に硬化されるからである。The above wet etching rate is about 1400 angstroms / minute in (a), about 390 angstroms / minute in (b), and about 410 angstroms / minute in (c). d) is about 7
It is about 00 angstrom / minute. Therefore, in the case of the hardening method of the present invention, the wet etching rate is about 2 to 3.5 times as long as in the case of the hardening method based on the conventional technique. The decrease in the wet etching rate is because the SOG film is structurally precisely cured by the plasma treatment.
【００３９】図４は、従来技術に基づいた熱処理によっ
て硬化処理されたＳＯＧ膜と本発明の一実施例によるア
ルゴンプラズマによって硬化処理されたＳＯＧ膜とのプ
ラズマ処理時間による電流−電圧（Ｉ−Ｖ）の特性を比
較図示したグラフである。上記グラフにおいて、（ａ）
は従来技術に基づいて熱によって硬化処理された場合で
あり、（ｂ）、（ｃ）および（ｄ）は本発明の一実施例
によりアルゴンプラズマによって硬化された場合であ
る。（ｂ）、（ｃ）および（ｄ）は、各々１０分、３０
分および６０分間硬化処理されたことに対応している。FIG. 4 shows the current-voltage (IV) depending on the plasma processing time of the SOG film cured by the heat treatment according to the prior art and the SOG film cured by the argon plasma according to the embodiment of the present invention. 3 is a graph comparing and illustrating the characteristics of FIG. In the above graph, (a)
Is a case of being cured by heat according to the conventional technique, and (b), (c) and (d) are cases of being cured by an argon plasma according to an embodiment of the present invention. (B), (c) and (d) are 10 minutes and 30 minutes, respectively.
It corresponds to the fact that it was cured for 60 minutes and 60 minutes.
【００４０】上記の試料として使用されたＳＯＧ膜の各
々は、１０００オングストロームの厚さを有して、電流
−電圧特性をモス（ＭＯＳ）構造のキャパシタで測定し
た。Each of the SOG films used as the above samples had a thickness of 1000 angstroms, and the current-voltage characteristics were measured with a MOS (MOS) structure capacitor.
【００４１】上記の測定結果、本発明の一実施例による
アルゴンプラズマによって硬化処理されたＳＯＧ膜が、
従来技術に示されているように熱によって硬化処理され
たＳＯＧ膜より、電流−電圧特性が良好で、その中で、
（ｄ）、すなわち、処理時間が６０分の場合が、一番良
好な電流−電圧特性を示す。As a result of the above measurement, the SOG film cured by the argon plasma according to the embodiment of the present invention was
Current-voltage characteristics are better than those of SOG films cured by heat as shown in the prior art.
(D), that is, the case where the processing time is 60 minutes shows the best current-voltage characteristics.
【００４２】上記の本発明の一実施例によるアルゴンプ
ラズマにより硬化処理されたＳＯＧ膜が良好な電流−電
圧特性を有することは、ＳＯＧ膜内の−ＯＨおよび−Ｃ
Ｈ3等の漏泄電流を発生させる欠陥等が減少されたこと
による。The fact that the SOG film hardened by the argon plasma according to the above embodiment of the present invention has good current-voltage characteristics means that -OH and -C in the SOG film are high.
This is because defects such as H 3 that generate leakage current are reduced.
【００４３】上述したような本発明に基づいた半導体装
置の絶縁層の形成方法は、第２絶縁膜であるＳＯＧ膜を
回転塗布し、いろいろな種類の有機溶剤と水分が短い時
間内に急激に除去されることによる亀裂発生を防止する
ように、数回の低温熱処理した後、平行板プラズマ反応
盧において、水素、酸化窒素、アルゴン、ヘリウム等の
うちいずれかのガスを使用して、高周波（例えば１３．
５６ＭＨｚ）で発生されるプラズマで硬化処理して、第
２絶縁膜内のＳｉ−ＯＨ、Ｈ2Ｏ、溶剤および揮発性の
有機物等の残有物を除去して、弾性が高くなるように形
成する。In the method of forming the insulating layer of the semiconductor device according to the present invention as described above, the SOG film as the second insulating film is spin-coated, and various kinds of organic solvents and water are rapidly applied within a short time. After performing low-temperature heat treatment for several times so as to prevent cracking due to removal, a high frequency (high frequency) was generated by using any gas of hydrogen, nitric oxide, argon, helium, etc. in the parallel plate plasma reaction rod. For example, 13.
56 MHz) is used for hardening treatment to remove residual substances such as Si—OH, H 2 O, solvent and volatile organic substances in the second insulating film so as to increase elasticity. To do.
【００４４】[0044]
【発明の効果】したがって、本発明は、ビアホールを形
成する等の後続工程にマスクとして利用される感光膜除
去時、水分が生成されて、ＳＯＧ膜の電流−電圧特性が
低下されることを防止することができる効果がある。Therefore, according to the present invention, it is prevented that the current-voltage characteristics of the SOG film are deteriorated due to the generation of water when removing the photosensitive film used as a mask in the subsequent process such as forming a via hole. There is an effect that can be.
【図１】一般的な多層構造の絶縁層を有する半導体装置
の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device having a general multi-layered insulating layer.
【図２】本発明による半導体装置の絶縁層の形成方法を
示すフロー図である。FIG. 2 is a flowchart showing a method for forming an insulating layer of a semiconductor device according to the present invention.
【図３】従来技術の熱処理によって硬化処理されたＳＯ
Ｇ膜と本発明によるプラズマによって硬化処理されたＳ
ＯＧ膜とのウェットエッチング率を比較図示したグラフ
である。FIG. 3 SO cured by prior art heat treatment
G film and S cured by plasma according to the present invention
5 is a graph showing a comparison of wet etching rates with an OG film.
【図４】従来技術の熱処理によって硬化処理されたＳＯ
Ｇ膜と本発明の一実施例によるアルゴンプラズマによっ
て硬化処理されたＳＯＧ膜とのプラズマ処理時間による
電流−電圧（Ｉ−Ｖ）特性を比較図示したグラフであ
る。FIG. 4 SO cured by prior art heat treatment
7 is a graph comparing current-voltage (IV) characteristics of a G film and an SOG film cured by argon plasma according to an exemplary embodiment of the present invention with a plasma processing time.
１…基板、３…金属配線、５…第１絶縁膜、７…第２絶
縁膜、９…第３絶縁膜1 ... Substrate, 3 ... Metal wiring, 5 ... First insulating film, 7 ... Second insulating film, 9 ... Third insulating film
Claims (3)
質を回転塗布して第２絶縁膜を形成する工程と、 上記第２絶縁膜に含んだ溶剤成分、揮発性の有機成分お
よび水分が除去されるように温度を順次的に上昇させな
がら数回の低温熱処理する工程と、 プラズマ反応盧で、水素もしくは酸化窒素、または、ア
ルゴンもしくはヘリウム等の不活性ガスを使用し、２０
０〜４５０℃程度の温度でプラズマ処理して、上記第２
絶縁膜を稠密化させるように硬化させる工程と、 上記硬化された第２絶縁膜の上部にシランガスまたはＴ
ＥＯＳソースとするシリコン酸化膜をＰＥＣＶＤ法によ
り成膜して第３絶縁膜を形成する工程とを備えた半導体
装置の絶縁層の形成方法。1. A step of forming a first insulating film on a substrate, a step of spin-coating an SOG (spin on glass) substance on the first insulating film to form a second insulating film, A step of performing low temperature heat treatment several times while sequentially increasing the temperature so as to remove the solvent component, volatile organic component and water contained in the insulating film, and hydrogen or nitrogen oxide, or Use an inert gas such as argon or helium, and
Plasma treatment at a temperature of about 0 to 450 ° C.
A step of hardening the insulating film so as to make it dense; and silane gas or T on the hardened second insulating film.
And a step of forming a third insulating film by forming a silicon oxide film as an EOS source by a PECVD method, and forming a third insulating film.
low rate）の範囲が１００〜１０００ｓｃｃｍであり、
チャンバ内の圧力は５０〜１０００ｍＴｏｒｒであるこ
とを特徴とする半導体装置の絶縁層の形成方法。2. The mass flow rate (mass f) of gas in the plasma reaction rod according to claim 1.
low rate) range is 100-1000 sccm,
The method for forming an insulating layer of a semiconductor device, wherein the pressure in the chamber is 50 to 1000 mTorr.
で、０．２〜２．０Ｗ／ｃｍ2のパワー密度でプラズマ
を生成する平行板プラズマ反応盧であり、上記プラズマ
処理は、上記第２絶縁膜に残留するＳｉ−ＯＨおよびＳ
ｉ−ＣＨ3の結合を破ってＳｉ−Ｏの結合を強化させて
稠密化させるように硬化させることを特徴とする半導体
装置の絶縁層の形成方法。3. The plasma reaction rod according to claim 1 or 2, wherein the radio frequency (RF) is 13.56 MHz.
And a parallel plate plasma reaction rod that generates plasma with a power density of 0.2 to 2.0 W / cm 2 , and the plasma treatment is performed by using Si—OH and S remaining on the second insulating film.
A method for forming an insulating layer of a semiconductor device, which comprises curing by hardening a bond of i-CH 3 to strengthen a bond of Si-O to make it dense.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR94-28804 | 1994-11-03 | ||
| KR1019940028804A KR0138853B1 (en) | 1994-11-03 | 1994-11-03 | Curing method of spin-on glass by plasma process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08236520A true JPH08236520A (en) | 1996-09-13 |
| JP3061558B2 JP3061558B2 (en) | 2000-07-10 |
Family
ID=19397052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7287009A Expired - Fee Related JP3061558B2 (en) | 1994-11-03 | 1995-11-06 | Method for forming insulating layer of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3061558B2 (en) |
| KR (1) | KR0138853B1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6133137A (en) * | 1997-09-02 | 2000-10-17 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| WO2004012252A1 (en) * | 2002-07-30 | 2004-02-05 | Tokyo Electron Limited | Method for forming insulating layer |
| KR100492906B1 (en) * | 2000-10-04 | 2005-06-02 | 주식회사 하이닉스반도체 | Method of forming dielectric layer in semiconductor device |
| US7569497B2 (en) | 2002-07-30 | 2009-08-04 | Tokyo Electron Limited | Method and apparatus for forming insulating layer |
| US11972945B2 (en) | 2018-03-01 | 2024-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990004889A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Method of forming interlayer insulating film of semiconductor device |
| KR100440265B1 (en) * | 1997-12-30 | 2004-09-18 | 주식회사 하이닉스반도체 | Method for forming sog layer of semiconductor device to basically prevent change of driving threshold voltage and via bowing phenomenon |
| US6534921B1 (en) * | 2000-11-09 | 2003-03-18 | Samsung Electronics Co., Ltd. | Method for removing residual metal-containing polymer material and ion implanted photoresist in atmospheric downstream plasma jet system |
| KR20030090191A (en) * | 2002-05-21 | 2003-11-28 | 삼성전자주식회사 | Method of performing dielectric layer in semiconductor device |
| KR102201698B1 (en) * | 2013-06-20 | 2021-01-12 | 주성엔지니어링(주) | Semiconductor device and method for manufacutring the same |
-
1994
- 1994-11-03 KR KR1019940028804A patent/KR0138853B1/en not_active IP Right Cessation
-
1995
- 1995-11-06 JP JP7287009A patent/JP3061558B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6133137A (en) * | 1997-09-02 | 2000-10-17 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| KR100492906B1 (en) * | 2000-10-04 | 2005-06-02 | 주식회사 하이닉스반도체 | Method of forming dielectric layer in semiconductor device |
| WO2004012252A1 (en) * | 2002-07-30 | 2004-02-05 | Tokyo Electron Limited | Method for forming insulating layer |
| US7569497B2 (en) | 2002-07-30 | 2009-08-04 | Tokyo Electron Limited | Method and apparatus for forming insulating layer |
| US11972945B2 (en) | 2018-03-01 | 2024-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3061558B2 (en) | 2000-07-10 |
| KR960019505A (en) | 1996-06-17 |
| KR0138853B1 (en) | 1998-06-01 |
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