JPH05243212A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05243212A JPH05243212A JP4277292A JP4277292A JPH05243212A JP H05243212 A JPH05243212 A JP H05243212A JP 4277292 A JP4277292 A JP 4277292A JP 4277292 A JP4277292 A JP 4277292A JP H05243212 A JPH05243212 A JP H05243212A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- polysilazane
- passivation
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、パシベーション膜の形
成方法に特徴を有する半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device characterized by a method of forming a passivation film.
【0002】[0002]
【従来の技術】半導体装置、特に半導体集積回路装置へ
の水分の影響は従来から問題視されており、半導体装置
等の活性領域や配線を湿気等から保護するためのパシベ
ーション膜として比較的吸湿性が小さいプラズマSiN
膜やプラズマSiON膜が使用されてきた。2. Description of the Related Art The influence of moisture on a semiconductor device, particularly a semiconductor integrated circuit device, has conventionally been regarded as a problem, and it has a relatively hygroscopic property as a passivation film for protecting active regions and wirings of the semiconductor device from moisture. Small plasma SiN
Films and plasma SiON films have been used.
【0003】[0003]
【発明が解決しようとする課題】しかし、前記のプラズ
マSiN膜やプラズマSiON膜をパシベーション膜と
して用いる場合は、これらのパシベーション膜を形成す
る過程で、半導体装置の特性に変動あるいは劣化を生じ
ない最高限度の温度でキュアしても、膜質を緻密化する
温度としては不十分で必要な耐湿性を持たせることがで
きず、これらのパシベーション膜を厚くすることによっ
て必要な耐湿性を持たせようとすると、クラックの発生
を伴うという問題があった。However, when the above plasma SiN film or plasma SiON film is used as the passivation film, the characteristics of the semiconductor device are not changed or deteriorated in the process of forming these passivation films. Even if the film is cured at the limit temperature, it is not sufficient as the temperature for densifying the film quality and cannot have the necessary moisture resistance.Thus, by increasing the thickness of these passivation films, it is necessary to provide the necessary moisture resistance. Then, there is a problem that cracks are generated.
【0004】また、これらのパシベーション膜は被覆性
が悪いため、段差部の側壁に厚く堆積できず、堆積でき
る膜厚は5000Å、厚くても1.0μm程度が限度
で、それ以上厚く堆積しても部分的に膜厚の薄い部分が
生じていた。Further, since these passivation films have poor coverage, they cannot be deposited thickly on the side walls of the step portion, and the film thickness that can be deposited is 5000 Å, and even if it is thick, the limit is about 1.0 μm. Also, there was a part where the film thickness was thin.
【0005】また、これらのパシベーション膜のクラッ
クあるいは膜厚が不足する部分の耐湿性の劣化を補うた
めにポリイミドを塗布することが試みられていたが、段
差を平坦化しないままにしてポリイミドを形成すると、
窪みにポリイミドが厚く生成され、この吸湿性の高いポ
リイミドの水分が半導体装置の活性領域に浸透するのを
完全に遮断することはできなかった。Further, it has been attempted to apply polyimide in order to compensate for the cracks in the passivation film or the deterioration of the moisture resistance in the portion where the film thickness is insufficient, but the polyimide is formed without flattening the steps. Then,
It was impossible to completely block the penetration of the moisture of the highly hygroscopic polyimide into the active region of the semiconductor device because the polyimide was thickly formed in the depression.
【0006】本発明は、このような問題を解決するた
め、耐湿性が良好で、被覆性がよく、厚く形成してもク
ラックの発生を伴わない緻密なパシベーション膜を有す
る半導体装置を提供することを目的とする。In order to solve such a problem, the present invention provides a semiconductor device having a fine passivation film which has good moisture resistance, good coverage, and does not cause cracks even when formed thick. With the goal.
【0007】[0007]
【課題を解決するための手段】本発明にかかる半導体装
置の製造方法においては、半導体装置の表面にポリシラ
ザンを塗布する工程と、塗布したポリシラザンをキュア
して酸化することによって緻密で吸湿性が小さいシリコ
ン酸化膜からなるパシベーション膜を形成する工程を採
用した。In the method for manufacturing a semiconductor device according to the present invention, a step of applying polysilazane to the surface of the semiconductor device and a dense and low hygroscopic property by curing and oxidizing the applied polysilazane. A process of forming a passivation film made of a silicon oxide film is adopted.
【0008】[0008]
【作用】本発明者らは、ポリシラザンの半導体装置のパ
シベーション膜への適用可能性を検討し実験を重ねた結
果、ポリシラザンは450℃程度の低温で積極的に酸化
されシラザン結合がSi−O結合に変換されて、緻密性
が高く、耐湿性が優れたシリコン酸化膜を形成すること
を見出した。The inventors of the present invention investigated the applicability of polysilazane to the passivation film of the semiconductor device, and conducted repeated experiments. As a result, polysilazane was actively oxidized at a low temperature of about 450 ° C. and the silazane bond was a Si—O bond. It was found that a silicon oxide film having a high density and a high moisture resistance was formed by being converted into.
【0009】本発明は、従来から半導体装置の成膜の最
終工程で行われていたカバーSiN膜,カバーSiON
膜,ポリイミド膜等のパシベーション膜の耐湿性を改善
するために、これらのパシベーション膜の代わりに、ま
たは、これらのパシベーション膜の成膜の前後に、被覆
性が良好なポリシラザンを塗布し、比較的低温でウェッ
ト酸素雰囲気中でキュアして、ポリシラザンの窒素を酸
素で置換することによって緻密で耐湿性が優れたシリコ
ン酸化膜からなるパシベーション膜を形成することを特
徴とする。According to the present invention, the cover SiN film and the cover SiON film, which have been conventionally used in the final step of film formation of a semiconductor device, are used.
In order to improve the moisture resistance of a passivation film such as a film or a polyimide film, polysilazane having a good covering property is applied in place of these passivation films, or before or after the formation of these passivation films, and relatively. It is characterized in that a passivation film made of a silicon oxide film which is dense and has excellent moisture resistance is formed by performing curing in a wet oxygen atmosphere at a low temperature and replacing nitrogen of polysilazane with oxygen.
【0010】従来からパシベーション膜として使用され
ていた無機SOGを用いた場合は下記の化学式1の通り
であり、左側の無機SOGの(OH)と(OH)が(H
2 O)として抜けだし、その後に右側のように(O)が
残ることによって(Si−O−Si)の形で酸化される
ため、原子量が34から16に減少し、それに応じて体
積が収縮しクラックを生じることになる。When an inorganic SOG conventionally used as a passivation film is used, the following chemical formula 1 is given, and (OH) and (OH) of the left inorganic SOG are (H
2 O), and after that (O) remains on the right side, it is oxidized in the form of (Si-O-Si), so the atomic weight decreases from 34 to 16 and the volume shrinks accordingly. This will cause cracks.
【0011】[0011]
【化1】 [Chemical 1]
【0012】また、有機SOGを用いる場合は下記の化
学式2に示されるように、右側の有機SOGの有機基が
離脱して(Si−O−Si)の形で酸化されるが、Rが
CH 3 である場合は、原子量が15から16に増加する
から、体積は僅か膨張しクラックの発生を伴わないで厚
い膜を形成することができる。When organic SOG is used,
As shown in Formula 2, the organic group of the organic SOG on the right side
It leaves and is oxidized in the form of (Si-O-Si), but R is
CH 3, Then the atomic weight increases from 15 to 16
Therefore, the volume expands slightly and the thickness is increased without cracks.
It is possible to form a transparent film.
【0013】[0013]
【化2】 [Chemical 2]
【0014】しかし、有機SOGは、耐熱性が不足する
ため、550℃以上の高温処理を施すバルク工程では用
いることができなかった。However, since organic SOG has insufficient heat resistance, it cannot be used in a bulk process in which a high temperature treatment of 550 ° C. or higher is performed.
【0015】これに反して、ポリシラザンを用いた場合
は下記の化学式3の通りであり、左側のポリシラザンの
(H)が(O)によって置換されて右側に示されるよう
に(Si−O−Si)の形で酸化されて原子量は1から
16に増加するため体積が膨張して圧縮力を発生するこ
とになる。On the other hand, when polysilazane is used, it is represented by the following chemical formula 3, and (H) of the polysilazane on the left side is replaced by (O) as shown on the right side (Si-O-Si). ), The atomic weight increases from 1 to 16 and the volume expands to generate a compressive force.
【0016】[0016]
【化3】 [Chemical 3]
【0017】そして、この圧縮力によってパシベーショ
ン膜が緻密化され、クラックが発生しないばかりでな
く、Al等の金属配線が圧縮力を受け、金属のエレクト
ロマイグレーションが抑制されることによって配線の信
頼性が向上する。また、この圧縮力によって上記の配線
だけでなく、その下層の絶縁膜や回路素子の信頼性を向
上する効果を生じる。The compressive force densifies the passivation film to prevent cracks from occurring, and the metal wiring such as Al receives a compressive force to suppress electromigration of the metal, thereby improving reliability of the wiring. improves. Further, this compressive force has an effect of improving not only the above-mentioned wiring but also the reliability of the insulating film and the circuit element therebelow.
【0018】また、ポリシラザン膜の被覆性が優れてい
るため、段差部においても1.5μm程度の厚さまで容
易に形成することができるから、ポリシラザン膜を酸化
して形成したシリコン酸化膜自体の水分の吸収性能がプ
ラズマCVD−SiN膜の2分の1程度であり、プラズ
マCVD−SiN膜の5倍の厚さに形成できるとする
と、このパシベーション膜を透過する水分の量を従来の
10分の1程度に低減すことができる。Further, since the polysilazane film has excellent coverage, the polysilazane film can be easily formed to a thickness of about 1.5 μm. Therefore, the moisture content of the silicon oxide film itself formed by oxidizing the polysilazane film can be improved. Is about half the plasma CVD-SiN film, and if it can be formed to have a thickness five times that of the plasma CVD-SiN film, the amount of water that permeates the passivation film can be reduced to 10 times the conventional amount. It can be reduced to about 1.
【0019】[0019]
【実施例】本発明の一実施例を説明する。図1(A)〜
(C)は、本発明の一実施例の半導体装置の製造工程説
明図である。この図において、1は半導体基板、2は配
線、3はボンディングパッド、4はプラズマCVD−S
iN膜、5はポリシラザン膜、6はシリコン酸化膜、7
はポリイミド膜である。この製造工程説明図によって本
発明の一実施例の半導体装置の製造方法を説明する。EXAMPLE An example of the present invention will be described. FIG. 1 (A)-
(C) is a manufacturing process explanatory diagram of the semiconductor device of one embodiment of the present invention. In this figure, 1 is a semiconductor substrate, 2 is wiring, 3 is a bonding pad, and 4 is plasma CVD-S.
iN film, 5 is a polysilazane film, 6 is a silicon oxide film, 7
Is a polyimide film. A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the manufacturing process explanatory diagram.
【0020】第1工程(図1(A)参照) 半導体基板1に、従来から知られている工程によって回
路素子等を形成し、その上に厚さ1.0μmのAl−C
u−Ti合金からなる配線2とボンディングパッド3を
形成する。その上に、パシベーション膜として厚さ50
00ÅのプラズマCVD−SiN膜4を形成する。この
プラズマCVD−SiN膜4は半導体基板1と配線2と
ボンディングパッド3の表面に段差状に形成される。First step (see FIG. 1A) A circuit element or the like is formed on a semiconductor substrate 1 by a conventionally known step, and Al-C having a thickness of 1.0 μm is formed thereon.
The wiring 2 and the bonding pad 3 made of a u-Ti alloy are formed. Then, as a passivation film, a thickness of 50
A plasma CVD-SiN film 4 of 00Å is formed. The plasma CVD-SiN film 4 is formed in steps on the surfaces of the semiconductor substrate 1, the wiring 2 and the bonding pad 3.
【0021】第2工程(図1(B)参照) 段差上のプラズマCVD−SiN膜4の上にポリシラザ
ンを8000Å程度スピンコートし、200℃で3分間
程度ベークして有機溶剤を除去して固体化しポリシラザ
ン膜5を形成する。Second step (see FIG. 1B) Polysilazane is spin-coated on the stepped plasma CVD-SiN film 4 by about 8000 Å, and baked at 200 ° C. for about 3 minutes to remove the organic solvent and solidify. Then, the polysilazane film 5 is formed.
【0022】第3工程(図1(C)参照) ウェット酸素雰囲気中において450℃で30分間焼成
して、ポリシラザン5の窒素を酸素で置換してシリコン
酸化膜6に変換する。このシリコン酸化膜6は大部分が
SiO2 であるが、ポリシラザンの窒素(N)が残った
SiONが僅かに存在する。次いで、シリコン酸化膜6
の上にポリイミド膜7を形成し、フォトリソグラフィー
技術とプラズマエッチングによって、ボンディングパッ
ド3の上のポリイミド膜7とシリコン酸化膜6とプラズ
マCVD−SiN膜4を除去して、ボンディングパッド
3を露出させる。このポリイミド膜7は、耐エッチング
性がやや弱いシリコン酸化膜6を保護するために形成さ
れている。Third step (see FIG. 1C) In a wet oxygen atmosphere, baking is performed at 450 ° C. for 30 minutes to replace nitrogen in the polysilazane 5 with oxygen to convert it into a silicon oxide film 6. Most of the silicon oxide film 6 is SiO 2 , but there is a small amount of SiON in which nitrogen (N) of polysilazane remains. Then, the silicon oxide film 6
A polyimide film 7 is formed on the bonding pad 3, and the polyimide film 7, the silicon oxide film 6 and the plasma CVD-SiN film 4 on the bonding pad 3 are removed by photolithography and plasma etching to expose the bonding pad 3. . The polyimide film 7 is formed to protect the silicon oxide film 6 having a slightly weak etching resistance.
【0023】[0023]
【発明の効果】以上説明したように、本発明によると、
ポリシラザン膜を塗布し酸化してシリコン酸化膜からな
るパシベーション膜を形成することにより、従来技術に
よるプラズマ−SiN膜の問題であった吸湿性の原因と
なっていた被覆性の悪さとパシベーション膜自体の吸湿
性を解消できるため、水分の浸入の遮断を確実に行うこ
とができ、半導体装置の信頼性の向上に寄与するところ
が大きい。As described above, according to the present invention,
By coating and oxidizing a polysilazane film to form a passivation film made of a silicon oxide film, the poor coverage and the passivation film itself, which had been the cause of the hygroscopicity which was the problem of the plasma-SiN film of the prior art. Since the hygroscopicity can be eliminated, it is possible to surely prevent the infiltration of moisture, which largely contributes to the improvement of the reliability of the semiconductor device.
【図1】(A)〜(C)は本発明の一実施例の半導体装
置の製造工程説明図である。1A to 1C are explanatory views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
1 半導体基板 2 配線 3 ボンディングパッド 4 プラズマCVD−SiN膜 5 ポリシラザン膜 6 シリコン酸化膜 7 ポリイミド膜 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Wiring 3 Bonding pad 4 Plasma CVD-SiN film 5 Polysilazane film 6 Silicon oxide film 7 Polyimide film
Claims (1)
シラザンを塗布する工程と、塗布したポリシラザンをキ
ュアして酸化することによって緻密で吸湿性が小さいシ
リコン酸化膜からなるパシベーション膜を形成する工程
を含むことを特徴とする半導体装置の製造方法。1. A step of applying polysilazane having excellent coverage to a surface of a semiconductor device, and a step of curing the applied polysilazane to oxidize it to form a passivation film made of a silicon oxide film which is dense and has low hygroscopicity. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4277292A JPH05243212A (en) | 1992-02-28 | 1992-02-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4277292A JPH05243212A (en) | 1992-02-28 | 1992-02-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05243212A true JPH05243212A (en) | 1993-09-21 |
Family
ID=12645265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4277292A Withdrawn JPH05243212A (en) | 1992-02-28 | 1992-02-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05243212A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5770260A (en) * | 1993-07-29 | 1998-06-23 | Fujitsu Limited | Process for forming silicon dioxide film |
US6191002B1 (en) | 1998-04-27 | 2001-02-20 | Nec Corporation | Method of forming trench isolation structure |
US6767641B1 (en) * | 2000-04-25 | 2004-07-27 | Clariant Finance (Bvi) Limited | Method for sealing fine groove with siliceous material and substrate having siliceous coating formed thereon |
DE102008044769A1 (en) | 2008-08-28 | 2010-03-04 | Clariant International Limited | Process for producing ceramic passivation layers on silicon for solar cell production |
-
1992
- 1992-02-28 JP JP4277292A patent/JPH05243212A/en not_active Withdrawn
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5770260A (en) * | 1993-07-29 | 1998-06-23 | Fujitsu Limited | Process for forming silicon dioxide film |
US5976618A (en) * | 1993-07-29 | 1999-11-02 | Fujitsu Limited | Process for forming silicon dioxide film |
US6191002B1 (en) | 1998-04-27 | 2001-02-20 | Nec Corporation | Method of forming trench isolation structure |
US6767641B1 (en) * | 2000-04-25 | 2004-07-27 | Clariant Finance (Bvi) Limited | Method for sealing fine groove with siliceous material and substrate having siliceous coating formed thereon |
DE102008044769A1 (en) | 2008-08-28 | 2010-03-04 | Clariant International Limited | Process for producing ceramic passivation layers on silicon for solar cell production |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |