JP3390890B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3390890B2 JP3390890B2 JP24747194A JP24747194A JP3390890B2 JP 3390890 B2 JP3390890 B2 JP 3390890B2 JP 24747194 A JP24747194 A JP 24747194A JP 24747194 A JP24747194 A JP 24747194A JP 3390890 B2 JP3390890 B2 JP 3390890B2
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- JP
- Japan
- Prior art keywords
- firing
- film
- semiconductor device
- manufacturing
- sog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関するものであり、特に、無機厚膜SOG(spin
on glass)を用いた層間絶縁膜の形成方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an inorganic thick film SOG (spin).
on glass) for forming an interlayer insulating film.
【0002】[0002]
【従来の技術】従来、半導体集積回路装置の配線層の平
坦化のために、テトラアルコキシシランを原料とした無
機SOGやメチルトリアルコキシシランを原料とした有
機SOGが用いられていたが、これらのSOG内には結
合に寄与しないメチル基やエチル基が含まれているため
収縮応力が小さく、したがって、クラック耐性は良好で
あるものの、逆に、含まれるメチル基やエチル基が多い
とフォトレジストのアッシング工程等において、酸素プ
ラズマに晒された時に劣化するという欠点があった。2. Description of the Related Art Conventionally, in order to flatten a wiring layer of a semiconductor integrated circuit device, an inorganic SOG made of tetraalkoxysilane or an organic SOG made of methyltrialkoxysilane has been used. Since the SOG contains a methyl group or an ethyl group that does not contribute to the bond, the shrinkage stress is small, and therefore the crack resistance is good, but conversely, if the methyl group or the ethyl group contained is large, the photoresist becomes In the ashing process and the like, there is a drawback that it deteriorates when exposed to oxygen plasma.
【0003】近年、このクラック耐性及び酸素プラズマ
耐性を両立するSOGとして、分子末端が水素で終端
し、骨格中にシラザン結合を有するSi化合物材料を原
料とした無機厚膜SOGが実用化されている。この無機
厚膜SOGは、従来のSOGとは異なって、焼成時に酸
素雰囲気或いは水蒸気雰囲気等の酸化雰囲気にすること
で、シラザン結合を酸化させて緻密で良質な酸化膜に変
換することができる。In recent years, as an SOG having both crack resistance and oxygen plasma resistance, an inorganic thick film SOG made of a Si compound material having a molecular end terminated with hydrogen and having a silazane bond in the skeleton has been put to practical use. . Unlike the conventional SOG, this inorganic thick film SOG can oxidize silazane bonds and convert it into a dense and high-quality oxide film by setting it in an oxidizing atmosphere such as an oxygen atmosphere or a steam atmosphere during firing.
【0004】しかし、この様な焼成方法を用いると、焼
成工程後の降温速度によりAl等の配線層に欠損が生じ
たり、焼成工程後の加熱処理工程、例えば、Al配線層
形成前の450℃程度の温度におけるアニール処理にお
いて、SOGから多量の脱ガスが発生して、脱ガスとの
反応によってAl配線層が腐食したり、脱ガスの気泡に
より層間絶縁膜が破裂したりする等の問題が生じてい
た。However, when such a firing method is used, a defect occurs in the wiring layer such as Al due to the temperature decrease rate after the firing step, or a heat treatment step after the firing step, for example, 450 ° C. before the formation of the Al wiring layer. In annealing at a moderate temperature, a large amount of degas is generated from SOG, and the Al wiring layer is corroded by the reaction with the degas, and the interlayer insulating film is ruptured by bubbles of the degas. It was happening.
【0005】この内、焼成工程後の降温速度によるAl
等の配線層の欠損の発生を抑制するためには、焼成を低
温化して酸化反応を抑制したり、或いは、焼成を短時間
化することにより焼成雰囲気中から取り込まれる水分を
少なくして酸化反応を抑制したりすることにより、SO
Gの収縮による応力を小さくして、下地Al配線層の欠
損を防止することができる。Of these, Al depending on the temperature decrease rate after the firing step
In order to prevent the occurrence of defects in the wiring layer such as, the firing reaction is suppressed by lowering the firing temperature, or the firing reaction is shortened to reduce the moisture taken in from the firing atmosphere. Suppressing SO
The stress due to the contraction of G can be reduced to prevent the underlying Al wiring layer from being damaged.
【0006】次に、焼成工程後の加熱処理工程における
SOGからの脱ガスの発生を抑制するためには、水蒸気
雰囲気中で焼成を行うことにより、脱ガスを焼成時に済
ましてその後の工程における脱ガスの発生を低減するこ
とができる。Next, in order to suppress the generation of outgas from SOG in the heat treatment step after the firing step, firing is performed in a steam atmosphere so that degassing is completed at the time of firing and degassing is performed in the subsequent step. Generation of gas can be reduced.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、焼成を
低温化或いは短時間化すると酸化が不十分となり、緻密
で良質な酸化膜に変換するという目的に反することにな
り、酸化膜の膜質が低下するという欠点が生ずることに
なり、また、焼成を水蒸気雰囲気中で行うとしても、下
地Al配線層の欠損の発生を抑制するという観点からは
十分な時間焼成を行うことができないので、依然として
脱ガス発生の問題が残ることになる。However, if the firing temperature is lowered or the heating time is shortened, the oxidation becomes insufficient, which defeats the purpose of converting the oxide film into a dense and high-quality oxide film, resulting in deterioration of the film quality of the oxide film. However, even if the firing is performed in a steam atmosphere, since firing cannot be performed for a sufficient time from the viewpoint of suppressing the occurrence of defects in the underlying Al wiring layer, degassing still occurs. The problem of will remain.
【0008】したがって、本発明は、分子末端が水素で
終端し、骨格中にシラザン結合を有するSi化合物材料
からなる無機厚膜SOG形成用材料の焼成工程及びその
後の熱処理工程における、配線層の欠損の発生及び脱ガ
スの発生を抑制することを目的とする。Therefore, according to the present invention, the wiring layer is deficient in the step of firing the inorganic thick film SOG forming material made of a Si compound material having a silazane bond in the skeleton, the molecular end of which is terminated by hydrogen, and the subsequent heat treatment step. The purpose is to suppress the generation of gas and degassing.
【0009】[0009]
【課題を解決するための手段】本発明は、下地絶縁膜
(図1の2)上に設けた配線層(図1の3)表面及び前
記下地絶縁膜(図1の2)の露出表面にCVD膜(図1
の4)を堆積し、次いで、分子末端が水素で終端し、骨
格中にシラザン結合を有するSi化合物材料からなる無
機厚膜SOG形成用材料を塗布し、この無機厚膜SOG
形成用材料を塗布した半導体ウェハを焼成する工程にお
いて、焼成炉からの半導体ウェハの引出しを900mm
/分以上の高速で行うことを特徴とする。また、本発明
は、乾燥酸素雰囲気或いは水蒸気雰囲気中で焼成を行う
ことを特徴とする。The present invention provides a wiring layer (3 in FIG. 1) surface provided on a base insulating film (2 in FIG. 1) and an exposed surface of the base insulating film (2 in FIG. 1). CVD film (Fig. 1
4) is deposited, and then an inorganic thick film SOG forming material composed of a Si compound material having a molecular end terminated with hydrogen and having a silazane bond in the skeleton is applied, and this inorganic thick film SOG is applied.
In the step of baking the semiconductor wafer coated with the forming material, pulling out the semiconductor wafer from the baking furnace is 900 mm.
The feature is that it is performed at a high speed of more than 1 minute. Further, the present invention is characterized in that firing is performed in a dry oxygen atmosphere or a steam atmosphere.
【0010】また、本発明は、下地絶縁膜(図1の2)
上に設けた配線層(図1の3)を覆うように分子末端が
水素で終端し、骨格中にシラザン結合を有するSi化合
物材料からなる無機厚膜SOG形成用材料を塗布し、こ
の無機厚膜SOG形成用材料を塗布した半導体ウェハを
24時間以上密閉容器中に放置し、その後、焼成するこ
とを特徴とする。The present invention also provides a base insulating film (2 in FIG. 1).
An inorganic thick film SOG forming material composed of a Si compound material whose molecular end is terminated by hydrogen so as to cover the wiring layer (3 in FIG. 1) provided above and having a silazane bond in the skeleton is applied, and this inorganic thickness It is characterized in that the semiconductor wafer coated with the material for forming a film SOG is left in a closed container for 24 hours or more and then baked.
【0011】また、本発明は、塗布後24時間以上密閉
容器中に放置した無機厚膜SOGを、乾燥酸素雰囲気中
で焼成することを特徴とする。また、本発明は、CVD
膜としてプラズマCVD膜を用いることを特徴とする。 Further, the present invention is characterized in that the inorganic thick film SOG left in a closed container for 24 hours or more after coating is baked in a dry oxygen atmosphere. The present invention also relates to CVD
A feature is that a plasma CVD film is used as the film.
【0012】[0012]
【作用】焼成炉からの半導体ウェハの引出しを900m
m/分以上の高速で行うことにより、焼成温度から室温
までの降温時間を45分程度と短くできるため、収縮応
力が小さくなり、下地Al配線層の欠損の発生を防止す
ることができる。また、焼成を乾燥酸素雰囲気中で行っ
た場合には、酸化膜の膜質は多少劣るものの、焼成装置
の構成を簡素化することができ、他方、焼成を水蒸気雰
囲気中で行った場合には、水蒸気発生装置等の特別の機
構を焼成装置内に設ける必要が生ずるものの、得られる
酸化膜がより緻密になり、膜質が向上する。[Operation] Pulling out the semiconductor wafer from the baking furnace 900 m
By performing the heating at a high speed of m / min or more, the temperature lowering time from the firing temperature to room temperature can be shortened to about 45 minutes, so that the shrinkage stress can be reduced and the occurrence of defects in the underlying Al wiring layer can be prevented. Also, when firing is performed in a dry oxygen atmosphere, the film quality of the oxide film is somewhat inferior, but the configuration of the firing apparatus can be simplified, while when firing is performed in a steam atmosphere, Although it is necessary to provide a special mechanism such as a steam generator in the baking apparatus, the obtained oxide film becomes more dense and the film quality is improved.
【0013】また、無機厚膜SOGを塗布したのち、2
4時間以上密閉容器中に放置することにより、密閉容器
内において、容器内の空気中の水分がSOG膜表面に自
然吸着し、この水分とSOGの成分とが反応してアンモ
ニアが生成され、この生成されたアンモニアが触媒とし
て作用することにより更に反応が進むことになる。そし
て、この結果、焼成の際には、水蒸気雰囲気中での焼成
と同じような状態になるので、脱ガスが焼成時に略完了
することになる。After the inorganic thick film SOG is applied, 2
By leaving it in the closed container for 4 hours or more, the water in the air in the container is naturally adsorbed on the surface of the SOG film in the closed container, and the water reacts with the component of SOG to generate ammonia. The produced ammonia acts as a catalyst to further advance the reaction. Then, as a result, the state of firing is the same as the state of firing in a steam atmosphere, so that degassing is almost completed at the time of firing.
【0014】また、上述のように、焼成時の状態は水蒸
気雰囲気中での焼成と同じような状態になるので、乾燥
酸素雰囲気中での焼成で十分になり、焼成装置の構成を
簡素化することができる。また、後述するように、プラ
ズマCVD膜はブロック作用が高いので、即ち、膜が緻
密であるため、CVD膜としてプラズマCVD膜を用い
ることによって水分をブロックすることができる。 Further, as described above, the state of firing is the same as the state of firing in a steam atmosphere, so firing in a dry oxygen atmosphere is sufficient, and the configuration of the firing apparatus is simplified. be able to. Also, as described later,
Since the Zuma CVD film has a high blocking effect, that is, the film is fine.
Since it is dense, plasma CVD film is used as the CVD film.
Water can be blocked by doing so.
【0015】[0015]
【実施例】図1は本発明の第1の実施例の説明図であ
る。
図1参照
先ず、シリコン半導体基板1上にSiO2 等の下地絶縁
膜2を介してAl配線層3を設け、次いで、SiH4 を
40ml/分、N2 Oを150ml/分、N2を200
0ml/分の流量比で流した、3.0Torrの圧力下
で、基板温度を250℃とした状態で240WのRF電
力を印加するプラズマCVD法により、膜厚が450n
mのSiON膜4をAl配線層3及び下地絶縁膜2の露
出表面を覆うように堆積させる。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of a first embodiment of the present invention. Referring to FIG. 1, first, an Al wiring layer 3 is provided on a silicon semiconductor substrate 1 through a base insulating film 2 such as SiO 2 , and then SiH 4 is 40 ml / min, N 2 O is 150 ml / min, and N 2 is 200 ml.
A film thickness of 450 n is obtained by a plasma CVD method in which RF power of 240 W is applied at a substrate temperature of 250 ° C. under a pressure of 3.0 Torr and a flow rate of 0 ml / min.
The SiON film 4 of m is deposited so as to cover the exposed surfaces of the Al wiring layer 3 and the base insulating film 2.
【0016】なお、この場合に、得られたSiON膜4
はシリコンオキシナイトライド膜を総称するものであ
り、Si:O:N=1:1:1の膜を表すものではな
い。また、この場合に得られたSiON膜4の屈折率は
1.58であった。In this case, the SiON film 4 obtained
Represents a silicon oxynitride film generically, and does not represent a film of Si: O: N = 1: 1: 1. The refractive index of the SiON film 4 obtained in this case was 1.58.
【0017】次に、分子末端が水素で終端し、骨格中に
シラザン結合を有するSi化合物材料からなるSOG形
成用材料を塗布したのち、SOG形成用材料が塗布され
た半導体ウェハを900mm/分の挿入速度で450℃
に昇温させた焼成炉内に挿入する。Next, after applying an SOG-forming material composed of a Si compound material whose molecular ends are terminated by hydrogen and having a silazane bond in the skeleton, a semiconductor wafer coated with the SOG-forming material is 900 mm / min. 450 ℃ at insertion speed
It is inserted into the firing furnace whose temperature has been raised to.
【0018】次いで、焼成炉内において、乾燥酸素雰囲
気中で、450℃の温度で30分間焼成を行い、焼成終
了後に、900mm/分の引出し速度で半導体ウェハを
焼成炉から引出し、室温まで急速に降温させて、緻密化
したSOG膜5を得る。この場合、450℃から室温ま
での降温時間は45分であった。なお、焼成温度は45
0℃が好適であるが、400℃〜500℃の範囲であれ
ば良く、また、焼成時間も焼成温度にもよるが、10分
〜120分の範囲であれば良い。Then, in a firing furnace, firing is performed at a temperature of 450 ° C. for 30 minutes in a dry oxygen atmosphere, and after the firing is completed, the semiconductor wafer is pulled out from the firing furnace at a withdrawing speed of 900 mm / min, and rapidly heated to room temperature. The temperature is lowered to obtain the densified SOG film 5. In this case, the cooling time from 450 ° C. to room temperature was 45 minutes. The firing temperature is 45
0 ° C. is suitable, but it may be in the range of 400 ° C. to 500 ° C., and may be in the range of 10 minutes to 120 minutes, depending on the firing time and the firing temperature.
【0019】次に、この第1の実施例と比較例との実験
結果を表1に示す。Next, Table 1 shows the experimental results of the first embodiment and the comparative example.
【表1】 [Table 1]
【0020】表1は、焼成炉への挿入速度及び焼成炉か
らの引出し速度を共に900mm/分とした本発明の第
1の実施例と、焼成炉への挿入速度を900mm/分と
すると共に、焼成炉からの引出し速度を120mm/分
とした比較例を比べたものであり、表1における上段の
分数は配線幅に対する欠損の大きさを表し、下段の数値
は1チップ内の欠損の個数を示すものであり、0は欠損
が全く無いことを表す。なお、比較例においては、焼成
炉からの引出し速度が異なるだけで他の条件は全く同じ
である。Table 1 shows the first embodiment of the present invention in which the insertion speed into the firing furnace and the withdrawal speed from the firing furnace are both 900 mm / min, and the insertion speed into the firing furnace is 900 mm / min. In comparison with the comparative example in which the drawing speed from the firing furnace was 120 mm / min, the upper fraction in Table 1 represents the size of the defect with respect to the wiring width, and the lower number represents the number of defects in one chip. And 0 means that there is no defect at all. In the comparative example, other conditions are exactly the same except that the drawing speed from the firing furnace is different.
【0021】表1から明らかなように、比較例において
はAl配線層に欠損が発生するが、本発明の第1の実施
例においては欠損の発生は見られなかった。要するに、
焼成炉からの引出し速度を900mm/分以上の高速に
することにより、焼成炉の炉温から室温までの降温時間
を短くでき、それによって無機厚膜SOG膜に発生する
収縮応力は小さくなり、配線層に欠損が発生することが
抑制される。As is clear from Table 1, in the comparative example, the Al wiring layer had a defect, but in the first embodiment of the present invention, no defect was observed. in short,
By setting the drawing speed from the baking furnace to a high speed of 900 mm / min or more, the temperature decrease time from the furnace temperature to the room temperature of the baking furnace can be shortened, thereby reducing the shrinkage stress generated in the inorganic thick film SOG film, and reducing the wiring. The occurrence of defects in the layer is suppressed.
【0022】また、比較例において発生した欠損は、配
線幅が0.7μmの場合は、0.7μmの大きさの欠損
が1チップ当たり71個発生し、配線幅が1.0μmの
場合には、0.2μmの大きさの欠損が1チップ当たり
6個発生した。この様に、配線幅が狭くなるほど発生頻
度が大きくなる傾向が見られるので、本発明は集積度の
向上した超高集積度半導体集積回路装置においてより効
果を発揮するものである。In the comparative example, when the wiring width is 0.7 μm, 71 defects having a size of 0.7 μm are generated per chip, and when the wiring width is 1.0 μm. , 0.2 μm in size, 6 defects were generated per chip. As described above, since the frequency of occurrence tends to increase as the wiring width becomes narrower, the present invention is more effective in an ultra-high integration semiconductor integrated circuit device having an improved integration degree.
【0023】なお、上記の実施例においては、乾燥酸素
雰囲気中で焼成を行っているが、水蒸気雰囲気中で行っ
ても良く、この場合には、酸化反応がより進行するので
緻密で膜質の良好なSOG膜が得られる。但し、水蒸気
雰囲気を得るためには、酸素と水素とからなる燃焼装置
等の水蒸気発生装置を焼成炉内に組み込む必要が生じ、
装置が大型化・複雑化することになる。In the above embodiment, the baking is carried out in a dry oxygen atmosphere, but it may be carried out in a water vapor atmosphere. In this case, the oxidation reaction proceeds further, so that the film is dense and has a good film quality. A stable SOG film can be obtained. However, in order to obtain a steam atmosphere, it becomes necessary to incorporate a steam generator such as a combustion device composed of oxygen and hydrogen into the firing furnace.
The device becomes large and complicated.
【0024】また、上記の第1の実施例においては、水
分のブロック作用を考慮して、配線層を被覆するCVD
膜として、プラズマSiON膜を用いているが、プラズ
マSiNでも良い、このプラズマSiN膜上にプラズマ
SiO2 膜を重ねて2層膜としたものでも良い。In the first embodiment, the CVD for covering the wiring layer is performed in consideration of the water blocking effect.
Although a plasma SiON film is used as the film, plasma SiN may be used, or a plasma SiO 2 film may be stacked on this plasma SiN film to form a two-layer film.
【0025】次に、本発明の第2の実施例を図1および
図2を用いて説明する。
図1参照
先ず、シリコン半導体基板1上にSiO2 等の下地絶縁
膜2を介してAl配線層3を設け、次いで、SiH4 を
40ml/分、N2 Oを150ml/分、N2を200
0ml/分の流量比で流した、3.0Torrの圧力下
で、基板温度を250℃とした状態で240WのRF電
力を印加するプラズマCVD法により、膜厚が450n
mのSiON膜4をAl配線層3及び下地絶縁膜2の露
出表面を覆うように堆積させる。なお、この場合にも、
得られたSiON膜4はシリコンオキシナイトライド膜
を総称するものであり、Si:O:N=1:1:1の膜
を表すものではない。また、この場合に得られたSiO
N膜4の屈折率は1.58であった。Next, a second embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 1, first, an Al wiring layer 3 is provided on a silicon semiconductor substrate 1 via a base insulating film 2 such as SiO 2 , then SiH 4 is 40 ml / min, N 2 O is 150 ml / min, and N 2 is 200 ml.
A film thickness of 450 n is obtained by a plasma CVD method in which RF power of 240 W is applied at a substrate temperature of 250 ° C. under a pressure of 3.0 Torr and a flow rate of 0 ml / min.
The SiON film 4 of m is deposited so as to cover the exposed surfaces of the Al wiring layer 3 and the base insulating film 2. Even in this case,
The obtained SiON film 4 is a generic term for a silicon oxynitride film, and does not represent a film of Si: O: N = 1: 1: 1. In addition, the SiO obtained in this case
The refractive index of the N film 4 was 1.58.
【0026】次に、分子末端が水素で終端し、骨格中に
シラザン結合を有するSi化合物材料からなるSOG形
成用材料を塗布したのち、SOG形成用材料が塗布され
た半導体ウェハを原結晶BOX(ウェハ購入時の収納容
器)等の密閉容器内に収納し、24時間以上放置する。
放置している間に、容器内の空気中の水分が塗布膜の表
面に自然吸着して反応生成物としてアンモニアが発生
し、発生したアンモニアが触媒として作用することによ
り、反応はさらに進行する。Next, an SOG-forming material composed of a Si compound material having molecular ends terminated with hydrogen and having a silazane bond in the skeleton is applied, and then a semiconductor wafer on which the SOG-forming material is applied is processed into a raw crystal BOX ( Store in a closed container (such as the container used to purchase the wafer) and leave it for 24 hours or more.
While left to stand, moisture in the air in the container is naturally adsorbed on the surface of the coating film to generate ammonia as a reaction product, and the generated ammonia acts as a catalyst to further advance the reaction.
【0027】次に、24時間以上の放置後、SOG形成
用材料が塗布された半導体ウェハを900mm/分の挿
入速度で450℃に昇温させた焼成炉内に挿入し、焼成
炉内において、乾燥酸素雰囲気中で、450℃の温度で
30分間焼成を行い、焼成終了後に、900mm/分の
引出し速度で半導体ウェハを焼成炉から引出し、室温ま
で急速に降温させて、緻密化したSOG膜5を得る。Next, after standing for 24 hours or more, the semiconductor wafer coated with the SOG forming material is inserted into a firing furnace heated to 450 ° C. at an insertion speed of 900 mm / min, and in the firing furnace, Sintering is performed at a temperature of 450 ° C. for 30 minutes in a dry oxygen atmosphere, and after the firing is completed, the semiconductor wafer is pulled out from the firing furnace at a withdrawing speed of 900 mm / min, and the temperature is rapidly lowered to room temperature to densify the SOG film 5. To get
【0028】図2参照
図2は、この様にして得られたSOG膜5を焼成工程後
の加熱処理工程、例えば、Al配線層形成前のアニール
温度に相当する450℃程度の温度に加熱した場合の脱
ガス量をTDS(Thermal Desorptio
n Spectroscopy:加熱することにより系
内に発生するガスを測定する装置)により測定した結果
を示すものである。Referring to FIG. 2, FIG. 2 shows that the SOG film 5 thus obtained is heated at a heat treatment step after the firing step, for example, at a temperature of about 450 ° C. corresponding to the annealing temperature before the formation of the Al wiring layer. In the case of TDS (Thermal Desorptio)
n Spectroscopy: A device for measuring the gas generated in the system by heating).
【0029】図から明らかなように、分子量16のガ
ス、分子量17のガス、及び、分子量18のガスの脱ガ
ス量の経時変化は同じではないものの、24時間放置し
た場合の総脱ガス量(図における左側から3番目の黒塗
りの四角形のドット)は、放置時間が0の場合に比べて
1/2以下に低減し、48時間放置した場合(図におけ
る左側から4番目の黒塗りの四角形のドット)には1/
6以下に低減することが理解できる。As is clear from the figure, the degassing amounts of the gas having a molecular weight of 16, the gas having a molecular weight of 17 and the gas having a molecular weight of 18 are not the same over time, but the total amount of degassing when left for 24 hours ( The third black-painted quadrangular dot from the left side in the figure is reduced to 1/2 or less compared to the case where the leaving time is 0, and when left for 48 hours (fourth black-painted quadrangle from the left side in the figure). Dot) is 1 /
It can be understood that the number is reduced to 6 or less.
【0030】したがって、SOG形成用材料の塗布後、
少なくとも24時間密閉容器内で放置することにより、
大幅な脱ガス量の発生を抑制することができる。なお、
塗布後の放置を開放系で行った場合には、水分との反応
で生成されるアンモニアが飛散して触媒として作用しな
くなるため、反応の進行が遅くなるので放置する効果が
あまりなくなる。Therefore, after applying the SOG forming material,
By leaving it in a closed container for at least 24 hours,
The generation of a large amount of degas can be suppressed. In addition,
If the coating is left to stand in an open system, the ammonia produced by the reaction with water scatters and does not act as a catalyst, and the reaction is slowed down, so that the effect of standing is not so great.
【0031】なお、上記の第2の実施例においては、第
1の実施例と同様な挿入・引出し条件及び焼成条件を採
用しているが、前述の表1からも明らかなように、配線
層の幅が2.0μm以上の場合等においては、焼成炉か
らの引出し速度を900mm/分以上の高速にする必要
はない。In the second embodiment, the same insertion / drawing conditions and firing conditions as in the first embodiment are adopted, but as is clear from Table 1 above, the wiring layer When the width is 2.0 μm or more, the drawing speed from the firing furnace need not be 900 mm / min or more.
【0032】また、上記各実施例においては、配線層と
してAl配線層を用いているが、Al配線層に限られる
ものではなく、Cu等を含有するAl合金配線層や、或
いは、W等の他の高融点金属配線層でも良いものであ
る。In each of the above embodiments, the Al wiring layer is used as the wiring layer, but the wiring layer is not limited to the Al wiring layer, and an Al alloy wiring layer containing Cu or the like or W or the like. Other refractory metal wiring layers may also be used.
【0033】[0033]
【発明の効果】本発明によれば、分子末端が水素で終端
し、骨格中にシラザン結合を有するSi化合物材料から
形成される無機厚膜SOG膜を層間絶縁膜として用いる
際に、SOG膜の焼成工程において焼成炉からの半導体
ウェハの引出し速度を高速にすることにより、或いは、
焼成前に塗布後の半導体ウェハを密閉容器内に長時間放
置することにより、配線層に欠損が発生することを抑制
し、また、脱ガスによる配線層の腐食及び層間絶縁膜の
破裂の発生を抑制できるので、信頼性の高い半導体装置
を得ることができる。According to the present invention, when an inorganic thick film SOG film formed of a Si compound material having molecular ends terminated by hydrogen and having a silazane bond in the skeleton is used as an interlayer insulating film, By increasing the speed of withdrawing the semiconductor wafer from the firing furnace in the firing step, or
Leaving the coated semiconductor wafer in a closed container for a long time before firing suppresses the occurrence of defects in the wiring layer, and also prevents corrosion of the wiring layer and rupture of the interlayer insulating film due to degassing. Since it can be suppressed, a highly reliable semiconductor device can be obtained.
【図1】本発明の第1の実施例及び第2の実施例に共通
の説明図である。FIG. 1 is an explanatory view common to a first embodiment and a second embodiment of the present invention.
【図2】本発明の第2の実施例における放置時間と脱ガ
ス量の相関を示す図である。FIG. 2 is a diagram showing a correlation between a standing time and a degassing amount in the second embodiment of the present invention.
【符号の説明】 1 シリコン半導体基板 2 下地絶縁膜 3 Al配線層 4 CVDSiON膜 5 SOG膜[Explanation of symbols] 1 Silicon semiconductor substrate 2 Base insulating film 3 Al wiring layer 4 CVD SiON film 5 SOG film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/31 H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/31 H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318
Claims (9)
記下地絶縁膜の露出表面にCVD膜を堆積し、次いで、
分子末端が水素で終端し、骨格中にシラザン結合を有す
るSi化合物材料からなる無機厚膜SOG形成用材料を
塗布し、前記無機厚膜SOG形成用材料を塗布した半導
体ウェハを焼成炉において焼成した後、前記焼成炉から
前記半導体ウェハを引き出す際の引出速度を900mm
/分以上の高速にしたことを特徴とする半導体装置の製
造方法。1. A CVD film is deposited on a surface of a wiring layer provided on a base insulating film and an exposed surface of the base insulating film, and then,
An inorganic thick film SOG forming material made of a Si compound material having a molecular terminus terminated by hydrogen and having a silazane bond in the skeleton was applied, and the semiconductor wafer coated with the inorganic thick film SOG forming material was fired in a firing furnace. After that, the withdrawal speed when withdrawing the semiconductor wafer from the firing furnace is 900 mm.
A method for manufacturing a semiconductor device, which is characterized by a high speed of not less than / minute.
G形成用材料を塗布した半導体ウェハを上記焼成炉に挿
入する際に、挿入速度を900mm/分以上の高速にし
たことを特徴とする請求項1記載の半導体装置の製造方
法。2. The inorganic thick film SO prior to the firing.
2. The method for manufacturing a semiconductor device according to claim 1, wherein when the semiconductor wafer coated with the G forming material is inserted into the firing furnace, the insertion speed is set to a high speed of 900 mm / min or more.
とを特徴とする請求項1または2に記載の半導体装置の
製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein the firing is performed in a dry oxygen atmosphere.
を特徴とする請求項1または2に記載の半導体装置の製
造方法。4. The method for manufacturing a semiconductor device according to claim 1, wherein the firing is performed in a water vapor atmosphere.
特徴とする請求項1記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the CVD film is a SiON film.
に分子末端が水素で終端し、骨格中にシラザン結合を有
するSi化合物材料からなる無機厚膜SOG形成用材料
を塗布し、前記無機厚膜SOG形成用材料を塗布した半
導体ウェハを24時間以上密閉容器内に放置したのち、
焼成を行い無機厚膜SOG膜を形成することを特徴とす
る半導体装置の製造方法。6. A material for forming an inorganic thick film SOG comprising a Si compound material whose molecular end is terminated by hydrogen so as to cover a wiring layer provided on a base insulating film and has a silazane bond in the skeleton, After leaving the semiconductor wafer coated with the material for forming an inorganic thick film SOG in a closed container for 24 hours or more,
A method of manufacturing a semiconductor device, which comprises firing to form an inorganic thick film SOG film.
とを特徴とする請求項6記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein the firing is performed in a dry oxygen atmosphere.
焼成炉から引出す際に、その引出し速度を900mm/
分以上にしたことを特徴とする請求項6または7に記載
の半導体装置の製造方法。8. When the semiconductor wafer is pulled out from the firing furnace after the firing, the pulling rate is 900 mm /
8. The method for manufacturing a semiconductor device according to claim 6, wherein the number of minutes is set to be at least a minute.
ことを特徴とする請求項1乃至8のいずれか1項に記載
の半導体装置の製造方法。 9. The CVD film is a plasma CVD film.
9. The method according to any one of claims 1 to 8, characterized in that
Of manufacturing a semiconductor device of.
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JP3390890B2 true JP3390890B2 (en) | 2003-03-31 |
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