JPH09330976A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method by which the occurrence of a provided via hole which occurs in the via hole of an interlayer insulating film constructed in a multilayered wiring structure can be prevented effectively. SOLUTION: When a via hole is formed in an interlayer insulating film composed of PTEOS-NSG(plasma TEOS-nondoped silicate glass) films 13 and 15 and an SOG film (spin on glass film 14, the via hole is not formed to an aluminum wiring layer 12 by one time of etching, but formed in two steps. In the first step, a via hole 18-1 is formed until the SOG film 14 is exposed in a first etching step and a via hole 18-2 is formed to the wiring layer 12 in a second etching step after coating the SOG film 14 with an acid-resistant thin film (PTEOS-NSG film 30). Since the conductive deposit which is produced by the etching does not adhere directly to the exposed part of the SOG film 14, the film 14 is protected front oxidation by the PTEOS-NSG film 30 during the resist ashing and organic cleaning processes which are performed for removing the deposit after the etching process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a flattening insulating film containing a large amount of water such as SOG (Spin On Glass) as an interlayer film of a multilayer wiring, and more particularly,
The present invention relates to a method of manufacturing a semiconductor device including a step of penetrating such a planarization insulating film and forming a via hole (connection hole) for connecting upper and lower wiring layers.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device having a fine multi-layered wiring, a so-called coated insulating film such as SOG is used as an insulating film having an excellent gap fill characteristic in order to flatten a lower layer wiring. And O ₃ (ozone gas) -TEOS (tetra-ethyl-orthosilicate)
-A TEOS film such as NSG (Non doped Silicate Glass) was used. However, since these materials have a property of containing a large amount of water, when an insulating film such as SOG or O ₃ -TEOS-NSG is exposed on the side wall of the via hole, the via hole portion of the upper wiring layer formed thereafter is oxidized. It is known that a so-called poisoned via phenomenon occurs. This poisoned
The via is a phenomenon in which the wiring inside the via hole is eroded by oxidation, which causes disconnection of the wiring and abnormal increase in resistance in the via hole portion.

Therefore, recently, in order to deal with such inconvenience, SOG having a small water content (for example, SOG containing an organic component) has been developed, and it has been proposed to use it as an interlayer flattening insulating film. . When this type of SOG is used, there is a possibility that the poisoned via phenomenon can be prevented even if the SOG is exposed in the via hole portion.

[0004]

However, in the process of studying the practical application thereof, it has become clear that the above-mentioned new SOG having a low water content has the following problems. Hereinafter, the problem will be described with reference to the drawings.

FIGS. 4 and 5 show a method of forming via holes for multilayer interconnection between layers in a semiconductor device using a new type of SOG having a small moisture content as the interlayer flattening insulating film.

In this method, first, as shown in FIG. 4A, a semiconductor element such as a transistor element (not shown) is used.
On the base insulating film 111 formed so as to cover the first
After forming and patterning the aluminum wiring layer 112 which is the wiring layer of PTEOS (Plasma Teos) -as the first insulating film-
NSG film 113, SOG film 114 having a low moisture content as a planarization insulating film, and PTEO as a second insulating film.
The S-NSG film 115 is sequentially deposited. Then, a resist film 116 that is patterned so as to have an opening 117 in the via hole formation portion is formed.

Next, as shown in FIG. 4B, the PTEOS-NSG film 11 is formed using the resist film 116 as a mask.
5, SOG film 114 and PTEOS-NSG film 113
To form a via hole 118. The etching at this time is sufficiently performed until the aluminum wiring layer 112 is exposed. Therefore, a conductive deposit 119 made of an etching product of the aluminum wiring layer 112 is attached and formed on the sidewall of the via hole 118.

Next, as shown in FIG. 5A, a resist assembling step and an organic cleaning step are performed to remove the conductive deposit 119. However, S with low water content
Since the OG film 114 has a defect that it is easily oxidized by resist assembling or organic cleaning, the exposed SOG film 114 is oxidized and the deteriorated layer 1 containing water.
Form 20.

Next, as shown in FIG. 5B, an aluminum wiring layer 121, which is a second wiring layer, is formed so as to cover the via hole 118, and predetermined patterning is performed. At this time, the aluminum wiring layer 121 is replaced by the altered layer 12
Since it is in contact with 0, aluminum may be oxidized at this contact portion. Therefore, in the end, as shown in FIG.
As shown in (b), there is a possibility that the above-mentioned poisoned via may occur, and it is difficult to sufficiently reduce manufacturing process defects such as disconnection of wiring and abnormal increase of resistance in the via hole portion. It was

The present invention has been made in view of the above problems, and an object thereof is to effectively prevent the occurrence of Poinsunds and vias generated in via holes of an interlayer insulating film of a semiconductor device having a multi-layer wiring structure and to prevent wiring failure. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce

[0011]

According to the method of manufacturing a semiconductor device of the present invention, a connection hole is formed in an interlayer insulating film formed on a first wiring layer, and the connection hole forms the first wiring. In the method for manufacturing a semiconductor device, the first wiring layer and the second wiring layer formed on the interlayer insulating film are connected to each other.
A first insulating film, a planarizing insulating film and a second insulating film on the wiring layer of
Step of sequentially depositing insulating films to form an interlayer insulating film, and of the interlayer insulating films, at least the second insulating film and the flattening insulating film are etched to form a first connection hole. A step of forming an oxidation resistant thin film so as to cover at least the planarization insulating film exposed on the inner wall of the first connection hole, and leaving the thin film of the inner wall of the first connection hole, And etching the thin film at the bottom of the first connection hole and the first insulating film thereunder to form a second connection hole reaching the first wiring layer. As the oxidation resistant thin film, for example, a silicon oxide film formed by plasma chemical vapor deposition using tetra ethyl orthosilicate or metal tungsten is used.

In the method of manufacturing a semiconductor device according to the present invention,
The flattening insulating film exposed on the inner wall of the first connection hole when it is formed is covered with an oxidation resistant thin film, and in this state, the thin film at the bottom of the first connection hole and the first lower film The second insulating layer is etched to reach the first wiring layer.
Connection holes are formed. At that time, conductive deposits are generated by etching of the first wiring layer, but the conductive deposits do not directly adhere to the flattening insulating film on the inner wall of the first connection hole but are formed into an oxidation resistant thin film. To stick on. For this reason,
During the subsequent resist ashing and organic cleaning steps for removing conductive deposits, the flattening insulating film is protected by the oxidation resistant thin film, and deterioration due to oxidation does not occur.
As a result, it is possible to avoid the occurrence of a poisoned via in the via hole portion of the second wiring layer formed thereafter.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 and 2 show a manufacturing process of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1A, an aluminum wiring as a first wiring layer is formed on a base insulating film 11 formed so as to cover a semiconductor element (not shown) such as a transistor element. Form and pattern layer 12. As the aluminum wiring layer 12, for example, an AlSi film made of aluminum and silicon or an AlCu film made of aluminum and copper is used and has a film thickness of, for example, about 500 nm.

Next, as shown in the figure, P as a first insulating film is formed so as to cover the aluminum wiring layer 12.
A TEOS-NSG film 13, a SOG film 14 having a low water content as a planarization insulating film, and a PTEOS-NSG film 15 as a second insulating film are sequentially deposited on the entire surface.
Of these, the PTEOS-NSG film 13 and the PTE
The OS-NSG film 15 is a silicon oxide film containing no impurities, and is a so-called plasma CVD (Chemical Vapor D).
eposition: chemical vapor deposition) using TEOS (tetra ethyl orthosilicate), for example, 30
It is formed to a thickness of about 0 nm. In addition, the SOG film 14 is
It is a silicon oxide film containing an organic component and having a low water content, which is formed by spin-coating a solution of a silicon compound dissolved in an organic solvent, followed by baking. The SOG film 14 is formed to have a film thickness of, for example, about 300 nm.

Next, as shown in the figure, a resist film 16 which is patterned so as to have an opening 17 in a via hole forming portion is formed on the entire surface. The film thickness is, for example, 1.
It is about 2 μm.

Next, as shown in FIG. 1B, the PTEOS-NSG film 15 and the SOG film 14 are etched using the resist film 16 as a mask to form the via hole 18-1 as the first connection hole. Form. The etching at this time is performed to the extent that at least the PTEOS-NSG film 13 is exposed and the aluminum wiring layer 12 is not exposed. As a result of this etching, the SOG film 14 is exposed on the inner sidewall of the via hole 18-1. For the etching, for example, CF ₄ (carbon tetrafluoride) -based gas is used, and the etching conditions for the silicon oxide film-based insulating film are applied.

As described above, the etching is performed so that the aluminum wiring layer 12 is not exposed. If the aluminum wiring layer 12 is also etched, conductive deposits, which will be described later, are directly applied to the exposed portions of the SOG film 14. This is because the SOG film 14 adheres, and the SOG film 14 is oxidized and deteriorated in the resist ashing and organic cleaning steps for removing it.

Next, as shown in FIG.
After removing 6, PTEOS as an oxidation resistant thin film
-The NSG film 30 is formed on the entire surface. This PTEOS-N
The SG film 30 is also the above-mentioned PTEOS-NSG film 13,
Similar to 15, it is formed using TEOS by the plasma CVD method. The film thickness is, eg, about 300 nm. The PTEOS-NSG film 30 has higher resistance to resist ashing and organic cleaning in a post process than the SOG film 14.

Next, as shown in FIG. 2A, a resist film 31 patterned so as to have an opening corresponding to the via hole 18-1 is formed, and the resist film 31 is used as a mask. Aluminum wiring layer 12
The PTEOS-NSG film 13 is etched until the exposed portion, and the via hole 18-2 as the second via hole is formed.
To form As a result, all the PTEOS-NSG film 30 except the inner side wall portion of the via hole 18-1 is removed. At this time, the inside of the PTEOS-NSG film 30 remaining on the inner side wall of the via hole 18-1 and the via hole 1 are removed.
A conductive deposit 19 made of an etching product of the aluminum wiring layer 12 is adhered and formed on the inner wall of 8-2.

Next, as shown in FIG. 2B, a resist assembling process and an organic cleaning process are performed to remove the conductive deposit 19. In this case, the resist ashing is performed under the conditions of, for example, oxygen (O ₂ ) gas of 12000 sccm, high frequency (RF) power of 700 W, and ultimate vacuum degree of 4000 Pa, and organic cleaning is performed using an organic cleaning agent such as an organic amine-based stripping solution. Using, for example, a temperature of 60 ° C,
The time is 60 minutes.

At this time, the SOG film 14 having a low water content
Is covered with the PTEOS-NSG film 30 and is not exposed in the via hole 18-1. Therefore, the SOG film 1
No. 4 is protected by the PTEOS-NSG film 30 having high oxidation resistance even in the resist assembling step and the organic cleaning step, and deterioration due to oxidation does not occur unlike the conventional case.

Next, as shown in FIG. 3, the via hole 1
The aluminum wiring layer 21 which is the second wiring layer is formed so as to cover 8-2, and a predetermined patterning is performed. At this time, the aluminum wiring layer 21 is covered with the via hole 18-.
2 PTEOS-N with high oxidation resistance on the inner wall surface
It only contacts the SG film 30 and the PTEOS-NSG film 13, and does not directly contact the SOG film 14. Therefore, the aluminum wiring layer 12 is less likely to be oxidized in this via hole portion.

As described above, in this embodiment, the PTEO
S-NSG film 13, SOG film 14 and PTEOS-N
When a via hole is formed in the interlayer insulating film made of the SG film 15, the via hole reaching the aluminum wiring layer 12 which is the first wiring layer is not formed by one etching step, but first, in the first stage etching, After forming a via hole at least up to the position where the SOG film 14 is exposed, the exposed SOG film 14 is covered with a thin film (PTEOS-NSG film 30) having high oxidation resistance, and aluminum wiring is used in the second-stage etching. Since the via hole reaching the layer 12 is formed,
Conductive deposits 19 produced in the second stage etching
Does not directly adhere to the exposed portion of the SOG film 14.
Therefore, even during the subsequent resist ashing and organic cleaning steps for removing the conductive deposits 19, the cross-section of the SOG film 14 is protected by the thin film (PTEOS-NSG film 30) having high oxidation resistance. Therefore, alteration due to oxidation is prevented without being directly exposed to oxidizing gas or organic cleaning agent. As a result, it is possible to prevent the occurrence of pointed vias in the via hole portion, and reduce manufacturing process defects such as disconnection of wiring and abnormal increase in resistance.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to this embodiment, and can be variously modified within an equivalent range.

For example, in the above-described embodiment, the flattening insulating film is an SO containing an organic component and having a small water content.
Although the case of applying it to the G film has been described, it can also be applied to an ordinary SOG film having a high water content. Further, the present invention is not limited to the SOG film, and can be applied to other flattening insulating films having a large water content, such as a Teos film such as O ₃ -TEOS-NSG.

Further, in the above embodiment, the description has been made on the assumption that the insulating film called PTEOS-NSG film is used as the thin film having high oxidation resistance, but the insulating film is not limited to the insulating film as long as it has high oxidation resistance. It is also possible to use a conductive thin film of, for example, tungsten metal.

[0029]

As described above, according to the method of manufacturing a semiconductor device of the present invention, when the first connection hole which does not reach the first generation layer is formed, the flatness exposed on the inner wall of the first connection hole is formed. A second connection hole that reaches the first wiring layer by etching the thin film at the bottom of the first connection hole and the first insulation film below it in a state in which the oxidized insulation film is covered with the oxidation resistant thin film. Therefore, the conductive deposit generated by the etching of the first wiring layer does not directly adhere to the flattening insulating film on the inner wall of the first connection hole, but is formed of the oxidation-resistant thin film. Will adhere to the top. Therefore, during the subsequent resist ashing for removing the conductive deposits and the organic cleaning process, the flattening insulating film can be protected by the oxidation resistant thin film, and deterioration due to oxidation can be prevented. As a result, it is possible to avoid the occurrence of a poisoned via in the via hole portion of the second wiring layer formed later,
It is possible to reduce manufacturing process defects such as disconnection of wiring and abnormal increase in resistance.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a part of a process representing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating each step following FIG. 1;

FIG. 3 is a cross-sectional view showing a process following on the process shown in FIG.

FIG. 4 is a cross-sectional view showing a step in a conventional method for manufacturing a semiconductor device.

FIG. 5 is a sectional view illustrating each step following FIG. 4;

[Description of Reference Signs] 11 ... Base insulating layer, 12 ... Aluminum wiring layer (first wiring layer), 21 ... Aluminum wiring layer (second wiring layer), 13 ... PTEOS-NSG film (first insulating film) ,
14 ... SOG film (planarization insulating film), 15 ... PTEOS-
NSG film (second insulating film), 16, 31 ... Resist, 1
8-1 ... Via hole (first connection hole), 18-2 ... Via hole (second connection hole), 19 ... Conductive deposit, 30 ...
PTEOS-NSG film (oxidation-resistant thin film)

Claims (3)

[Claims] 1. A connection hole is formed in an interlayer insulating film formed on a first wiring layer, and the connection hole forms a second wiring layer on the first wiring layer and the interlayer insulating film. In the method for manufacturing a semiconductor device, the first insulating film, the planarizing insulating film, and the second insulating film are sequentially deposited on the first wiring layer to form the interlayer insulating film. A step of forming a film; a step of etching at least the second insulating film and the flattening insulating film in the interlayer insulating film to form a first connection hole; at least the first connection hole A step of forming an oxidation resistant thin film so as to cover the planarization insulating film exposed on the inner wall of the first connection hole, and a thin film on the bottom of the first connection hole while leaving the thin film on the inner wall of the first connection hole. And etching the first insulating film thereunder to form the first wiring. The method of manufacturing a semiconductor device which comprises a step of forming a second contact hole reaching. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxidation resistant thin film is a silicon oxide film formed by plasma chemical vapor deposition using tetra ethyl orthosilicate. . 3. The method of manufacturing a semiconductor device according to claim 1, wherein the oxidation resistant thin film is made of metal tungsten.