KR920000629B1 - Manufacturing method of semiconductor device using etch-back process - Google Patents

Manufacturing method of semiconductor device using etch-back process Download PDF

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KR920000629B1
KR920000629B1 KR1019880007467A KR880007467A KR920000629B1 KR 920000629 B1 KR920000629 B1 KR 920000629B1 KR 1019880007467 A KR1019880007467 A KR 1019880007467A KR 880007467 A KR880007467 A KR 880007467A KR 920000629 B1 KR920000629 B1 KR 920000629B1
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metal layer
photoresist
semiconductor device
substrate
interlayer insulating
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KR900000988A (en
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최규현
이형섭
육태윤
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삼성전자 주식회사
강진구
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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Abstract

The manufacturing method for semiconductor device consists of three unit processes: (A) the first process forming contact area on semiconductor substrate (11), the second process forming patterns after coating the first metal layer (15) on the contact area, and the third process forming successively interlayer insulation film and the second metal layer on the substrate (11). Between second and third processes three-stepwise operation is continuously repeated more than twice: the first step forming successively insulation film (16) and photoresist (17) on the substrate (11), the second step etching photoresist (17), and the third step etching back (17) and (16) in the ratio of 1:1.

Description

에치백 공정을 이용한 반도체 장치의 제조방법Method of manufacturing semiconductor device using etch back process

제1a도-제1e도는 종래 반도체 장치의 콘택부분을 평탄화 하는 반도체 장치의 제조공정도.1A to 1E are manufacturing process diagrams of a semiconductor device for planarizing a contact portion of a conventional semiconductor device.

제2a-제2h도는 본 발명에 따른 제조공정도.2a-2h is a manufacturing process diagram according to the present invention.

본 발명은 반도체 장치의 제조방법에 관한 것으로 특히 콘택부분과 그 이외의 단차부분에서 스텝커버리지(stepcoverage)를 향상시키기 위한 개선된 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an improved method of manufacturing a semiconductor device for improving step coverage in contact portions and other stepped portions.

반도체 장치가 초고집적화로 진행됨에 따라 접촉 부위(Contact)의 크기는 줄어드는 반면 단차는 일정하게 유지되므로 단차부분, 특히 다층배선구조의 반도체 장치에서 스텝커버리지(Stepcoverage)의 악화로 금속배선의 끊어짐이나 금속의 이주현상(Electromigration) 또는 금속배선간의 단락으로 인한 소자의 신뢰성 저하등 여러문제가 야기되고 있다.As the semiconductor device progresses to ultra high integration, the contact size decreases while the step remains constant. Therefore, in the semiconductor device having a stepped portion, in particular, in a semiconductor device having a multi-layered structure, the breakage of the metal wiring or the metal may occur. Many problems are caused, such as the reliability of the device due to the electromigration or short circuit between metal wires.

제1a-제1e도는 종래 방법으로 평탄화를 실시하여 다층배선 반도체 장치에서 상기 문제를 해결하고자 하는 반도체 장치의 제조공정을 순서대로 나타낸 일실시예의 도면이다.1A to 1E are diagrams of one embodiment sequentially showing a manufacturing process of a semiconductor device to solve the problem in a multilayer wiring semiconductor device by planarization by a conventional method.

제1a도를 참조하면 실리콘 반도체 기판(1) 상면에 게이트산화막(2)을 성장시킨 후 다결정 실리콘층을 형성한다. 그후 통상의 사진식각 공정(Photolithographic Process)으로 다결정 실리콘 게이트(3)를 형성한 후 금속 배선층과의 절연유지를 위하여 상기 기판(1) 상면에 절연막(4)을 성장시킨다. 그후 통상의 사진 식각 공정으로 콘택(Contact)영역을 형성하며 제1금속층(5)을 증착하고 사진식각공정으로 패턴을 형성한다.Referring to FIG. 1A, after the gate oxide film 2 is grown on the silicon semiconductor substrate 1, a polycrystalline silicon layer is formed. After that, the polycrystalline silicon gate 3 is formed by a general photolithographic process, and then the insulating film 4 is grown on the upper surface of the substrate 1 to maintain insulation with the metal wiring layer. Thereafter, a contact region is formed by a general photolithography process, a first metal layer 5 is deposited, and a pattern is formed by a photolithography process.

그다음 제1금속층(5)의 패턴상에 이후 형성될 제2금속층과의 절연을 위하여 제1층간절연막(6)을 도포하고 그위에 포토레지스트(7) 또는 SOG(spin on glass)등을 도포하면 제1b도와 같다.Then, the first interlayer insulating film 6 is applied on the pattern of the first metal layer 5 to insulate the second metal layer to be formed later, and the photoresist 7 or spin on glass (SOG) is applied thereon. Same as FIG. 1b.

그다음 상기 제1층간절연막(6)의 소정 영역이 충분히 노출되도록 상기 포토레지스트(7)를 소정 두께 식각하면 제1c도와 같다.Subsequently, the photoresist 7 is etched by a predetermined thickness so that a predetermined region of the first interlayer insulating film 6 is sufficiently exposed, as illustrated in FIG. 1C.

그다음 상기 포토레지스터(7)와 제1층간절연막(6)이 거의 1:1의 식각비를 갖도록 에치백(Etch Back)을 실시하여 평탄화를 진행하면 제1d도와 같다.Next, when the photoresist 7 and the first interlayer insulating film 6 are etched back to have an etch ratio of about 1: 1, the planarization is performed as shown in FIG. 1D.

그다음 기판상면에 남아있는 포토레지스트(7)를 제거하고 이후 형성되는 제2금속층과의 절연을 위하여 제2층간절연막(8)을 도포하면 제1e도와 같다.Then, the photoresist 7 remaining on the upper surface of the substrate is removed, and the second interlayer insulating film 8 is applied to insulate the second metal layer formed thereafter, as shown in FIG. 1E.

상기와 같은 경우 제1금속층과 제1금속층 사이의 간격이 좁고 두께 차이에 의해 단차가 심한 경우 에치백후에도 평탄화가 잘 이루어지지 않고 음의 계단(Negative step)이 형성된다. 특히 콘택부분의 경우는 완전히 음의 경사(Negative Slope)를 형성하거나 제1e도와 같이 동공(Void)(9)을 형성하게 된다.In such a case, when the gap between the first metal layer and the first metal layer is narrow and the step is severe due to the difference in thickness, even after etch back, the planarization is poor and a negative step is formed. Particularly, in the case of the contact portion, a negative slope is completely formed, or a pupil 9 is formed as shown in FIG. 1e.

그러므로 제2금속층을 형성할 경우 스텝커버리지의 문제가 더욱 심각하고 층간 절연막의 두께 차이에 의해 비아(Via)식각시 문제가 된다.Therefore, when the second metal layer is formed, the problem of step coverage becomes more serious, and a problem in etching via is caused by the difference in thickness of the interlayer insulating layer.

따라서 본 발명의 목적은 제1금속층과 제1금속층 사이의 간격이 좁고 단차가 심한 경우 평탄화 실시후에 발생하는 음의 경사를 줄이고, 제1금속층과 제2금속층 사이의 층간절연막의 두께 차이를 줄여 비아(Via)식각을 용이하게 하는 반도체 장치의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to reduce the inclination of the negative signal generated after the planarization when the gap between the first metal layer and the first metal layer is narrow and the step is severe, and to reduce the difference in thickness of the interlayer insulating film between the first metal layer and the second metal layer. The present invention provides a method for manufacturing a semiconductor device that facilitates etching.

이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2a-제2h도는 본 발명에 따른 실시예의 제조공정도로서, 모오스 전계효과 트랜지스터의 일부를 실시예로 도시하였으나 본 발명은 반도체 장치의 콘택부위 또는 어떠한 단차 부위에서도 이용될수 있음을 유의하여야 한다.2A to 2H are manufacturing process diagrams of an embodiment according to the present invention, although some of the MOS field effect transistors are shown as an embodiment, it should be noted that the present invention can be used in the contact portion or any step portion of the semiconductor device.

제2a도를 참조하면 실리콘 반도체 기판(11)위에 게이트 산화막(12)과 다결정 실리콘층을 순차적으로 형성한 후 통상의 사진식각 공정으로 다결정 실리콘 게이트(13)를 형성한다. 그후 금속 배선층과의 절연유지를 위하여 상기 기판상면에 절연막(14)을 성장시키고 사진식각 공정으로 콘택영역(Contact Area)을 형성하며 제1금속층(15)을 증착하고 사진 식각공정으로 패턴을 형성한다. 그 다음 상기 제1금속층의 패턴(15)상에 이후 형성될 제2금속층과의 절연을 위하여 제1층간절연막(16)을 도포하고 그위에 포토레지스트(17)를 도포하면 제2b도와 같다.Referring to FIG. 2A, the gate oxide layer 12 and the polycrystalline silicon layer are sequentially formed on the silicon semiconductor substrate 11, and then the polycrystalline silicon gate 13 is formed by a general photolithography process. After that, the insulating layer 14 is grown on the upper surface of the substrate to maintain insulation with the metal wiring layer, a contact area is formed by a photolithography process, a first metal layer 15 is deposited, and a pattern is formed by a photolithography process. . Next, the first interlayer insulating film 16 is applied on the pattern 15 of the first metal layer to insulate the second metal layer to be formed later, and the photoresist 17 is applied thereon, as shown in FIG. 2B.

그다음 상기 제1포토레지스트(17)를 제1층간 절연막(16)의 아랫부분까지 식각시켜 상당부분의 제1층간절연막(16)을 드러나게 하면 제2c도와 같다.Next, the first photoresist 17 is etched to the lower portion of the first interlayer insulating layer 16 to expose a substantial portion of the first interlayer insulating layer 16 as shown in FIG. 2C.

그다음 제1포토레지스트(17)와 제2층간 절연막(16)을 1 : 1의 비율로 에치백하면 제2d도와 같이 형성된다.Then, the first photoresist 17 and the second interlayer insulating film 16 are etched back in a ratio of 1: 1 to form the second photoresist.

그다음 제2e도에 도시한 바와같이 상기 기판(17) 상면에 제2층간절연막(18)을 도포하고 그 상면에 제2포토레지스트(19)를 도포한다.Then, as shown in FIG. 2E, a second interlayer insulating film 18 is applied on the upper surface of the substrate 17, and a second photoresist 19 is applied on the upper surface.

그다음 상기 제2포토레지스트(19)를 소정 두께 식각하여 제2f도와 같이 형성하는데 이때 상기 제2포토레지스트(19)의 식각정도는 제조되는 반도체 장치가 요구하는 평탄화 정도에 따라 결정될수 있다.The second photoresist 19 is then etched to a predetermined thickness to form a second thickness as shown in FIG. 2F, where the etching degree of the second photoresist 19 may be determined according to the degree of planarization required by the semiconductor device to be manufactured.

그다음 상기 제2f도와 같이, 식각된 제1층간 절연막(16)과 제2층간절연막(18)을 합한 제3층간절연막(18a)이 노출된 기판을 제2포토레지스트와 제3층간 절연막의 식각비가 1 : 1이 되도록 에치백한다. 그 결과 제2g도와 같이 완만한 경사를 갖는 평탄한 기판면이 형성된다.Next, as shown in FIG. 2F, the etch rate of the second photoresist and the third interlayer insulating layer may be changed to a substrate on which the third interlayer insulating layer 18a including the etched first interlayer insulating layer 16 and the second interlayer insulating layer 18 is exposed. Etch back to 1: 1. As a result, a flat substrate surface having a gentle slope as shown in FIG. 2G is formed.

그다음 제1금속층(15)과 이후 형성될 제2금속층과 절연유지를 위하여, 식각된 제3층간 절연막(18b)상에 제4층간절연막(20)을 도포하면 제2h도와 같이 형성된다.Then, when the fourth interlayer insulating film 20 is coated on the etched third interlayer insulating film 18b to maintain insulation between the first metal layer 15 and the second metal layer to be formed thereafter, it is formed as shown in FIG. 2H.

통상적으로 다층배선구조를 이용하는 반도체 장치의 제조공정에서는 제1금속층과 제2금속층 사이의 층간절연막의 평탄화 정도에 따라 제2금속층의 스텝커버리가 결정되며 수율(Yield)과 신뢰성에 영향을 미치게 되는데 본 발명은 제2h도에 도시한 바와같이 콘택부분에서 동공(Void)이 형성되지 않을뿐 아니라 스텝커버리가 개선된다.In general, in the manufacturing process of a semiconductor device using a multi-layered wiring structure, the step coverage of the second metal layer is determined by the degree of planarization of the interlayer insulating film between the first metal layer and the second metal layer, which affects yield and reliability. As shown in FIG. 2H, not only the voids are formed in the contact portion, but also the step coverage is improved.

본 발명의 일실시예에서는 층간 절연막과 포토레지스트를 형성한 후 식각하는 공정을 2회 실시하였으나 본 발명의 다른 실시예에서는 2회 이상 실시할 수도 있다.In an embodiment of the present invention, the process of etching after forming the interlayer insulating film and the photoresist is performed twice, but in another embodiment of the present invention, it may be performed twice or more.

상술한 바와같이 본 발명은 다층배선구조의 반도체 장치의 제조방법에 있어서 제1금속층을 형성한 후 층간절연막과 포토레지스트를 도포한 다음 식각하는 공정을 적어도 2회 이상 반복함으로써 금속층간의 층간절연막이 양의 경사로 침적되도록 하였다. 그 결과 제2금속층의 스텝커버리지를 향상시키는 효과가 있다. 또한 콘택부분의 동공 형성을 방지함으로써 이 동공이 반도체 장치에 미칠수 있는 영향을 줄여주며 비아(Via)식각시 층간 절연막 단차를 줄여 수율과 신뢰성이 향상되는 이점도 있다.As described above, in the method of manufacturing a semiconductor device having a multi-layered wiring structure, the interlayer insulating film between the metal layers is formed by repeating at least two or more steps after forming the first metal layer, applying the interlayer insulating film and the photoresist, and then etching the same. It was allowed to deposit on a positive slope. As a result, there is an effect of improving the step coverage of the second metal layer. In addition, by preventing the formation of holes in the contact portion, the effect of the holes on the semiconductor device can be reduced, and the yield and reliability can be improved by reducing the interlayer insulating film step during via etching.

Claims (2)

반도체 기판(11)상의 소정 영역에 콘택영역을 형성하는 제1공정과, 상기 기판 상면에 상기 콘택영역에 접촉하는 제1금속층(15)을 도포한 후, 패턴을 형성하는 제2공정과, 상기 기판(11) 상면에 층간절연막과 제2금속층을 순차적으로 형성하는 제3공정을 구비하는 에치백 공정을 이용한 반도체 장치의 제조 방법에 있어서, 상기 제2공정과 제3공정 사이에 상기 기판(11) 상면에 절연막(16)과 포토레지스트(17)를 순차적으로 형성하는 제1단계와, 상기 포토레지스트(17)를 소정 두께 식각하는 제2단계와, 상기 기판(11) 상면의 포토레지스트(17)와 절연막(16)을 에치백하는 제3단계를 연속으로 적어도 2회 이상 반복 실시함을 특징으로 하는 에치백 공정을 이용한 반도체 장치의 제조방법.A first step of forming a contact region in a predetermined region on the semiconductor substrate 11, a second step of forming a pattern after applying the first metal layer 15 in contact with the contact region on the upper surface of the substrate, and A method of manufacturing a semiconductor device using an etch back process comprising a third step of sequentially forming an interlayer insulating film and a second metal layer on an upper surface of the substrate 11, wherein the substrate 11 is disposed between the second step and the third step. A first step of sequentially forming the insulating film 16 and the photoresist 17 on the upper surface, a second step of etching the photoresist 17 by a predetermined thickness, and the photoresist 17 on the upper surface of the substrate 11. ) And the third step of etching back the insulating film 16 is repeated at least twice in succession. 제1항에 있어서, 상기 에치백 공정은 식각비가 1 : 1임을 특징으로 하는 반도체 장치의 제조방법.The method of claim 1, wherein the etching back process comprises an etching ratio of about 1: 1.
KR1019880007467A 1988-06-21 1988-06-21 Manufacturing method of semiconductor device using etch-back process KR920000629B1 (en)

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