KR0172505B1 - Method of forming contact on semiconductor device - Google Patents
Method of forming contact on semiconductor device Download PDFInfo
- Publication number
- KR0172505B1 KR0172505B1 KR1019950043628A KR19950043628A KR0172505B1 KR 0172505 B1 KR0172505 B1 KR 0172505B1 KR 1019950043628 A KR1019950043628 A KR 1019950043628A KR 19950043628 A KR19950043628 A KR 19950043628A KR 0172505 B1 KR0172505 B1 KR 0172505B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- film
- layer
- conductive layer
- contact
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Abstract
본 발명은 다층 구조의 콘택 형성시 콘택 저항을 크게 감소시키고, 평탄도를 증대시킬 수 있는 반도체 소자의 콘택 형성방법에 관한 것으로, 반도체 소자 제조공정 중 소자와 소자간의 전기적 연결을 위한 콘택 형성방법에 있어서, 제1도전층, 제2도전층을 차례로 형성하는 제1단계; 상기 제2도전층 상부에 감광막패턴을 형성한 다음, 이를 마스크로 사용한 식각공정을 통해 상기 제2금속층을 식각하는 제2단계; 상기 제1단계 및 제2단계에 의한 구조의 전체 상부에 감광막이 없는 지역에만 선택적으로 증착되는 LPD(Liquid Phase Dielectrics)막을 형성하는 제3단계; 상기 감광막패턴을 제거한 다음, 평탄화 특성이 우수한 평탄화절연막을 형성하는 제4단계; 및 상기 평탄화절연막을 에치-백(etch-back)하여 평탄화한 다음, 전체 상부에 제3금속층을 형성하는 제5단계를 포함하여 이루어지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device capable of greatly reducing contact resistance and increasing flatness when forming a multilayer structure contact. A first step of sequentially forming a first conductive layer, the second conductive layer; Forming a photoresist pattern on the second conductive layer and then etching the second metal layer through an etching process using the photoresist pattern as a mask; A third step of forming a LPD film (Liquid Phase Dielectrics) film selectively deposited only in a region where no photoresist film is formed over the entire structure of the first and second structures; Removing the photoresist pattern, and then forming a planarization insulating film having excellent planarization characteristics; And a fifth step of etching and planarizing the planarization insulating layer, and then forming a third metal layer over the entire surface.
Description
제1a도 내지 제1d도는 본 발명의 일실시예에 따른 콘택 형성과정을 나타내는 단면도.1A to 1D are cross-sectional views illustrating a process for forming a contact according to an embodiment of the present invention.
제2도는 본 발명의 다른 실시예에 따른 콘택 형성 후의 단면도.2 is a cross-sectional view after contact formation according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 절연막1 silicon substrate 2 insulating film
23,24,28 : 금속막 5 : 감광막패턴23, 24, 28: metal film 5: photoresist pattern
6,7 : LPD막 29 : 접착력 증가층6,7 LPD film 29: adhesion increasing layer
본 발명은 반도체 소자 제조공정 중 소자와 소자간의 전기적 연결을 위한 콘택 형성방법에 관한 것으로, 특히 다층구조의 콘택 형성시 평탄도를 증대시키기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact for electrical connection between a device and a device during a semiconductor device manufacturing process. More particularly, the present invention relates to a method for increasing flatness when forming a multi-layer contact.
종래의 소자간 콘택 방법은 특히, 다층금속막(multi-level metallization)간의 콘택시 층간절연막 사이에 미세 콘택홀을 형성한 다음, 도전층 증착 및 마스크 공정을 통해 상기 금속막을 콘택하는 방법이 주로 이용되고 있다.In the conventional inter-device contact method, a method of forming a fine contact hole between inter-layer insulating films during contact between multi-level metallization and then contacting the metal film through a conductive layer deposition and a mask process is mainly used. It is becoming.
그러나, 소자의 집적도가 크게 증대됨에 따라 콘택홀의 크기도 미세해지고, 이에 따라 상기 종래방법은 도전층의 스텝커버리지(stepcoverage)가 크게 떨어지고, 접촉저항이 크게 증대되어 소자 불량을 초래하는 등의 문제점이 따랐다.However, as the degree of integration of the device is greatly increased, the size of the contact hole is also reduced. Accordingly, the conventional method has a problem that the step coverage of the conductive layer is greatly decreased, and the contact resistance is greatly increased, resulting in device defects. Followed.
상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 본 발명은 다층 구조의 콘택 형성시 콘택 저항을 크게 감소시키고, 평탄도를 증대시킬 수 있는 반도체 소자의 콘택 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the problems of the prior art as described above is to provide a method for forming a contact of a semiconductor device that can greatly reduce the contact resistance and increase the flatness when forming a multi-layer contact.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자 제조공정 중 소자와 소자간의 전기적 연결을 위한 콘택 형성방법에 있어서, 제1도전층, 제2도전층을 차례로 형성하는 제1단계; 상기 제2도전층 상부에 감광막패턴을 형성한 다음, 이를 마스크로 사용한 식각공정을 통해 상기 제2금속층을 식각하는 제2단계; 상기 제1단계 및 제2단계에 의한 구조의 전체 상부에 감광막이 없는 지역에만 선택적으로 증착되는 LPD(Liquid Phase Dielectrics)막을 형성하는 제3단계; 상기 감광막패턴을 제거한 다음, 평탄화 특성이 우수한 평탄화절연막을 형성하는 제4단계; 및 상기 평탄화절연막을 에치-백(etch-back)하여 평탄화한 다음, 전체 상부에 제3금속층을 형성하는 제5단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a contact for electrical connection between a device and a device during a semiconductor device manufacturing process, comprising: a first step of sequentially forming a first conductive layer and a second conductive layer; Forming a photoresist pattern on the second conductive layer and then etching the second metal layer through an etching process using the photoresist pattern as a mask; A third step of forming a LPD film (Liquid Phase Dielectrics) film selectively deposited only in a region where no photoresist film is formed over the entire structure of the first and second structures; Removing the photoresist pattern, and then forming a planarization insulating film having excellent planarization characteristics; And a fifth step of etching and planarizing the planarization insulating layer, and then forming a third metal layer over the entire surface.
이하, 첨부된 도면 제1a도 내지 제1d도 및 제2도를 참조하여 본 발명의 실시예를 상술한다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1A to 1D and 2.
제1a도 내지 제1d도는 본 발명의 일실시예에 따른 콘택 형성과정을 나타내는 단면도로서, 먼저 제1a도에 도시된 바와같이 실리콘기판(1)에 절연막(2), 제1금속막(3) 및 제2금속막(4)을 차례로 형성한 다음, 상기 제2금속막(4) 상부에 감광막패턴(5)을 형성하고 이를 마스크로 사용한 식각공정을 통해 상기 제2금속막(4)을 식각한다.1A to 1D are cross-sectional views illustrating a process for forming a contact according to an embodiment of the present invention. First, as shown in FIG. 1A, an insulating film 2 and a first metal film 3 are formed on a silicon substrate 1. And forming the second metal film 4 in sequence, and then forming the photoresist pattern 5 on the second metal film 4 and etching the second metal film 4 through an etching process using the photoresist pattern 5 as a mask. do.
이어서, 제1b도에서 상기 제1a도에 의한 구조의 전체 상부에 감광막이 없는 지역에만 선택적으로 증착되는 LPD(Liquid Phase Dielectrics)막(6)을 증착한다.Subsequently, in FIG. 1B, a LPD (Liquid Phase Dielectrics) film 6 which is selectively deposited only in an area where there is no photoresist film is deposited over the entire structure of FIG. 1A.
계속해서, 상기 감광막패턴(5)을 제거한 다음, 다시 LPD막(7)을 증착하여 제1c도에 도시된 바와같은 단면을 형성한다. 이때, 상기 LPD막(7) 대신 평탄화 특성이 우수한 SOG(pin On Glass)막을 코팅할 수도 있다.Subsequently, the photosensitive film pattern 5 is removed, and then the LPD film 7 is deposited again to form a cross section as shown in FIG. 1C. In this case, a pin on glass (SOG) film having excellent planarization property may be coated instead of the LPD film 7.
끝으로, 제1d도에 도시된 바와같이 상기 LPD막(7)을 에치-백(etch-back)하여 평탄화한 다음, 제3금속막(8)을 형성하여 상기 제1금속막(3), 제2금속막(4), 제3금속막(8)을 서로 콘택한다.Finally, as shown in FIG. 1d, the LPD film 7 is etched back to be flattened, and a third metal film 8 is formed to form the first metal film 3, The second metal film 4 and the third metal film 8 are in contact with each other.
한편, 제2도는 본 발명의 다른 실시예에 따른 콘택 형성 후의 단면도로서, 제1금속막(23)과 제3금속막(28)간의 접착력을 증대시키기 위해 상기 제2금속막(24)의 상부 및 하부에 TiN막 또는 TiW막 등의 접착력 증가층(29)을 형성한 상태를 나타낸다.FIG. 2 is a cross-sectional view after forming a contact according to another embodiment of the present invention, and the upper portion of the second metal film 24 to increase the adhesion between the first metal film 23 and the third metal film 28. And an adhesive force increasing layer 29 such as a TiN film or a TiW film formed below.
상기와 같이 이루어지는 본 발명은 다층 구조의 콘택 형성시 콘택 저항을 크게 감소시키고, 평탄도를 증대시키는 효과를 갖는다.The present invention made as described above has the effect of greatly reducing contact resistance and increasing flatness when forming a multilayer structure of contact.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043628A KR0172505B1 (en) | 1995-11-24 | 1995-11-24 | Method of forming contact on semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043628A KR0172505B1 (en) | 1995-11-24 | 1995-11-24 | Method of forming contact on semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970030358A KR970030358A (en) | 1997-06-26 |
| KR0172505B1 true KR0172505B1 (en) | 1999-03-30 |
Family
ID=19435656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950043628A KR0172505B1 (en) | 1995-11-24 | 1995-11-24 | Method of forming contact on semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172505B1 (en) |
-
1995
- 1995-11-24 KR KR1019950043628A patent/KR0172505B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970030358A (en) | 1997-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5966632A (en) | Method of forming borderless metal to contact structure | |
| KR0172505B1 (en) | Method of forming contact on semiconductor device | |
| US6117787A (en) | Planarization method for a semiconductor device | |
| KR100363642B1 (en) | Method for forming contact hole of semiconductor devices | |
| KR100230730B1 (en) | Semiconductor element multi-layer metal line manufacturing method | |
| KR100668221B1 (en) | Method for Manufacturing MIM Capacitor | |
| JPH11186274A (en) | Dual damascene technique | |
| US6284645B1 (en) | Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process | |
| KR100257762B1 (en) | Method for manufacturing metal wiring of semiconductor device | |
| KR100214067B1 (en) | Manufacture of semiconductor device | |
| KR920001913B1 (en) | Method of fabricating semiconductor device with pattern layer | |
| KR920010126B1 (en) | Multi-layer metal wiring method of semiconductor elements | |
| JPH03148130A (en) | Manufacture of semiconductor device | |
| KR920000629B1 (en) | Manufacturing method of semiconductor device using etch-back process | |
| JPH0758204A (en) | Manufacture of semiconductor device | |
| KR100226755B1 (en) | Interconnection structure and manufacturing method of the same in semiconductor device | |
| KR100271402B1 (en) | A manufacturing method of contact holes for semiconductor devices | |
| KR970003718B1 (en) | Method of forming the metal wiring | |
| KR100249130B1 (en) | Method for forming metal line of semiconductor device | |
| KR100194600B1 (en) | Manufacturing method of multilayer metal wiring | |
| KR100265835B1 (en) | A method for forming metal wire in semiconductor device | |
| KR100365937B1 (en) | Method for forming copper metal wiring | |
| KR100459062B1 (en) | Method for forming a contact hole in a semiconductor manufacturing process | |
| KR100248805B1 (en) | A method for forming metal wire in semiconductor device | |
| KR100275127B1 (en) | Method of planarization multilayer metal line of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20090922 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |