KR100459062B1 - Method for forming a contact hole in a semiconductor manufacturing process - Google Patents
Method for forming a contact hole in a semiconductor manufacturing process Download PDFInfo
- Publication number
- KR100459062B1 KR100459062B1 KR10-2001-0086940A KR20010086940A KR100459062B1 KR 100459062 B1 KR100459062 B1 KR 100459062B1 KR 20010086940 A KR20010086940 A KR 20010086940A KR 100459062 B1 KR100459062 B1 KR 100459062B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- forming
- photoresist
- layer
- metal layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 239000010410 layer Substances 0.000 claims description 33
- 239000011229 interlayer Substances 0.000 claims description 10
- 230000008054 signal transmission Effects 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 제조 공정에서의 콘택트 홀 형성 방법에 관한 것으로, 기판 상부에 하부 금속층과 IMD층을 형성하는 단계와, 하부 금속층과 IMD층 상부에 제 1 포토레지스트를 도포하여 제 1 포토레지스트 패턴을 형성한 후 IMD층을 기설정 범위까지 식각하여 제 1 콘택트 홀을 형성하는 단계와, 제 1 콘택트 홀과 IMD층 상부에 제 2 포토레지스트를 도포하여 제 2 포토레지스트 패턴을 형성하는 단계와, 제 2 포토레지스트 패턴으로 IMD층과 하부 금속층을 오픈하여 제 2 콘택트 홀을 형성하는 단계와, 오픈된 제 2 콘택트 홀 내에 금속을 매립하여 금속층을 형성하는 단계를 포함한다. 본 발명에 의하면, 콘택트 홀을 이중화함으로써 신호 전달 신뢰성 향상에 의한 높은 반도체 수율을 구현할 수 있는 효과가 있다.The present invention relates to a method for forming a contact hole in a semiconductor manufacturing process, the method comprising: forming a lower metal layer and an IMD layer on a substrate, and applying a first photoresist on the lower metal layer and an IMD layer to form a first photoresist pattern. Forming a first contact hole by etching the IMD layer to a predetermined range after formation, and forming a second photoresist pattern by applying a second photoresist on the first contact hole and the IMD layer; Forming a second contact hole by opening the IMD layer and the lower metal layer with a second photoresist pattern; and forming a metal layer by filling a metal in the open second contact hole. According to the present invention, it is possible to realize a high semiconductor yield by improving the signal transmission reliability by redundancy of the contact hole.
Description
본 발명은 반도체 제조 공정에서의 콘택트 홀 형성 기술에 관한 것으로, 특히, 콘택트 홀을 이중화하여 소자의 전기적 신뢰성을 향상시키도록 한 반도체 제조공정에서의 콘택트 홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for forming a contact hole in a semiconductor manufacturing process, and more particularly, to a method for forming a contact hole in a semiconductor manufacturing process in which contact holes are doubled to improve electrical reliability of the device.
콘택트 홀 형성 공정은 금속층간의 연결을 위해 사용되는 반도체 공정 중 하나로서, 반도체 금속 배선 형성 공정에서의 절연층을 소정 부분 노출시켜 상부 금속층과 하부 금속층을 연결하는 공정을 일컫는다.The contact hole forming process is one of semiconductor processes used to connect the metal layers, and refers to a process of connecting the upper metal layer and the lower metal layer by exposing a portion of the insulating layer in the semiconductor metal wiring forming process.
이러한 상부 금속층과 하부 금속층을 연결하기 위해서는 콘택트 홀을 충진하는 과정이 필요한데, 통상, 갭필(gap fill) 능력이 우수한 CVD W(텅스텐)법이 사용된다.In order to connect the upper metal layer and the lower metal layer, a process of filling a contact hole is required. In general, a CVD W (tungsten) method having excellent gap fill capability is used.
도 1a 내지 도 1c는 이러한 CVD W를 이용한 통상의 콘택트 홀 형성 과정을 설명하기 위한 도면이다.1A to 1C are diagrams for explaining a conventional contact hole forming process using the CVD W.
먼저, 도 1a에 도시한 바와 같이, 금속층(10)과 층간 절연막(IMD:Inter Metallic Dielectric)(12)이 증착된 웨이퍼상에 포토레지스트(14)를 도포한 후 사진 공정에 의해 포토레지스트 패턴을 형성한다.First, as shown in FIG. 1A, a photoresist 14 is coated on a wafer on which a metal layer 10 and an interlayer insulating film (IMD) are deposited, and then a photoresist pattern is formed by a photolithography process. Form.
그런 다음, 콘택트 홀을 형성한 후 포토레지스트(14)를 제거하는데, 이러한 콘택트 홀은, 예컨대, RIE(Reactive Ion Etching : 반응성 이온 에칭) 기법에 의해 형성될 수 있다(도 2b).The photoresist 14 is then removed after forming the contact holes, which may be formed by, for example, Reactive Ion Etching (RIE) techniques (FIG. 2B).
콘택트 홀이 형성되면, 도 1c에 도시한 바와 같이, 세정 및 베리어 메탈 공정을 통해 도전물질, 즉, W(텅스텐)(16)를 콘택트 홀내에 매립한다.When the contact hole is formed, a conductive material, that is, W (tungsten) 16 is embedded in the contact hole through a cleaning and barrier metal process, as shown in FIG. 1C.
이후, CMP 공정 등을 거쳐 콘택트 홀 형성 과정이 완료된다.Thereafter, the contact hole forming process is completed through a CMP process.
그런데, 이러한 콘택트 홀 형성 공정에서는 CVD W의 우수한 갭필 능력에도 불구하고 콘택트 홀이 오픈(open)되지 않는 경우가 종종 발생하는데, 이러한 결과는 소자의 전기적 특성 저하를 초래하고 궁극적으로 반도체 수율을 떨어뜨리는 결과를 낳게된다.However, in such a contact hole forming process, the contact hole often does not open despite the good gap fill capability of the CVD W, which results in deterioration of the electrical characteristics of the device and ultimately decreases the semiconductor yield. Will yield results.
따라서, 콘택트 홀의 구조 변경을 통해 콘택트 홀이 오픈되지 않음으로 인한 공정 에러를 방지할 수 있는 기술이 요망된다.Therefore, there is a need for a technique capable of preventing a process error caused by the contact hole not being opened by changing the structure of the contact hole.
본 발명은 상술한 요망에 의해 안출한 것으로, 1차 포토레지스트를 도포한 후 RIE 기법으로 층간 절연막을 10 내지 90% 1차 식각하고, 콘택트 홀내에 포토레지스트가 이격된 형태로 도포되게 2차 포토레지스트를 도포한 후 층간 절연막을 2차 식각하여 반전된 요(凹)자 형태의 콘택트 홀을 형성하여 콘택트 홀을 이중화함으로써, 신호 전달 신뢰성 향상에 의한 높은 반도체 수율을 구현하도록 한 반도체 제조 공정에서의 콘택트 홀 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made in accordance with the above-described requirements, and after the primary photoresist is applied, the secondary insulating film is 10-90% primary etched by the RIE technique and the photoresist is spaced apart in the contact hole. In the semiconductor fabrication process, after the resist is applied, the interlayer insulating film is secondly etched to form inverted concave contact holes to double the contact holes, thereby achieving high semiconductor yield by improving signal transmission reliability. It is an object of the present invention to provide a method for forming a contact hole.
이러한 목적을 달성하기 위하여 본 발명은, 금속 배선용 콘택트 홀을 형성하는 방법으로서, 기판 상부에 하부 금속층과 IMD층을 형성하는 단계와, 하부 금속층과 IMD층 상부에 제 1 포토레지스트를 도포하여 제 1 포토레지스트 패턴을 형성한 후 IMD층을 기설정 범위까지 식각하여 제 1 콘택트 홀을 형성하는 단계와, 제 1 콘택트 홀과 IMD층 상부에 제 2 포토레지스트를 도포하여 제 2 포토레지스트 패턴을 형성하는 단계와, 제 2 포토레지스트 패턴으로 IMD층과 하부 금속층을 오픈하여 제 2 콘택트 홀을 형성하는 단계와, 오픈된 제 2 콘택트 홀 내에 금속을 매립하여 금속층을 형성하는 단계를 포함하는 반도체 제조 공정에서의 콘택트 홀 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a method for forming a contact hole for metal wiring, forming a lower metal layer and an IMD layer on the upper substrate, and applying a first photoresist on the lower metal layer and the IMD layer to the first Forming a first contact hole by etching the IMD layer to a predetermined range after forming the photoresist pattern, and forming a second photoresist pattern by applying a second photoresist on the first contact hole and the IMD layer. And forming a second contact hole by opening an IMD layer and a lower metal layer with a second photoresist pattern, and filling a metal in the open second contact hole to form a metal layer. A method of forming a contact hole is provided.
도 1a 내지 도 1c는 통상의 콘택트 홀 형성 과정을 설명하기 위한 도면,1A to 1C are views for explaining a conventional contact hole forming process,
도 2a 내지 도 2d는 본 발명에 따른 이중 콘택트 홀 형성 과정을 설명하기 위한 도면,2A to 2D are views for explaining a process of forming a double contact hole according to the present invention;
도 3a는 도 2c의 A-B간의 단면 상부 평면도,Figure 3a is a cross-sectional top plan view between A-B of Figure 2c,
도 3b는 도 2c의 C-D간의 단면 상부 평면도.3B is a cross-sectional top plan view of the C-D of FIG. 2C.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 금속층10: metal layer
12 : 층간 절연막(IMD)12: interlayer insulating film (IMD)
14 : 포토레지스트14 photoresist
16 : W16: W
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
설명에 앞서, 본 발명의 핵심 기술 요지는 1차 포토레지스트를 도포한 후 RIE 기법으로 층간 절연막, 즉 IMD층을 10 내지 90% 1차로 식각하고, 2차 포토레지스트를 도포한 후 IMD층을 2차 식각함으로써, 반전된 요(凹)자 형태의 콘택트 홀을 형성한다는 것으로, 이러한 기술 사상으로부터 본 발명에서 목적으로 하는 바를 용이하게 달성할 수 있을 것이다.Prior to the description, the key technical gist of the present invention is to apply the primary photoresist, and then to etch the interlayer insulating film, that is, the IMD layer by 10 to 90% primary by RIE technique, and apply the secondary photoresist to By forming the inverted concave contact holes by the difference etching, it is possible to easily achieve the object of the present invention from this technical idea.
도 2a 내지 도 2d는 본 발명에 따른 이중 콘택트 홀 형성 과정을 설명하기 위한 도면이다.2A to 2D are views for explaining a process of forming a double contact hole according to the present invention.
먼저, 본 과정은 상술한 도 1a의 포토레지스트 도포 과정이 전제된다. 즉, 금속층(10)과 층간 절연막(12)이 증착된 웨이퍼상에 포토레지스트(14)를 도포한 후 사진 공정에 의해 포토레지스트 패턴을 형성하는 공정이 전제되는 것이다.First, this process is premised on the photoresist coating process of FIG. 1A described above. That is, a process of forming the photoresist pattern by a photolithography process after applying the photoresist 14 on the wafer on which the metal layer 10 and the interlayer insulating layer 12 are deposited is assumed.
포토레지스트 패턴이 형성되면 RIE 기법에 의해 층간 절연막(12)을 식각하여 콘택트 홀을 1차로 형성한다.When the photoresist pattern is formed, the interlayer insulating layer 12 is etched by RIE to form a contact hole primarily.
도 2a는 이러한 식각 공정에 의해 1차 콘택트 홀이 형성된 결과를 도시한 도면이다. 도 2a에 도시한 바와 같이, 본 발명에 따른 기법은, 금속층(20)이 드러나지 않도록 층간 절연막(22)을 일부까지, 예를 들어, 10 내지 90%까지만 1차로 식각한 것을 특징으로 한다.FIG. 2A illustrates a result of primary contact holes being formed by such an etching process. As shown in FIG. 2A, the technique according to the present invention is characterized in that the interlayer insulating film 22 is primarily etched up to a part, for example, 10 to 90% so that the metal layer 20 is not exposed.
이후, 도 2b에서는 층간 절연막(22)상에 2차 포토레지스트(24)를 도포한다. 이러한 2차 포토레지스트(24)는 선행된 1차 포토레지스트(14)의 형태에 부가하여 콘택트 홀내에 이격된 형태로 도포되는 것을 특징으로 한다.Subsequently, in FIG. 2B, the secondary photoresist 24 is coated on the interlayer insulating layer 22. The secondary photoresist 24 is characterized in that it is applied in the form of spaced apart in the contact hole in addition to the form of the preceding primary photoresist 14.
도 2c는 이러한 2차 포토레지스트(24)를 패턴으로 하여 금속층(20)까지 2차 RIE 식각한 결과를 도시한 도면이다.FIG. 2C is a view illustrating a result of secondary RIE etching up to the metal layer 20 using the secondary photoresist 24 as a pattern.
도 2c에 도시한 바와 같이, 2차 포토레지스트(24)의 패턴에 의해 층간 절연막(22)이 식각되어 이중화된 콘택트 홀, 즉, 반전된 요(凹)자 형태의 콘택트 홀이 형성됨을 알 수 있다. 이러한 이중화된 콘택트 홀은 콘택트와 콘택트 사이의 유전체를 직렬로 연결할 수 있기 때문에 IMD 캐패시턴스를 줄일 수 있으며, 부수적으로 RC 릴레이를 개선할 수 있을 것이다.As shown in FIG. 2C, it can be seen that the interlayer insulating film 22 is etched by the pattern of the secondary photoresist 24 to form a redundant contact hole, that is, an inverted concave contact hole. have. This redundant contact hole can reduce the IMD capacitance and concomitantly improve the RC relay because the dielectric between the contact and the contact can be connected in series.
도 3a는 도 2c의 A-B간의 단면 상부 평면도이며, 도 3b는 도 2c의 C-D간의 단면 상부 평면도이다.3A is a cross-sectional top plan view between A-B of FIG. 2C, and FIG. 3B is a cross-sectional top plan view of C-D of FIG. 2C.
이와 같은 이중화된 콘택트 홀이 형성되면, 도 2d에 도시한 바와 같이, 세정 및 베리어 메탈 공정을 통해 도전물질, 즉, W(26)를 이중화된 콘택트 홀내에 매립한다.When the redundant contact hole is formed, the conductive material, that is, the W 26 is buried in the redundant contact hole through the cleaning and barrier metal process, as shown in FIG. 2D.
이후, CMP 공정 등을 거쳐 본 실시예에 따른 이중화된 콘택트 홀 형성 과정이 완료된다.Thereafter, the redundant contact hole forming process according to the present embodiment is completed through a CMP process or the like.
본 발명에 의하면, 콘택트 홀을 이중화함으로써 신호 전달 신뢰성 향상에 의한 높은 반도체 수율을 구현할 수 있는 효과가 있다.이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 그 요지를 벗어나지 않는 범위내에서 여러 가지 변형이 가능한 것은 물론이다.According to the present invention, it is possible to realize a high semiconductor yield by improving the signal transmission reliability by redundancy of the contact hole. Although the present invention has been described in detail based on the embodiments, the present invention is limited to these embodiments. Of course, various modifications are possible without departing from the gist of the invention.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0086940A KR100459062B1 (en) | 2001-12-28 | 2001-12-28 | Method for forming a contact hole in a semiconductor manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0086940A KR100459062B1 (en) | 2001-12-28 | 2001-12-28 | Method for forming a contact hole in a semiconductor manufacturing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030056662A KR20030056662A (en) | 2003-07-04 |
| KR100459062B1 true KR100459062B1 (en) | 2004-12-03 |
Family
ID=32214839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0086940A KR100459062B1 (en) | 2001-12-28 | 2001-12-28 | Method for forming a contact hole in a semiconductor manufacturing process |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100459062B1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0823028A (en) * | 1994-07-05 | 1996-01-23 | Oki Electric Ind Co Ltd | Semiconductor device having multilayer interconnect and manufacture thereof |
| KR0124638B1 (en) * | 1994-05-02 | 1997-12-11 | 문정환 | Manufacturing method of multilayer lining for semiconductor device |
| KR19980057696A (en) * | 1996-12-30 | 1998-09-25 | 김광호 | Metal wiring layer formation method of semiconductor device |
| KR20010047961A (en) * | 1999-11-24 | 2001-06-15 | 윤종용 | method to shape line first dual damascene pattern use the oxide mask |
| JP2002134612A (en) * | 2000-10-26 | 2002-05-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
-
2001
- 2001-12-28 KR KR10-2001-0086940A patent/KR100459062B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0124638B1 (en) * | 1994-05-02 | 1997-12-11 | 문정환 | Manufacturing method of multilayer lining for semiconductor device |
| JPH0823028A (en) * | 1994-07-05 | 1996-01-23 | Oki Electric Ind Co Ltd | Semiconductor device having multilayer interconnect and manufacture thereof |
| KR19980057696A (en) * | 1996-12-30 | 1998-09-25 | 김광호 | Metal wiring layer formation method of semiconductor device |
| KR20010047961A (en) * | 1999-11-24 | 2001-06-15 | 윤종용 | method to shape line first dual damascene pattern use the oxide mask |
| JP2002134612A (en) * | 2000-10-26 | 2002-05-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030056662A (en) | 2003-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR19990037532A (en) | Method for manufacturing a semiconductor device having a dual damascene structure | |
| KR100554210B1 (en) | Dual damascene with self aligned via interconnects | |
| KR100342639B1 (en) | Method of fabricating a semiconductor structure | |
| KR100459062B1 (en) | Method for forming a contact hole in a semiconductor manufacturing process | |
| KR100528070B1 (en) | Method for fabricating contact hole and stack via | |
| US20020048902A1 (en) | Method for forming overlay verniers for semiconductor devices | |
| KR100668221B1 (en) | Method for Manufacturing MIM Capacitor | |
| KR100352304B1 (en) | Semiconductor device and method of manufacturing the same | |
| KR100607753B1 (en) | Method for forming a metal layer of semiconductor device | |
| KR100278274B1 (en) | A method for forming stack contact in semiconductor device | |
| KR100784074B1 (en) | Method of manufacturing bit line in a semiconductor device | |
| KR100398584B1 (en) | Method for manufacturing semiconductor device | |
| KR100395907B1 (en) | Method for forming the line of semiconductor device | |
| KR100408683B1 (en) | Method for forming contact of semiconductor device | |
| KR100422912B1 (en) | Method for forming contact or via hole of semiconductor devices | |
| KR100439477B1 (en) | Fabricating method of Tungsten plug in semiconductor device | |
| US20070148986A1 (en) | Semiconductor device and method for manufacturing same | |
| KR100265972B1 (en) | Method for forming mutilayer og semiconductor device | |
| KR100564122B1 (en) | Manufacturing method for semiconductor device by damascene tungten plug process | |
| KR100248805B1 (en) | A method for forming metal wire in semiconductor device | |
| KR100338605B1 (en) | Method for forming contact hole of semiconductor | |
| KR100268810B1 (en) | Manufacturing method of metal line of semiconductor device | |
| KR19990055175A (en) | Metal wiring formation method of semiconductor device | |
| KR20050032308A (en) | Method of forming metal line in semiconductor devices | |
| KR20000042001A (en) | Method forming metal distribution layer of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| AMND | Amendment | ||
| E601 | Decision to refuse application | ||
| J201 | Request for trial against refusal decision | ||
| AMND | Amendment | ||
| B701 | Decision to grant | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20111020 Year of fee payment: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20121026 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |