KR100194600B1 - Manufacturing method of multilayer metal wiring - Google Patents

Abstract

The present invention relates to a method for manufacturing a multi-layer metal wiring, in order to solve the problems such as electromigration due to the complete metal step coverage in the manufacturing of ultra-high-density (ULSI) device of the prior art, in the formation of a plurality of metal wiring, via inverted via Solving problems such as electromigration and controlling the thickness of the intermetallic insulating layer by providing a method of manufacturing a multilayer metal wiring, characterized in that the first pillar is formed, the conductive layer is formed later, and the planarization is performed. This feature reduces parasitic capacitance and reduces via resistance.

Description

Manufacturing method of multilayer metal wiring

(A)-(c) of FIG. 1 is a manufacturing process chart for manufacturing the multilayer metal wiring of the semiconductor device of the prior art.

(A) to (f) of FIG. 2 is a manufacturing process diagram of the multi-layered metal wiring of the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 insulating film

3: gate electrode 4: diffusion region

6: interlayer insulating film 11, 21: first and second barrier metal layers

12, 22: first and second metal layers

13: first etch endpoint detection layer and the first metal layer reflective reduction film

23: second metal layer reflection reducing film 14: metal layer for pillar

14 ': Pillar 15: Metal layer reflective film for pillar

16: column region defining photoresist layer 17: first conductive layer defining photoresist layer

18: first interlayer insulating film

19: Consumable photoresist or spin-on-glass layer for planarization

20: first conductive layer 30: second conductive layer

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a multi-layered metal wiring, particularly in the manufacture of a multi-layered metal wiring of an ultra high integration (ULSI) device, first forming a pillar by a reverse via hole, and then forming a conductive layer later. It relates to a multi-layer metal wiring manufacturing method characterized in that to perform a planarization after.

In general, the determination of IC chip size using sub-micron devices is determined by design rules that allow for manufacturing processes.

Most of them are determined by the pitch of the metal for inter-element wiring.

The solution to this problem is the metal multi-layer wiring method, which can realize multifunction and high performance by seeking design flexibility and increasing integration density by reducing chip area.

However, this multilayer wiring method has various problems.

First, due to the low melting point of metals (eg Al), low temperature process is required to be below 500 ° C. Therefore, plasma chemical vapor deposition (PECVD) is mainly used as inter-metal dielectric (IMD). have.

Secondly, a deposition method of metals, in particular, a method of connecting metals through via holes has become a problem.

In other words, in order to reduce the parasitic capacitance naturally occurring in the silicon substrate, the gate, the lower metal line, and the like, a thick intermetallic insulating film is required, thereby increasing the aspect ratio, which is a ratio between the via hole size and the intermetallic insulating film thickness.

However, when the aspect ratio is increased, when the sputter method, which is a conventional physical metal deposition method, is used, the thickness of the metal deposited on the wall of the via hole is thin, causing serious electrical problems such as electromigration, and chemical vapor deposition. Although a method of forming a used plug or the like is used, this also has problems such as a decrease in yield due to unnecessary area defects.

Third, there is a problem of pattern formation technology of metal film with high reflectivity and metal profile control technology by dry etching, besides, improvement of via resistance and low yield due to particle problem due to the heating process. There is a problem to be solved in the conventional multilayer wiring technology.

An embodiment of the method for manufacturing a multi-layer metal wiring according to the related art (forms up to secondary gold wiring) according to the related art will be described with reference to FIG.

First, (a) process is as follows.

An n ⁺ region doped with phosphorus (P) or bis (As) or a p ⁺ region doped with boron (B) is formed on the silicon substrate 1, and at a predetermined position on the silicon substrate 1. An isolation insulating film 2 is formed.

Thereafter, a gate electrode 3 is formed on the silicon substrate 1, and a contact window 5 is formed on an upper surface of the gate electrode 3 and an upper surface of the n ⁺ region or the p ⁺ region 4.

In this case, both ends of the gate electrode 3 have sidewalls.

An interlayer insulating film (ILD: LTO or BPSG) 6 is formed on the entire surface of the upper portion of the structure, and the portion of the interlayer insulating film 6 to be formed of the primary metal is etched by conventional lithography, followed by Ti / TiN, TiW. A primary metal wiring 7 comprising a barrier metal layer 7a using a metal film such as MoSix, a metal layer 7b using Al, and a reflection reducing film 7c.

Then, a predetermined region of the primary metal wiring 7 is formed through a lithography process.

(b) The process deposits an intermetal interconnection film (mainly using a PEVCD oxide film) 8 to form a via hole for connection with the secondary metal wiring 10, and deposits the via hole region 9a. Defined by a lithography process, a via hole is formed by removing the intermetallic insulating film 8 and a photosensitive agent (not shown).

In this case, reference numeral 9 denotes a portion where the primary metal wiring 7 and the secondary metal wiring 10 to be described later contact.

(c) The second metal is formed of the barrier metal layer 10a, the metal layer 10b, and the reflection reducing film 10c in the same manner as the method of forming the primary metal wiring 7 after the via hole is completed. After depositing the wiring 10 and defining a region of the secondary metal wiring 10 through a lithography process, an etching process and a photoresist (not shown) are removed.

As described above, the prior art processes are performed in the order of the primary metal, the via hole, and the secondary metal in order to perform multilayer metal wiring.

In the prior art, in the manufacture of ultra-high integrated (ULSI) devices, a portion where a secondary metal is deposited (reference A) becomes thin and an electromigration phenomenon occurs, and a contact portion between a primary metal and a secondary metal (reference 9) ), The via resistance becomes large, and the flatness of the insulating film 8 between the metal wires is deteriorated, so that the multilayer metal wiring is difficult (due to the cracking of the metal and the electric short circuit due to the metal residue). Etc.) There were problems.

Accordingly, the present invention provides a method of manufacturing a multilayer metal wiring for wiring multilayer metal by first forming a pillar having a reverse phase of a via hole and forming a metal wiring later, and then performing planarization to solve the above problem. The purpose is.

A technical feature of the present invention for achieving the above object is a semiconductor substrate of a first conductive type, an isolation insulating film defining an element region in a predetermined portion of the surface of the semiconductor substrate, and a gate on the semiconductor substrate between the insulating insulating film. A gate electrode formed through an oxide film, a second conductive diffusion region formed on a semiconductor substrate on both sides of the gate electrode, and an interlayer insulating film formed to expose the diffusion region. The method may further include forming a first conductive layer on the interlayer insulating layer to contact the diffusion region and the gate, and a conductive pillar electrically connected to the first conductive layer on a predetermined portion of the first conductive layer. And forming a first interlayer insulating film so that the pillar is covered on the first conductive layer, and forming a photoresist layer or A planarization process for applying a SOG layer, and removing the photoresist layer or the spin-on-glass layer and the first interlayer insulating film so that the surface of the first interlayer insulating film is flat so that the top of the pillar is exposed. And forming a second conductive layer in contact with the pillar on top of the first interlayer insulating film.

Hereinafter, the formation process up to the second conductive layer based on the present invention will be described in detail.

Method for manufacturing a multi-layered metal wiring according to the present invention is as shown in (a) to (f) of FIG.

First, the step (a) is performed between the silicon substrate 1 of the first conductivity type, the isolation insulating film 2 defining the element region at a predetermined portion of the silicon substrate 1 surface, and the isolation insulating film 2. A gate electrode 3 formed on the silicon substrate 1 with a gate oxide film 3 'interposed therebetween, and a diffusion region of a second conductivity type formed on the silicon substrate 1 on both sides of the gate electrode 3 (for example, n). ⁺ Region or p ⁺ region) 4, an interlayer insulating film (ILD) 6 formed to expose the diffusion region 4, and contacting the diffusion region 4 on the interlayer insulating film 6 The first barrier metal layer 11 using metals such as Ti / TiN, TiW, MoSix, etc., the first metal layer 12 using Al, Cu, etc., and the end point of etching during reflection removal and pillar formation forming a first conductive layer 20 comprising a first etch endpoint detection layer 13 for sensing a -point, and sequentially depositing the pillar metal layer 14 and the pillar metal layer reflection reducing film 15 thereon. It is a step.

Here, the first etching endpoint detection layer 13 is a layer used to reduce the reflectivity of the metal film to define a metal wiring of a desired size in a lithography process, which is the next process, and a metal film such as TiN, TiW, MoSix, etc. is used ( Using a material similar to the first barrier metal layer (11).

In the next step (b), the pillar region is formed by using a reverse image or a reverse mask of a via hole using the pillar region defining photoresist layer 16 on a predetermined portion of the first conductive layer 20. After defining, the conductive pillar 14 ′ is formed by etching only a predetermined portion of the pillar metal layer reflection reducing film 15 and the pillar metal layer 14 corresponding to the shape of the pillar region defining photoresist layer 16. It is a process to do it.

At this time, the thickness of the first interlayer insulating film 18 to be formed later is adjusted according to the height of the pillar 14 '.

The step (c) is performed by applying a predetermined portion of the first conductive layer 20 and the pillars 14 'to the first conductive layer defining photoresist layer 17, and then applying the uncoated first conductive layer ( 20) is the process of completing the primary wiring by etching.

Step (d) is a step for forming an insulating film on the primary wiring formed in step (c), and the first interlayer layer is formed by a PECVD oxide film using plasma, which is an insulating film that can be deposited at a low temperature (about 400 ° C or less). An insulating film 18 is formed to cover the pillar 14 'on the first conductive layer 20, and a consumable photoresist layer or spin-on-glass layer (SOG) for planarization thereon. 19).

And (e) process is to expose the top of the pillar (14 '), such as chemical-mechanical polishing (CMP: chemical polishing) or spin-on-glass (SOG), etch back (Etch back), Alternatively, the first interlayer insulating film 18 and the photoresist layer or the spin-on-glass layer 19 are removed using a photoresist etch back lamp. At this time, the surface of the first interlayer insulating film 18 is made flat.

In order to form a multi-layered metal wiring, the above-described metal layer deposition step to the surface planarization step of the first interlayer insulating film 18 are repeatedly performed, and the metal wiring layer is formed as many times as the number of repetitions. Multi-layer metal wiring is achieved.

Finally, the step (f) forms the second conductive layer 30 (herein, the final wiring layer) on the top of the first interlayer insulating film 18 planarized in the step (e) so as to contact the pillar 14 '. It is a process to do it.

The second conductive layer 30 is formed by sequentially forming the second barrier metal layer 21, the second metal layer 22, and the second metal layer reflection reducing film 23.

Accordingly, the first conductive layer 20 is connected to the second conductive layer 30 through the pillar 14 ′, which is the reverse phase of the via hole, and a plurality of other conductive layers are formed by the pillar formed in the same manner as in the manufacturing process. Since they can be connected to each other, multilayer metal wiring can be performed.

As described above, the present invention solves problems such as electromigration due to perfect metal step coverage in manufacturing an ultra-high integration (ULSI) device, and enables to control the thickness of the intermetallic insulating layer, thereby greatly reducing parasitic capacitance, and via hole resistance. It has the effect of decrease.

Claims (2)

A semiconductor substrate of a first conductivity type, an isolation insulating film defining an element region at a predetermined portion of the surface of the semiconductor substrate, a gate electrode formed on a semiconductor substrate between the isolation insulating films via a gate oxide film, and both sides of the gate electrode. A method of manufacturing a multilayer metal interconnection of a semiconductor device comprising a diffusion region of a second conductivity type formed in a semiconductor substrate and an interlayer insulating film formed to expose the diffusion region, wherein the diffusion region is destroyed on top of the interlayer insulating film. A first step of forming a metal wiring having a three-layer structure in which a barrier metal layer and a reflective deceleration film layer are deposited before and after the metal layer to be in contact with the diffusion region; and an inverse or opposite shape of a via hole in the upper portion of the metal wiring formed in the first step. The second step of forming a conductive pillar using a mask, and the predetermined portion of the metal wiring and the pillar A third process of applying a toresist layer and then exposing to complete the first conductive layer; and forming a first insulating layer on the finished first conductive layer, and forming a first insulating layer on the entire first upper surface of the structure formed in the third process. A fourth step of depositing an interlayer insulating film and applying a photoresist layer or spin-on-glass layer, and the photoresist layer or spin-on-glass layer applied in the fourth step to expose the upper portion of the pillar. And a fifth step of removing the first interlayer insulating film and making the surface of the first interlayer insulating film flat, and a sixth step of forming a second conductive layer in contact with the pillar on the first interlayer insulating film. Multi-layer metallization manufacturing method. The multi-layered metal according to claim 1, wherein the fifth step removes the first interlayer insulating film until the pillars have the same height so that the height of the first interlayer insulating layer is the same as the height of the pillar. Wiring manufacturing method.